Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	696816	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5866526

1

T1

41

T2

23

T3

51

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1714989	1			T1	47		T2	35		T3	36
values[0x0]	2240054	1			T1	27		T2	14		T3	25
values[0x1]	2608299	1			T1	20		T2	11		T3	28

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	338998	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

6224344

1

T1

52

T2

34

T3

57

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27025	1			T4	462		T26	1		T21	1
valid_sources[0x01]	26627	1			T4	813		T26	2		T41	225
valid_sources[0x02]	24756	1			T4	638		T41	223		T42	836
valid_sources[0x03]	26467	1			T4	450		T26	1		T41	234
valid_sources[0x04]	25342	1			T4	565		T46	1		T41	225
valid_sources[0x05]	26499	1			T4	475		T41	222		T56	1
valid_sources[0x06]	25751	1			T3	1		T4	578		T26	1
valid_sources[0x07]	26169	1			T4	429		T13	134		T41	204
valid_sources[0x08]	25348	1			T4	567		T21	1		T41	218
valid_sources[0x09]	24433	1			T17	1		T4	626		T27	1
valid_sources[0x0a]	25113	1			T4	599		T26	1		T21	2
valid_sources[0x0b]	25843	1			T4	473		T21	1		T73	1
valid_sources[0x0c]	26312	1			T4	546		T41	224		T24	1
valid_sources[0x0d]	25311	1			T4	556		T26	1		T41	196
valid_sources[0x0e]	25414	1			T4	300		T22	1		T41	197
valid_sources[0x0f]	25669	1			T4	395		T26	1		T46	1
valid_sources[0x10]	25326	1			T4	631		T27	2		T41	235
valid_sources[0x11]	27168	1			T4	688		T25	6		T41	205
valid_sources[0x12]	24402	1			T1	1		T4	473		T21	2
valid_sources[0x13]	24803	1			T4	581		T46	1		T41	235
valid_sources[0x14]	25482	1			T4	840		T26	1		T21	1
valid_sources[0x15]	25818	1			T4	484		T6	3		T41	199
valid_sources[0x16]	24863	1			T4	424		T26	1		T41	219
valid_sources[0x17]	23731	1			T4	521		T41	213		T44	1
valid_sources[0x18]	25211	1			T2	4		T4	482		T26	1
valid_sources[0x19]	25491	1			T4	664		T26	2		T22	1
valid_sources[0x1a]	27301	1			T4	538		T26	1		T41	234
valid_sources[0x1b]	27424	1			T4	636		T41	234		T42	850
valid_sources[0x1c]	25329	1			T3	1		T4	460		T41	227
valid_sources[0x1d]	25230	1			T4	565		T41	203		T42	872
valid_sources[0x1e]	25201	1			T4	555		T41	167		T106	2
valid_sources[0x1f]	25163	1			T4	691		T26	1		T27	5
valid_sources[0x20]	26321	1			T4	473		T21	1		T41	206
valid_sources[0x21]	25688	1			T4	595		T41	246		T42	796
valid_sources[0x22]	24526	1			T3	1		T4	480		T73	1
valid_sources[0x23]	25811	1			T2	5		T4	545		T46	1
valid_sources[0x24]	23588	1			T17	42		T4	372		T26	3
valid_sources[0x25]	28361	1			T3	1		T4	348		T41	236
valid_sources[0x26]	26753	1			T4	468		T26	2		T41	222
valid_sources[0x27]	27110	1			T3	1		T4	457		T41	212
valid_sources[0x28]	26007	1			T4	322		T73	1		T41	209
valid_sources[0x29]	25616	1			T3	2		T4	398		T21	1
valid_sources[0x2a]	23955	1			T17	1		T4	487		T41	250
valid_sources[0x2b]	25415	1			T3	1		T4	442		T21	1
valid_sources[0x2c]	25281	1			T4	487		T41	211		T24	6
valid_sources[0x2d]	26342	1			T4	522		T41	197		T24	5
valid_sources[0x2e]	24145	1			T4	395		T21	2		T36	3
valid_sources[0x2f]	24821	1			T4	562		T41	248		T51	2
valid_sources[0x30]	24911	1			T17	1		T4	555		T26	1
valid_sources[0x31]	24274	1			T4	352		T73	1		T41	195
valid_sources[0x32]	26443	1			T4	598		T21	1		T41	238
valid_sources[0x33]	25842	1			T4	498		T21	1		T41	209
valid_sources[0x34]	25842	1			T4	557		T26	1		T21	1
valid_sources[0x35]	25525	1			T4	383		T26	1		T41	233
valid_sources[0x36]	27033	1			T4	797		T41	226		T105	1
valid_sources[0x37]	25371	1			T4	415		T41	214		T342	1
valid_sources[0x38]	25610	1			T4	578		T22	1		T41	236
valid_sources[0x39]	24678	1			T4	519		T21	1		T73	1
valid_sources[0x3a]	27208	1			T1	1		T4	630		T46	3
valid_sources[0x3b]	26056	1			T17	1		T4	522		T26	1
valid_sources[0x3c]	25405	1			T4	583		T26	1		T41	211
valid_sources[0x3d]	23436	1			T2	2		T3	1		T4	488
valid_sources[0x3e]	27582	1			T2	1		T3	1		T4	591
valid_sources[0x3f]	25928	1			T4	579		T22	1		T41	229
valid_sources[0x40]	25710	1			T3	1		T4	354		T73	1
valid_sources[0x41]	26242	1			T1	3		T2	1		T4	562
valid_sources[0x42]	24778	1			T2	1		T4	412		T26	2
valid_sources[0x43]	26309	1			T2	2		T4	709		T26	1
valid_sources[0x44]	28808	1			T4	467		T41	234		T24	3
valid_sources[0x45]	25704	1			T2	3		T4	573		T41	212
valid_sources[0x46]	26334	1			T17	1		T4	552		T22	6
valid_sources[0x47]	24426	1			T4	563		T26	1		T27	1
valid_sources[0x48]	25955	1			T4	497		T41	221		T306	1
valid_sources[0x49]	24674	1			T4	600		T14	1		T41	215
valid_sources[0x4a]	25588	1			T3	4		T4	591		T26	1
valid_sources[0x4b]	26224	1			T4	547		T21	1		T41	196
valid_sources[0x4c]	25515	1			T17	1		T4	526		T26	2
valid_sources[0x4d]	25604	1			T4	500		T26	1		T6	10
valid_sources[0x4e]	26284	1			T4	514		T26	1		T27	1
valid_sources[0x4f]	25987	1			T17	2		T4	661		T26	2
valid_sources[0x50]	26741	1			T1	1		T17	1		T4	640
valid_sources[0x51]	26904	1			T4	690		T21	1		T41	210
valid_sources[0x52]	26736	1			T2	1		T4	322		T73	1
valid_sources[0x53]	25503	1			T4	359		T22	1		T41	208
valid_sources[0x54]	25876	1			T3	5		T4	464		T26	1
valid_sources[0x55]	24812	1			T4	523		T26	1		T22	3
valid_sources[0x56]	26071	1			T4	427		T26	1		T21	1
valid_sources[0x57]	24993	1			T17	1		T4	379		T22	1
valid_sources[0x58]	25787	1			T4	564		T26	1		T41	207
valid_sources[0x59]	24922	1			T17	1		T4	659		T46	4
valid_sources[0x5a]	25308	1			T17	2		T4	620		T26	4
valid_sources[0x5b]	25395	1			T1	1		T2	1		T4	503
valid_sources[0x5c]	25246	1			T4	606		T14	1		T41	219
valid_sources[0x5d]	27253	1			T4	777		T26	1		T41	219
valid_sources[0x5e]	25564	1			T3	1		T4	477		T73	1
valid_sources[0x5f]	24964	1			T4	555		T73	1		T41	218
valid_sources[0x60]	25894	1			T4	655		T41	221		T306	4
valid_sources[0x61]	25297	1			T3	1		T4	636		T21	1
valid_sources[0x62]	24116	1			T4	468		T26	2		T41	218
valid_sources[0x63]	26054	1			T3	1		T4	655		T26	1
valid_sources[0x64]	25821	1			T3	1		T17	2		T4	414
valid_sources[0x65]	26166	1			T4	469		T41	191		T24	3
valid_sources[0x66]	24554	1			T4	543		T26	1		T21	1
valid_sources[0x67]	28254	1			T4	632		T26	2		T21	2
valid_sources[0x68]	26252	1			T4	461		T26	1		T21	2
valid_sources[0x69]	25393	1			T1	65		T17	1		T4	528
valid_sources[0x6a]	24106	1			T2	1		T4	546		T46	1
valid_sources[0x6b]	26970	1			T2	2		T4	533		T26	1
valid_sources[0x6c]	27301	1			T4	603		T41	203		T56	2
valid_sources[0x6d]	26313	1			T1	1		T2	2		T4	531
valid_sources[0x6e]	26156	1			T2	4		T4	497		T27	1
valid_sources[0x6f]	26928	1			T4	612		T26	1		T41	216
valid_sources[0x70]	25240	1			T4	419		T21	1		T41	251
valid_sources[0x71]	24495	1			T4	477		T26	1		T41	262
valid_sources[0x72]	25917	1			T2	2		T4	386		T27	2
valid_sources[0x73]	24293	1			T4	573		T26	1		T21	1
valid_sources[0x74]	26548	1			T1	1		T4	422		T41	224
valid_sources[0x75]	26923	1			T4	530		T21	1		T41	226
valid_sources[0x76]	27245	1			T4	486		T26	1		T21	1
valid_sources[0x77]	25642	1			T4	486		T41	204		T37	1
valid_sources[0x78]	25364	1			T4	568		T21	1		T41	218
valid_sources[0x79]	27295	1			T3	4		T4	469		T46	1
valid_sources[0x7a]	23986	1			T4	546		T26	1		T41	194
valid_sources[0x7b]	27077	1			T4	706		T26	1		T6	6
valid_sources[0x7c]	26281	1			T3	1		T4	332		T26	1
valid_sources[0x7d]	24812	1			T4	542		T22	2		T41	249
valid_sources[0x7e]	26949	1			T4	545		T26	1		T21	1
valid_sources[0x7f]	27388	1			T3	2		T4	311		T26	1
valid_sources[0x80]	26278	1			T4	415		T26	1		T27	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1474613

1

T1

9

T2

11

T3

12

values[0x0]

all_enables

biggest_size

2195055

1

T1

18

T2

8

T3

20

values[0x1]

all_enables

biggest_size

2196858

1

T1

14

T2

4

T3

19