Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
62.50	62.50	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	62.50	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	24	28	53.85

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	24	28	53.85	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2394	1			T4	11		T26	1		T27	2
non_zero_bins[1]	1797	1			T4	6		T26	2		T13	3
zero	8429	1			T1	5		T2	4		T3	5

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	492	1			T4	4		T26	1		T27	1
uni	3265	1			T4	17		T26	1		T27	2
gen	4069	1			T1	3		T2	2		T3	3
res	797	1			T13	2		T23	1		T5	1
ins	3997	1			T1	2		T2	2		T3	2

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

8256

1

T1

2

T2

1

T3

2

mubi_true

4364

1

T1

3

T2

3

T3

3

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

16

1

T79

1

T287

1

T151

1

pass

12604

1

T1

5

T2

4

T3

5

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	24	28	53.85	24
Automatically Generated Cross Bins	52	24	28	53.85	24
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	*	[fail]	*	--	--	6

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	105	1			T4	1		T41	3		T104	1
upd	non_zero_bins[0]	pass	mubi_true	121	1			T27	1		T42	5		T50	1
upd	non_zero_bins[1]	pass	mubi_false	91	1			T4	1		T26	1		T42	4
upd	non_zero_bins[1]	pass	mubi_true	81	1			T4	1		T41	2		T42	1
upd	zero	pass	mubi_false	57	1			T4	1		T42	1		T72	1
upd	zero	pass	mubi_true	37	1			T83	1		T225	1		T227	1
uni	zero	pass	mubi_false	2442	1			T4	12		T26	1		T27	2
uni	zero	pass	mubi_true	823	1			T4	5		T5	3		T41	16
gen	non_zero_bins[0]	pass	mubi_false	429	1			T41	2		T43	1		T47	1
gen	non_zero_bins[0]	pass	mubi_true	459	1			T4	2		T26	1		T13	17
gen	non_zero_bins[1]	pass	mubi_false	368	1			T4	2		T13	1		T41	3
gen	non_zero_bins[1]	pass	mubi_true	327	1			T4	2		T5	1		T41	2
gen	zero	fail	mubi_false	14	1			T79	1		T287	1		T288	1
gen	zero	pass	mubi_false	1714	1			T1	1		T3	1		T4	5
gen	zero	pass	mubi_true	758	1			T1	2		T2	2		T3	2
res	non_zero_bins[0]	pass	mubi_false	177	1			T41	3		T42	3		T71	2
res	non_zero_bins[0]	pass	mubi_true	194	1			T5	1		T41	1		T24	6
res	non_zero_bins[1]	pass	mubi_false	113	1			T41	2		T42	2		T289	2
res	non_zero_bins[1]	pass	mubi_true	154	1			T13	2		T21	4		T22	2
res	zero	fail	mubi_false	2	1			T151	1		T290	1		-	-
res	zero	pass	mubi_false	87	1			T23	1		T42	3		T64	2
res	zero	pass	mubi_true	70	1			T42	1		T72	1		T241	1
ins	non_zero_bins[0]	pass	mubi_false	462	1			T4	4		T27	1		T13	1
ins	non_zero_bins[0]	pass	mubi_true	447	1			T4	4		T5	2		T41	5
ins	non_zero_bins[1]	pass	mubi_false	331	1			T26	1		T5	2		T41	3
ins	non_zero_bins[1]	pass	mubi_true	332	1			T5	1		T41	1		T43	1
ins	zero	pass	mubi_false	1864	1			T1	1		T2	1		T3	1
ins	zero	pass	mubi_true	561	1			T1	1		T2	1		T3	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded