SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_edn_core.u_prim_mubi4_sync_auto_req_mode | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_edn_core.u_prim_mubi4_sync_boot_req_mode | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
97.28 | 100.00 | 90.88 | 98.23 | 100.00 | u_edn_core |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
97.28 | 100.00 | 90.88 | 98.23 | 100.00 | u_edn_core |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[3].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[3].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[3].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[3].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
97.28 | 100.00 | 90.88 | 98.23 | 100.00 | u_edn_core |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
97.28 | 100.00 | 90.88 | 98.23 | 100.00 | u_edn_core |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 21 | 21 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 20 | 20 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 5 | 5 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 4 | 4 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 3860 | 3860 | 0 | 0 |
OutputsKnown_A | 895753692 | 894971836 | 0 | 0 |
gen_no_flops.OutputDelay_A | 895753692 | 894971836 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 3860 | 3860 | 0 | 0 |
T1 | 4 | 4 | 0 | 0 |
T2 | 4 | 4 | 0 | 0 |
T3 | 4 | 4 | 0 | 0 |
T4 | 4 | 4 | 0 | 0 |
T13 | 4 | 4 | 0 | 0 |
T17 | 4 | 4 | 0 | 0 |
T23 | 4 | 4 | 0 | 0 |
T25 | 4 | 4 | 0 | 0 |
T26 | 4 | 4 | 0 | 0 |
T27 | 4 | 4 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 895753692 | 894971836 | 0 | 0 |
T1 | 11380 | 11136 | 0 | 0 |
T2 | 11244 | 10960 | 0 | 0 |
T3 | 11584 | 11188 | 0 | 0 |
T4 | 2546436 | 2546388 | 0 | 0 |
T13 | 10780 | 10464 | 0 | 0 |
T17 | 7092 | 6772 | 0 | 0 |
T23 | 10292 | 9980 | 0 | 0 |
T25 | 3268 | 3056 | 0 | 0 |
T26 | 10940 | 10540 | 0 | 0 |
T27 | 6004 | 5624 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 895753692 | 894971836 | 0 | 0 |
T1 | 11380 | 11136 | 0 | 0 |
T2 | 11244 | 10960 | 0 | 0 |
T3 | 11584 | 11188 | 0 | 0 |
T4 | 2546436 | 2546388 | 0 | 0 |
T13 | 10780 | 10464 | 0 | 0 |
T17 | 7092 | 6772 | 0 | 0 |
T23 | 10292 | 9980 | 0 | 0 |
T25 | 3268 | 3056 | 0 | 0 |
T26 | 10940 | 10540 | 0 | 0 |
T27 | 6004 | 5624 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 21 | 21 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 20 | 20 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 965 | 965 | 0 | 0 |
OutputsKnown_A | 223938423 | 223742959 | 0 | 0 |
gen_no_flops.OutputDelay_A | 223938423 | 223742959 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 965 | 965 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T23 | 1 | 1 | 0 | 0 |
T25 | 1 | 1 | 0 | 0 |
T26 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 223938423 | 223742959 | 0 | 0 |
T1 | 2845 | 2784 | 0 | 0 |
T2 | 2811 | 2740 | 0 | 0 |
T3 | 2896 | 2797 | 0 | 0 |
T4 | 636609 | 636597 | 0 | 0 |
T13 | 2695 | 2616 | 0 | 0 |
T17 | 1773 | 1693 | 0 | 0 |
T23 | 2573 | 2495 | 0 | 0 |
T25 | 817 | 764 | 0 | 0 |
T26 | 2735 | 2635 | 0 | 0 |
T27 | 1501 | 1406 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 223938423 | 223742959 | 0 | 0 |
T1 | 2845 | 2784 | 0 | 0 |
T2 | 2811 | 2740 | 0 | 0 |
T3 | 2896 | 2797 | 0 | 0 |
T4 | 636609 | 636597 | 0 | 0 |
T13 | 2695 | 2616 | 0 | 0 |
T17 | 1773 | 1693 | 0 | 0 |
T23 | 2573 | 2495 | 0 | 0 |
T25 | 817 | 764 | 0 | 0 |
T26 | 2735 | 2635 | 0 | 0 |
T27 | 1501 | 1406 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 5 | 5 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 4 | 4 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 965 | 965 | 0 | 0 |
OutputsKnown_A | 223938423 | 223742959 | 0 | 0 |
gen_no_flops.OutputDelay_A | 223938423 | 223742959 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 965 | 965 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T23 | 1 | 1 | 0 | 0 |
T25 | 1 | 1 | 0 | 0 |
T26 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 223938423 | 223742959 | 0 | 0 |
T1 | 2845 | 2784 | 0 | 0 |
T2 | 2811 | 2740 | 0 | 0 |
T3 | 2896 | 2797 | 0 | 0 |
T4 | 636609 | 636597 | 0 | 0 |
T13 | 2695 | 2616 | 0 | 0 |
T17 | 1773 | 1693 | 0 | 0 |
T23 | 2573 | 2495 | 0 | 0 |
T25 | 817 | 764 | 0 | 0 |
T26 | 2735 | 2635 | 0 | 0 |
T27 | 1501 | 1406 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 223938423 | 223742959 | 0 | 0 |
T1 | 2845 | 2784 | 0 | 0 |
T2 | 2811 | 2740 | 0 | 0 |
T3 | 2896 | 2797 | 0 | 0 |
T4 | 636609 | 636597 | 0 | 0 |
T13 | 2695 | 2616 | 0 | 0 |
T17 | 1773 | 1693 | 0 | 0 |
T23 | 2573 | 2495 | 0 | 0 |
T25 | 817 | 764 | 0 | 0 |
T26 | 2735 | 2635 | 0 | 0 |
T27 | 1501 | 1406 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 965 | 965 | 0 | 0 |
OutputsKnown_A | 223938423 | 223742959 | 0 | 0 |
gen_no_flops.OutputDelay_A | 223938423 | 223742959 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 965 | 965 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T23 | 1 | 1 | 0 | 0 |
T25 | 1 | 1 | 0 | 0 |
T26 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 223938423 | 223742959 | 0 | 0 |
T1 | 2845 | 2784 | 0 | 0 |
T2 | 2811 | 2740 | 0 | 0 |
T3 | 2896 | 2797 | 0 | 0 |
T4 | 636609 | 636597 | 0 | 0 |
T13 | 2695 | 2616 | 0 | 0 |
T17 | 1773 | 1693 | 0 | 0 |
T23 | 2573 | 2495 | 0 | 0 |
T25 | 817 | 764 | 0 | 0 |
T26 | 2735 | 2635 | 0 | 0 |
T27 | 1501 | 1406 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 223938423 | 223742959 | 0 | 0 |
T1 | 2845 | 2784 | 0 | 0 |
T2 | 2811 | 2740 | 0 | 0 |
T3 | 2896 | 2797 | 0 | 0 |
T4 | 636609 | 636597 | 0 | 0 |
T13 | 2695 | 2616 | 0 | 0 |
T17 | 1773 | 1693 | 0 | 0 |
T23 | 2573 | 2495 | 0 | 0 |
T25 | 817 | 764 | 0 | 0 |
T26 | 2735 | 2635 | 0 | 0 |
T27 | 1501 | 1406 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 965 | 965 | 0 | 0 |
OutputsKnown_A | 223938423 | 223742959 | 0 | 0 |
gen_no_flops.OutputDelay_A | 223938423 | 223742959 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 965 | 965 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T23 | 1 | 1 | 0 | 0 |
T25 | 1 | 1 | 0 | 0 |
T26 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 223938423 | 223742959 | 0 | 0 |
T1 | 2845 | 2784 | 0 | 0 |
T2 | 2811 | 2740 | 0 | 0 |
T3 | 2896 | 2797 | 0 | 0 |
T4 | 636609 | 636597 | 0 | 0 |
T13 | 2695 | 2616 | 0 | 0 |
T17 | 1773 | 1693 | 0 | 0 |
T23 | 2573 | 2495 | 0 | 0 |
T25 | 817 | 764 | 0 | 0 |
T26 | 2735 | 2635 | 0 | 0 |
T27 | 1501 | 1406 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 223938423 | 223742959 | 0 | 0 |
T1 | 2845 | 2784 | 0 | 0 |
T2 | 2811 | 2740 | 0 | 0 |
T3 | 2896 | 2797 | 0 | 0 |
T4 | 636609 | 636597 | 0 | 0 |
T13 | 2695 | 2616 | 0 | 0 |
T17 | 1773 | 1693 | 0 | 0 |
T23 | 2573 | 2495 | 0 | 0 |
T25 | 817 | 764 | 0 | 0 |
T26 | 2735 | 2635 | 0 | 0 |
T27 | 1501 | 1406 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |