Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.87	100.00	94.44		97.30	97.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	97.87	100.00	94.44		97.30	97.62	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.87	100.00	94.44		97.30	97.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.89	100.00	94.44		97.30	97.73	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		108	108	100.00
ALWAYS	42	3	3	100.00
CONT_ASSIGN	44	1	1	100.00
ALWAYS	47	104	104	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	3	3
44	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
78	1	1
79	1	1
80	1	1
83	1	1
84	1	1
85	1	1
			MISSING_ELSE
89	1	1
90	1	1
93	1	1
94	1	1
			MISSING_ELSE
98	1	1
101	1	1
102	1	1
			MISSING_ELSE
106	1	1
107	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
117	1	1
118	1	1
119	1	1
			MISSING_ELSE
123	1	1
124	1	1
125	1	1
			MISSING_ELSE
129	1	1
130	1	1
131	1	1
			MISSING_ELSE
135	1	1
136	1	1
137	1	1
138	1	1
140	1	1
141	1	1
143	1	1
148	1	1
149	1	1
150	1	1
153	1	1
154	1	1
155	1	1
156	1	1
			MISSING_ELSE
160	1	1
161	1	1
162	1	1
165	1	1
166	1	1
167	1	1
168	1	1
			MISSING_ELSE
172	1	1
175	1	1
178	1	1
186	1	1
188	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
211	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T25,T15,T77
1	1	Covered	T17,T25,T27

 LINE       66
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T24,T44
1	1	Covered	T1,T2,T3

 LINE       186
 EXPRESSION (local_escalate_i || csrng_ack_err_i)
             --------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T36,T14,T37

 LINE       188
 EXPRESSION (local_escalate_i ? Error : ((state_q == Error) ? Error : RejectCsrngEntropy))
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T36,T14,T37

 LINE       188
 SUB-EXPRESSION ((state_q == Error) ? Error : RejectCsrngEntropy)
                 ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       188
 SUB-EXPRESSION (state_q == Error)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T36,T14,T37

 LINE       201
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	20	100.00	(Not included in score)
Transitions	74	72	97.30
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	156	Covered	T1,T3,T13
AutoCaptGenCnt	143	Covered	T1,T2,T3
AutoCaptReseedCnt	141	Covered	T1,T13,T23
AutoDispatch	125	Covered	T1,T2,T3
AutoFirstAckWait	119	Covered	T1,T2,T3
AutoLoadIns	69	Covered	T1,T2,T3
AutoSendGenCmd	150	Covered	T1,T3,T13
AutoSendReseedCmd	162	Covered	T13,T23,T21
BootDone	98	Covered	T25,T27,T31
BootGenAckWait	90	Covered	T25,T27,T31
BootInsAckWait	80	Covered	T17,T25,T27
BootLoadGen	85	Covered	T25,T27,T31
BootLoadIns	65	Covered	T17,T25,T27
BootLoadUni	102	Covered	T27,T31,T44
BootPulse	94	Covered	T25,T27,T31
BootUniAckWait	107	Covered	T27,T31,T44
Error	188	Covered	T36,T14,T37
Idle	112	Covered	T1,T2,T3
RejectCsrngEntropy	188	Covered	T1,T2,T3
SWPortMode	74	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	131	Covered	T1,T13,T23
AutoAckWait->Error	188	Not Covered
AutoAckWait->Idle	211	Covered	T21,T24,T67
AutoAckWait->RejectCsrngEntropy	188	Covered	T3,T23,T79
AutoCaptGenCnt->AutoSendGenCmd	150	Covered	T1,T3,T13
AutoCaptGenCnt->Error	188	Covered	T113,T114,T115
AutoCaptGenCnt->Idle	211	Covered	T67,T116,T117
AutoCaptGenCnt->RejectCsrngEntropy	188	Covered	T2,T85,T118
AutoCaptReseedCnt->AutoSendReseedCmd	162	Covered	T13,T23,T21
AutoCaptReseedCnt->Error	188	Covered	T58,T119,T120
AutoCaptReseedCnt->Idle	211	Covered	T121,T122,T123
AutoCaptReseedCnt->RejectCsrngEntropy	188	Covered	T1,T124,T125
AutoDispatch->AutoCaptGenCnt	143	Covered	T1,T2,T3
AutoDispatch->AutoCaptReseedCnt	141	Covered	T1,T13,T23
AutoDispatch->Error	188	Covered	T126,T127,T128
AutoDispatch->Idle	138	Covered	T13,T22,T51
AutoDispatch->RejectCsrngEntropy	188	Covered	T129,T130,T131
AutoFirstAckWait->AutoDispatch	125	Covered	T1,T2,T3
AutoFirstAckWait->Error	188	Covered	T132
AutoFirstAckWait->Idle	211	Covered	T133,T134,T135
AutoFirstAckWait->RejectCsrngEntropy	188	Covered	T56,T136,T53
AutoLoadIns->AutoFirstAckWait	119	Covered	T1,T2,T3
AutoLoadIns->Error	188	Covered	T8,T137,T61
AutoLoadIns->Idle	211	Covered	T1,T3,T17
AutoLoadIns->RejectCsrngEntropy	188	Covered	T138,T92,T139
AutoSendGenCmd->AutoAckWait	156	Covered	T1,T3,T13
AutoSendGenCmd->Error	188	Covered	T111,T140
AutoSendGenCmd->Idle	211	Covered	T141,T142,T143
AutoSendGenCmd->RejectCsrngEntropy	188	Covered	T46,T144,T145
AutoSendReseedCmd->AutoAckWait	168	Covered	T13,T23,T21
AutoSendReseedCmd->Error	188	Covered	T9,T146,T147
AutoSendReseedCmd->Idle	211	Covered	T24,T148,T149
AutoSendReseedCmd->RejectCsrngEntropy	188	Covered	T150,T151,T152
BootDone->BootLoadUni	102	Covered	T27,T31,T44
BootDone->Error	188	Covered	T153
BootDone->Idle	211	Covered	T25,T54,T154
BootDone->RejectCsrngEntropy	188	Covered	T155,T156,T157
BootGenAckWait->BootPulse	94	Covered	T25,T27,T31
BootGenAckWait->Error	188	Covered	T158,T159
BootGenAckWait->Idle	211	Covered	T81,T160,T161
BootGenAckWait->RejectCsrngEntropy	188	Covered	T106,T162,T163
BootInsAckWait->BootLoadGen	85	Covered	T25,T27,T31
BootInsAckWait->Error	188	Covered	T160,T60,T164
BootInsAckWait->Idle	211	Covered	T59,T165,T166
BootInsAckWait->RejectCsrngEntropy	188	Covered	T17,T76,T78
BootLoadGen->BootGenAckWait	90	Covered	T25,T27,T31
BootLoadGen->Error	188	Covered	T167
BootLoadGen->Idle	211	Covered	T77,T168,T169
BootLoadGen->RejectCsrngEntropy	188	Covered	T68,T170,T171
BootLoadIns->BootInsAckWait	80	Covered	T17,T25,T27
BootLoadIns->Error	188	Covered	T172,T173,T174
BootLoadIns->Idle	211	Covered	T91,T175,T176
BootLoadIns->RejectCsrngEntropy	188	Covered	T177,T178,T179
BootLoadUni->BootUniAckWait	107	Covered	T27,T31,T44
BootLoadUni->Error	188	Covered	T180,T181,T182
BootLoadUni->Idle	211	Not Covered
BootLoadUni->RejectCsrngEntropy	188	Covered	T96,T183,T184
BootPulse->BootDone	98	Covered	T25,T27,T31
BootPulse->Error	188	Covered	T15,T59,T185
BootPulse->Idle	211	Covered	T15,T90,T186
BootPulse->RejectCsrngEntropy	188	Covered	T187,T188,T189
BootUniAckWait->Error	188	Covered	T190,T191,T192
BootUniAckWait->Idle	112	Covered	T27,T31,T56
BootUniAckWait->RejectCsrngEntropy	188	Covered	T44,T107,T193
Idle->AutoLoadIns	69	Covered	T1,T2,T3
Idle->BootLoadIns	65	Covered	T17,T25,T27
Idle->Error	188	Covered	T18,T19,T20
Idle->RejectCsrngEntropy	188	Covered	T17,T23,T44
Idle->SWPortMode	74	Covered	T1,T2,T3
RejectCsrngEntropy->Error	188	Covered	T194,T195
RejectCsrngEntropy->Idle	211	Covered	T1,T2,T3
SWPortMode->Error	188	Covered	T36,T14,T37
SWPortMode->Idle	211	Covered	T2,T4,T23
SWPortMode->RejectCsrngEntropy	188	Covered	T1,T2,T3

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		42	41	97.62
IF	42	2	2	100.00
CASE	62	35	35	100.00
IF	186	5	4	80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	42	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	62	case (state_q)
-2-:	64	if ((boot_req_mode_i && edn_enable_i))
-3-:	66	if ((auto_req_mode_i && edn_enable_i))
-4-:	70	if (edn_enable_i)
-5-:	84	if (csrng_cmd_ack_i)
-6-:	93	if (csrng_cmd_ack_i)
-7-:	101	if ((!boot_req_mode_i))
-8-:	110	if (csrng_cmd_ack_i)
-9-:	118	if (sw_cmd_req_load_i)
-10-:	124	if (csrng_cmd_ack_i)
-11-:	130	if (csrng_cmd_ack_i)
-12-:	136	if ((!auto_req_mode_i))
-13-:	140	if (max_reqs_cnt_zero_i)
-14-:	155	if (cmd_sent_i)
-15-:	167	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T17,T25,T27
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T17,T25,T27
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T17,T25,T27
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T17,T25,T27
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T25,T27,T31
BootGenAckWait	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T25,T27,T31
BootGenAckWait	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T25,T27,T31
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T25,T27,T31
BootDone	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T27,T31,T44
BootDone	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T25,T56,T107
BootLoadUni	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T27,T31,T44
BootUniAckWait	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T27,T31,T44
BootUniAckWait	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T27,T31,T44
AutoLoadIns	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T1,T2,T3
AutoLoadIns	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T1,T2,T3
AutoFirstAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T1,T2,T3
AutoFirstAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T3
AutoAckWait	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T1,T3,T13
AutoAckWait	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T1,T3,T13
AutoDispatch	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T13,T22,T51
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T1,T13,T23
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T1,T2,T3
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T3,T13
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T3,T13,T21
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T13,T23
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T13,T23,T21
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T13,T21,T22
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
RejectCsrngEntropy	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T36,T14,T37
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T18,T100

	LineNo.	Expression
-1-:	186	if ((local_escalate_i || csrng_ack_err_i))
-2-:	188	(local_escalate_i) ? 
-3-:	188	((state_q == Error)) ? 
-4-:	201	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy})))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T36,T14,T37
1	0	1	-	Not Covered
1	0	0	-	Covered	T1,T2,T3
0	-	-	1	Covered	T1,T2,T3
0	-	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	223938423	148645	0	0
FpvSecCmErrorStEscalate_A	223938423	149944	0	0
u_state_regs_A	223905175	223709711	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	148645	0	0
T7	0	330	0	0
T8	0	1102	0	0
T14	1696	362	0	0
T15	0	667	0	0
T16	0	918	0	0
T18	0	18670	0	0
T22	2304	0	0	0
T24	3710	0	0	0
T36	2168	1112	0	0
T37	643	203	0	0
T41	220697	0	0	0
T43	2764	0	0	0
T46	2279	0	0	0
T47	2069	0	0	0
T73	1736	0	0	0
T74	0	623	0	0
T75	0	573	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	149944	0	0
T7	0	331	0	0
T8	0	1103	0	0
T14	1696	363	0	0
T15	0	668	0	0
T16	0	919	0	0
T18	0	18930	0	0
T22	2304	0	0	0
T24	3710	0	0	0
T36	2168	1113	0	0
T37	643	204	0	0
T41	220697	0	0	0
T43	2764	0	0	0
T46	2279	0	0	0
T47	2069	0	0	0
T73	1736	0	0	0
T74	0	624	0	0
T75	0	574	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223905175	223709711	0	0
T1	2845	2784	0	0
T2	2811	2740	0	0
T3	2896	2797	0	0
T4	636609	636597	0	0
T13	2695	2616	0	0
T17	1773	1693	0	0
T23	2573	2495	0	0
T25	817	764	0	0
T26	2735	2635	0	0
T27	1501	1406	0	0