Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T2,T3
DataWait	75	Covered	T1,T2,T3
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T36,T14,T37
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T186,T196,T197
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T2,T3
DataWait->AckPls	80	Covered	T1,T2,T3
DataWait->Disabled	107	Covered	T77,T67,T168
DataWait->Error	99	Covered	T14,T15,T59
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T18,T19,T20
EndPointClear->Disabled	107	Covered	T21,T91,T175
EndPointClear->Error	99	Covered	T8,T18,T137
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T2,T3
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T36,T14,T37

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T2,T3
Idle	-	1	0	-	Covered	T1,T2,T3
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T2,T3
DataWait	-	-	-	0	Covered	T1,T2,T3
AckPls	-	-	-	-	Covered	T1,T2,T3
Error	-	-	-	-	Covered	T36,T14,T37
default	-	-	-	-	Covered	T36,T37,T74

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T36,T14,T37
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	1567568961	1053415	0	0
FpvSecCmErrorStEscalate_A	1567568961	1062508	0	0
u_state_regs_A	1567535713	1566167465	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1567568961	1053415	0	0
T7	0	2660	0	0
T8	0	7714	0	0
T14	11872	2534	0	0
T15	0	4669	0	0
T16	0	6426	0	0
T18	0	130690	0	0
T22	16128	0	0	0
T24	25970	0	0	0
T36	15176	7734	0	0
T37	4501	1371	0	0
T41	1544879	0	0	0
T43	19348	0	0	0
T46	15953	0	0	0
T47	14483	0	0	0
T73	12152	0	0	0
T74	0	4311	0	0
T75	0	3961	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1567568961	1062508	0	0
T7	0	2667	0	0
T8	0	7721	0	0
T14	11872	2541	0	0
T15	0	4676	0	0
T16	0	6433	0	0
T18	0	132510	0	0
T22	16128	0	0	0
T24	25970	0	0	0
T36	15176	7741	0	0
T37	4501	1378	0	0
T41	1544879	0	0	0
T43	19348	0	0	0
T46	15953	0	0	0
T47	14483	0	0	0
T73	12152	0	0	0
T74	0	4318	0	0
T75	0	3968	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1567535713	1566167465	0	0
T1	19915	19488	0	0
T2	19677	19180	0	0
T3	20272	19579	0	0
T4	4456263	4456179	0	0
T13	18865	18312	0	0
T17	12411	11851	0	0
T23	18011	17465	0	0
T25	5719	5348	0	0
T26	19145	18445	0	0
T27	10507	9842	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T26,T13,T22
DataWait	75	Covered	T26,T13,T22
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T36,T14,T37
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T26,T13,T22
DataWait->AckPls	80	Covered	T26,T13,T22
DataWait->Disabled	107	Covered	T77,T116,T169
DataWait->Error	99	Covered	T161,T185,T164
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T18,T19,T20
EndPointClear->Disabled	107	Covered	T21,T91,T175
EndPointClear->Error	99	Covered	T8,T18,T137
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T26,T13,T22
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T36,T14,T37

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T26,T13,T22
Idle	-	1	0	-	Covered	T26,T13,T22
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T26,T13,T22
DataWait	-	-	-	0	Covered	T26,T13,T22
AckPls	-	-	-	-	Covered	T26,T13,T22
Error	-	-	-	-	Covered	T36,T14,T37
default	-	-	-	-	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T36,T14,T37
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	223938423	150795	0	0
FpvSecCmErrorStEscalate_A	223938423	152094	0	0
u_state_regs_A	223938423	223742959	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	150795	0	0
T7	0	380	0	0
T8	0	1102	0	0
T14	1696	362	0	0
T15	0	667	0	0
T16	0	918	0	0
T18	0	18670	0	0
T22	2304	0	0	0
T24	3710	0	0	0
T36	2168	1112	0	0
T37	643	203	0	0
T41	220697	0	0	0
T43	2764	0	0	0
T46	2279	0	0	0
T47	2069	0	0	0
T73	1736	0	0	0
T74	0	623	0	0
T75	0	573	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	152094	0	0
T7	0	381	0	0
T8	0	1103	0	0
T14	1696	363	0	0
T15	0	668	0	0
T16	0	919	0	0
T18	0	18930	0	0
T22	2304	0	0	0
T24	3710	0	0	0
T36	2168	1113	0	0
T37	643	204	0	0
T41	220697	0	0	0
T43	2764	0	0	0
T46	2279	0	0	0
T47	2069	0	0	0
T73	1736	0	0	0
T74	0	624	0	0
T75	0	574	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	223742959	0	0
T1	2845	2784	0	0
T2	2811	2740	0	0
T3	2896	2797	0	0
T4	636609	636597	0	0
T13	2695	2616	0	0
T17	1773	1693	0	0
T23	2573	2495	0	0
T25	817	764	0	0
T26	2735	2635	0	0
T27	1501	1406	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T3,T17,T25
DataWait	75	Covered	T3,T17,T25
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T36,T14,T37
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T3,T17,T25
DataWait->AckPls	80	Covered	T3,T17,T25
DataWait->Disabled	107	Covered	T142,T198
DataWait->Error	99	Covered	T14,T199,T113
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T18,T19,T20
EndPointClear->Disabled	107	Covered	T21,T91,T175
EndPointClear->Error	99	Covered	T8,T18,T137
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T3,T17,T25
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T36,T37,T74

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T3,T17,T25
Idle	-	1	0	-	Covered	T3,T17,T25
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T3,T17,T25
DataWait	-	-	-	0	Covered	T3,T17,T25
AckPls	-	-	-	-	Covered	T3,T17,T25
Error	-	-	-	-	Covered	T36,T14,T37
default	-	-	-	-	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T36,T14,T37
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	223938423	150795	0	0
FpvSecCmErrorStEscalate_A	223938423	152094	0	0
u_state_regs_A	223938423	223742959	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	150795	0	0
T7	0	380	0	0
T8	0	1102	0	0
T14	1696	362	0	0
T15	0	667	0	0
T16	0	918	0	0
T18	0	18670	0	0
T22	2304	0	0	0
T24	3710	0	0	0
T36	2168	1112	0	0
T37	643	203	0	0
T41	220697	0	0	0
T43	2764	0	0	0
T46	2279	0	0	0
T47	2069	0	0	0
T73	1736	0	0	0
T74	0	623	0	0
T75	0	573	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	152094	0	0
T7	0	381	0	0
T8	0	1103	0	0
T14	1696	363	0	0
T15	0	668	0	0
T16	0	919	0	0
T18	0	18930	0	0
T22	2304	0	0	0
T24	3710	0	0	0
T36	2168	1113	0	0
T37	643	204	0	0
T41	220697	0	0	0
T43	2764	0	0	0
T46	2279	0	0	0
T47	2069	0	0	0
T73	1736	0	0	0
T74	0	624	0	0
T75	0	574	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	223742959	0	0
T1	2845	2784	0	0
T2	2811	2740	0	0
T3	2896	2797	0	0
T4	636609	636597	0	0
T13	2695	2616	0	0
T17	1773	1693	0	0
T23	2573	2495	0	0
T25	817	764	0	0
T26	2735	2635	0	0
T27	1501	1406	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T2,T4
DataWait	75	Covered	T1,T2,T4
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T36,T14,T37
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T200
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T2,T4
DataWait->AckPls	80	Covered	T1,T2,T4
DataWait->Disabled	107	Covered	T117,T201,T202
DataWait->Error	99	Covered	T15,T59,T154
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T18,T19,T20
EndPointClear->Disabled	107	Covered	T21,T91,T175
EndPointClear->Error	99	Covered	T8,T18,T165
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T2,T4
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T14,T16,T7

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T2,T4
Idle	-	1	0	-	Covered	T1,T2,T4
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T2,T4
DataWait	-	-	-	0	Covered	T1,T2,T4
AckPls	-	-	-	-	Covered	T1,T2,T4
Error	-	-	-	-	Covered	T36,T14,T37
default	-	-	-	-	Covered	T36,T37,T74

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T36,T14,T37
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	223938423	148645	0	0
FpvSecCmErrorStEscalate_A	223938423	149944	0	0
u_state_regs_A	223905175	223709711	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	148645	0	0
T7	0	380	0	0
T8	0	1102	0	0
T14	1696	362	0	0
T15	0	667	0	0
T16	0	918	0	0
T18	0	18670	0	0
T22	2304	0	0	0
T24	3710	0	0	0
T36	2168	1062	0	0
T37	643	153	0	0
T41	220697	0	0	0
T43	2764	0	0	0
T46	2279	0	0	0
T47	2069	0	0	0
T73	1736	0	0	0
T74	0	573	0	0
T75	0	523	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	149944	0	0
T7	0	381	0	0
T8	0	1103	0	0
T14	1696	363	0	0
T15	0	668	0	0
T16	0	919	0	0
T18	0	18930	0	0
T22	2304	0	0	0
T24	3710	0	0	0
T36	2168	1063	0	0
T37	643	154	0	0
T41	220697	0	0	0
T43	2764	0	0	0
T46	2279	0	0	0
T47	2069	0	0	0
T73	1736	0	0	0
T74	0	574	0	0
T75	0	524	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223905175	223709711	0	0
T1	2845	2784	0	0
T2	2811	2740	0	0
T3	2896	2797	0	0
T4	636609	636597	0	0
T13	2695	2616	0	0
T17	1773	1693	0	0
T23	2573	2495	0	0
T25	817	764	0	0
T26	2735	2635	0	0
T27	1501	1406	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T26,T21,T43
DataWait	75	Covered	T26,T21,T43
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T36,T14,T37
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T197
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T26,T21,T43
DataWait->AckPls	80	Covered	T26,T21,T43
DataWait->Disabled	107	Covered	T168,T203,T204
DataWait->Error	99	Covered	T100,T127,T132
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T18,T19,T20
EndPointClear->Disabled	107	Covered	T21,T91,T175
EndPointClear->Error	99	Covered	T8,T18,T137
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T26,T21,T43
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T36,T14,T37

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T26,T21,T43
Idle	-	1	0	-	Covered	T26,T21,T43
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T26,T21,T43
DataWait	-	-	-	0	Covered	T26,T21,T43
AckPls	-	-	-	-	Covered	T26,T21,T43
Error	-	-	-	-	Covered	T36,T14,T37
default	-	-	-	-	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T36,T14,T37
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	223938423	150795	0	0
FpvSecCmErrorStEscalate_A	223938423	152094	0	0
u_state_regs_A	223938423	223742959	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	150795	0	0
T7	0	380	0	0
T8	0	1102	0	0
T14	1696	362	0	0
T15	0	667	0	0
T16	0	918	0	0
T18	0	18670	0	0
T22	2304	0	0	0
T24	3710	0	0	0
T36	2168	1112	0	0
T37	643	203	0	0
T41	220697	0	0	0
T43	2764	0	0	0
T46	2279	0	0	0
T47	2069	0	0	0
T73	1736	0	0	0
T74	0	623	0	0
T75	0	573	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	152094	0	0
T7	0	381	0	0
T8	0	1103	0	0
T14	1696	363	0	0
T15	0	668	0	0
T16	0	919	0	0
T18	0	18930	0	0
T22	2304	0	0	0
T24	3710	0	0	0
T36	2168	1113	0	0
T37	643	204	0	0
T41	220697	0	0	0
T43	2764	0	0	0
T46	2279	0	0	0
T47	2069	0	0	0
T73	1736	0	0	0
T74	0	624	0	0
T75	0	574	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	223742959	0	0
T1	2845	2784	0	0
T2	2811	2740	0	0
T3	2896	2797	0	0
T4	636609	636597	0	0
T13	2695	2616	0	0
T17	1773	1693	0	0
T23	2573	2495	0	0
T25	817	764	0	0
T26	2735	2635	0	0
T27	1501	1406	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T26,T23,T44
DataWait	75	Covered	T26,T23,T44
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T36,T14,T37
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T205
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T26,T23,T44
DataWait->AckPls	80	Covered	T26,T23,T44
DataWait->Disabled	107	Covered	T67,T206,T207
DataWait->Error	99	Covered	T7,T61,T208
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T18,T19,T20
EndPointClear->Disabled	107	Covered	T21,T91,T175
EndPointClear->Error	99	Covered	T8,T18,T137
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T26,T23,T44
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T36,T14,T37

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T26,T23,T44
Idle	-	1	0	-	Covered	T26,T23,T44
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T26,T23,T44
DataWait	-	-	-	0	Covered	T26,T7,T81
AckPls	-	-	-	-	Covered	T26,T23,T44
Error	-	-	-	-	Covered	T36,T14,T37
default	-	-	-	-	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T36,T14,T37
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	223938423	150795	0	0
FpvSecCmErrorStEscalate_A	223938423	152094	0	0
u_state_regs_A	223938423	223742959	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	150795	0	0
T7	0	380	0	0
T8	0	1102	0	0
T14	1696	362	0	0
T15	0	667	0	0
T16	0	918	0	0
T18	0	18670	0	0
T22	2304	0	0	0
T24	3710	0	0	0
T36	2168	1112	0	0
T37	643	203	0	0
T41	220697	0	0	0
T43	2764	0	0	0
T46	2279	0	0	0
T47	2069	0	0	0
T73	1736	0	0	0
T74	0	623	0	0
T75	0	573	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	152094	0	0
T7	0	381	0	0
T8	0	1103	0	0
T14	1696	363	0	0
T15	0	668	0	0
T16	0	919	0	0
T18	0	18930	0	0
T22	2304	0	0	0
T24	3710	0	0	0
T36	2168	1113	0	0
T37	643	204	0	0
T41	220697	0	0	0
T43	2764	0	0	0
T46	2279	0	0	0
T47	2069	0	0	0
T73	1736	0	0	0
T74	0	624	0	0
T75	0	574	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	223742959	0	0
T1	2845	2784	0	0
T2	2811	2740	0	0
T3	2896	2797	0	0
T4	636609	636597	0	0
T13	2695	2616	0	0
T17	1773	1693	0	0
T23	2573	2495	0	0
T25	817	764	0	0
T26	2735	2635	0	0
T27	1501	1406	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T13,T36,T45
DataWait	75	Covered	T13,T36,T45
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T36,T14,T37
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T196
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T13,T36,T45
DataWait->AckPls	80	Covered	T13,T36,T45
DataWait->Disabled	107	Covered	T141,T209
DataWait->Error	99	Covered	T210,T211,T212
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T18,T19,T20
EndPointClear->Disabled	107	Covered	T21,T91,T175
EndPointClear->Error	99	Covered	T8,T18,T137
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T13,T36,T45
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T36,T14,T37

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T13,T36,T45
Idle	-	1	0	-	Covered	T13,T36,T45
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T13,T36,T45
DataWait	-	-	-	0	Covered	T13,T45,T48
AckPls	-	-	-	-	Covered	T13,T36,T45
Error	-	-	-	-	Covered	T36,T14,T37
default	-	-	-	-	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T36,T14,T37
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	223938423	150795	0	0
FpvSecCmErrorStEscalate_A	223938423	152094	0	0
u_state_regs_A	223938423	223742959	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	150795	0	0
T7	0	380	0	0
T8	0	1102	0	0
T14	1696	362	0	0
T15	0	667	0	0
T16	0	918	0	0
T18	0	18670	0	0
T22	2304	0	0	0
T24	3710	0	0	0
T36	2168	1112	0	0
T37	643	203	0	0
T41	220697	0	0	0
T43	2764	0	0	0
T46	2279	0	0	0
T47	2069	0	0	0
T73	1736	0	0	0
T74	0	623	0	0
T75	0	573	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	152094	0	0
T7	0	381	0	0
T8	0	1103	0	0
T14	1696	363	0	0
T15	0	668	0	0
T16	0	919	0	0
T18	0	18930	0	0
T22	2304	0	0	0
T24	3710	0	0	0
T36	2168	1113	0	0
T37	643	204	0	0
T41	220697	0	0	0
T43	2764	0	0	0
T46	2279	0	0	0
T47	2069	0	0	0
T73	1736	0	0	0
T74	0	624	0	0
T75	0	574	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	223742959	0	0
T1	2845	2784	0	0
T2	2811	2740	0	0
T3	2896	2797	0	0
T4	636609	636597	0	0
T13	2695	2616	0	0
T17	1773	1693	0	0
T23	2573	2495	0	0
T25	817	764	0	0
T26	2735	2635	0	0
T27	1501	1406	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T13,T44,T45
DataWait	75	Covered	T13,T44,T45
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T36,T14,T37
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T186,T213
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T13,T44,T45
DataWait->AckPls	80	Covered	T13,T44,T45
DataWait->Disabled	107	Covered	T214,T215
DataWait->Error	99	Covered	T103,T216,T217
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T18,T19,T20
EndPointClear->Disabled	107	Covered	T21,T91,T175
EndPointClear->Error	99	Covered	T8,T18,T137
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T13,T44,T45
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T36,T14,T37

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T13,T44,T45
Idle	-	1	0	-	Covered	T13,T44,T45
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T13,T44,T45
DataWait	-	-	-	0	Covered	T13,T44,T45
AckPls	-	-	-	-	Covered	T13,T44,T45
Error	-	-	-	-	Covered	T36,T14,T37
default	-	-	-	-	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T36,T14,T37
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	223938423	150795	0	0
FpvSecCmErrorStEscalate_A	223938423	152094	0	0
u_state_regs_A	223938423	223742959	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	150795	0	0
T7	0	380	0	0
T8	0	1102	0	0
T14	1696	362	0	0
T15	0	667	0	0
T16	0	918	0	0
T18	0	18670	0	0
T22	2304	0	0	0
T24	3710	0	0	0
T36	2168	1112	0	0
T37	643	203	0	0
T41	220697	0	0	0
T43	2764	0	0	0
T46	2279	0	0	0
T47	2069	0	0	0
T73	1736	0	0	0
T74	0	623	0	0
T75	0	573	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	152094	0	0
T7	0	381	0	0
T8	0	1103	0	0
T14	1696	363	0	0
T15	0	668	0	0
T16	0	919	0	0
T18	0	18930	0	0
T22	2304	0	0	0
T24	3710	0	0	0
T36	2168	1113	0	0
T37	643	204	0	0
T41	220697	0	0	0
T43	2764	0	0	0
T46	2279	0	0	0
T47	2069	0	0	0
T73	1736	0	0	0
T74	0	624	0	0
T75	0	574	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	223742959	0	0
T1	2845	2784	0	0
T2	2811	2740	0	0
T3	2896	2797	0	0
T4	636609	636597	0	0
T13	2695	2616	0	0
T17	1773	1693	0	0
T23	2573	2495	0	0
T25	817	764	0	0
T26	2735	2635	0	0
T27	1501	1406	0	0