Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T32,T94,T95
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T35,T39,T40
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	447121858	1083719	0	0
DepthKnown_A	447876846	447485918	0	0
RvalidKnown_A	447876846	447485918	0	0
WreadyKnown_A	447876846	447485918	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	447456952	1166295	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447121858	1083719	0	0
T1	5690	941	0	0
T2	5622	709	0	0
T3	5792	1098	0	0
T4	1273218	0	0	0
T13	5390	2285	0	0
T17	3546	73	0	0
T21	0	3404	0	0
T22	0	1285	0	0
T23	5146	747	0	0
T24	0	6048	0	0
T25	1634	0	0	0
T26	5470	0	0	0
T27	3002	0	0	0
T46	0	343	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447876846	447485918	0	0
T1	5690	5568	0	0
T2	5622	5480	0	0
T3	5792	5594	0	0
T4	1273218	1273194	0	0
T13	5390	5232	0	0
T17	3546	3386	0	0
T23	5146	4990	0	0
T25	1634	1528	0	0
T26	5470	5270	0	0
T27	3002	2812	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447876846	447485918	0	0
T1	5690	5568	0	0
T2	5622	5480	0	0
T3	5792	5594	0	0
T4	1273218	1273194	0	0
T13	5390	5232	0	0
T17	3546	3386	0	0
T23	5146	4990	0	0
T25	1634	1528	0	0
T26	5470	5270	0	0
T27	3002	2812	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447876846	447485918	0	0
T1	5690	5568	0	0
T2	5622	5480	0	0
T3	5792	5594	0	0
T4	1273218	1273194	0	0
T13	5390	5232	0	0
T17	3546	3386	0	0
T23	5146	4990	0	0
T25	1634	1528	0	0
T26	5470	5270	0	0
T27	3002	2812	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	447456952	1166295	0	0
T1	5690	941	0	0
T2	5622	709	0	0
T3	5792	1098	0	0
T4	1273218	0	0	0
T13	5390	2285	0	0
T14	0	2218	0	0
T17	3546	73	0	0
T21	0	3404	0	0
T22	0	1285	0	0
T23	5146	747	0	0
T25	1634	0	0	0
T26	5470	0	0	0
T27	3002	0	0	0
T46	0	343	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T67,T96
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T32,T94,T95
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T40,T97,T98
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T13,T23

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	223560929	535606	0	0
DepthKnown_A	223938423	223742959	0	0
RvalidKnown_A	223938423	223742959	0	0
WreadyKnown_A	223938423	223742959	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	223728476	576478	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223560929	535606	0	0
T1	2845	432	0	0
T2	2811	360	0	0
T3	2896	539	0	0
T4	636609	0	0	0
T13	2695	1127	0	0
T17	1773	29	0	0
T21	0	1660	0	0
T22	0	647	0	0
T23	2573	376	0	0
T24	0	2968	0	0
T25	817	0	0	0
T26	2735	0	0	0
T27	1501	0	0	0
T46	0	258	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	223742959	0	0
T1	2845	2784	0	0
T2	2811	2740	0	0
T3	2896	2797	0	0
T4	636609	636597	0	0
T13	2695	2616	0	0
T17	1773	1693	0	0
T23	2573	2495	0	0
T25	817	764	0	0
T26	2735	2635	0	0
T27	1501	1406	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	223742959	0	0
T1	2845	2784	0	0
T2	2811	2740	0	0
T3	2896	2797	0	0
T4	636609	636597	0	0
T13	2695	2616	0	0
T17	1773	1693	0	0
T23	2573	2495	0	0
T25	817	764	0	0
T26	2735	2635	0	0
T27	1501	1406	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	223742959	0	0
T1	2845	2784	0	0
T2	2811	2740	0	0
T3	2896	2797	0	0
T4	636609	636597	0	0
T13	2695	2616	0	0
T17	1773	1693	0	0
T23	2573	2495	0	0
T25	817	764	0	0
T26	2735	2635	0	0
T27	1501	1406	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	223728476	576478	0	0
T1	2845	432	0	0
T2	2811	360	0	0
T3	2896	539	0	0
T4	636609	0	0	0
T13	2695	1127	0	0
T14	0	1110	0	0
T17	1773	29	0	0
T21	0	1660	0	0
T22	0	647	0	0
T23	2573	376	0	0
T25	817	0	0	0
T26	2735	0	0	0
T27	1501	0	0	0
T46	0	258	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T99
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T35,T39
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	223560929	548113	0	0
DepthKnown_A	223938423	223742959	0	0
RvalidKnown_A	223938423	223742959	0	0
WreadyKnown_A	223938423	223742959	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	223728476	589817	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223560929	548113	0	0
T1	2845	509	0	0
T2	2811	349	0	0
T3	2896	559	0	0
T4	636609	0	0	0
T13	2695	1158	0	0
T17	1773	44	0	0
T21	0	1744	0	0
T22	0	638	0	0
T23	2573	371	0	0
T24	0	3080	0	0
T25	817	0	0	0
T26	2735	0	0	0
T27	1501	0	0	0
T46	0	85	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	223742959	0	0
T1	2845	2784	0	0
T2	2811	2740	0	0
T3	2896	2797	0	0
T4	636609	636597	0	0
T13	2695	2616	0	0
T17	1773	1693	0	0
T23	2573	2495	0	0
T25	817	764	0	0
T26	2735	2635	0	0
T27	1501	1406	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	223742959	0	0
T1	2845	2784	0	0
T2	2811	2740	0	0
T3	2896	2797	0	0
T4	636609	636597	0	0
T13	2695	2616	0	0
T17	1773	1693	0	0
T23	2573	2495	0	0
T25	817	764	0	0
T26	2735	2635	0	0
T27	1501	1406	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223938423	223742959	0	0
T1	2845	2784	0	0
T2	2811	2740	0	0
T3	2896	2797	0	0
T4	636609	636597	0	0
T13	2695	2616	0	0
T17	1773	1693	0	0
T23	2573	2495	0	0
T25	817	764	0	0
T26	2735	2635	0	0
T27	1501	1406	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	223728476	589817	0	0
T1	2845	509	0	0
T2	2811	349	0	0
T3	2896	559	0	0
T4	636609	0	0	0
T13	2695	1158	0	0
T14	0	1108	0	0
T17	1773	44	0	0
T21	0	1744	0	0
T22	0	638	0	0
T23	2573	371	0	0
T25	817	0	0	0
T26	2735	0	0	0
T27	1501	0	0	0
T46	0	85	0	0