Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	717349	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5939578

1

T1

5

T2

23

T3

51

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1748367	1			T1	46		T2	37		T3	48
values[0x0]	2268933	1			T1	6		T2	14		T3	35
values[0x1]	2639627	1			T1	6		T2	9		T3	21

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	351565	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

6305362

1

T1

21

T2

31

T3

64

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	25374	1			T31	2		T5	476		T40	1
valid_sources[0x01]	25842	1			T5	528		T40	1		T50	1
valid_sources[0x02]	25809	1			T3	1		T5	510		T42	3
valid_sources[0x03]	27171	1			T3	4		T28	1		T31	1
valid_sources[0x04]	24464	1			T5	540		T50	1		T89	1
valid_sources[0x05]	27725	1			T5	518		T50	1		T96	3
valid_sources[0x06]	26317	1			T1	1		T5	513		T41	1
valid_sources[0x07]	24613	1			T28	1		T5	535		T41	1
valid_sources[0x08]	24500	1			T5	462		T96	8		T281	1
valid_sources[0x09]	26678	1			T1	1		T5	490		T50	1
valid_sources[0x0a]	25798	1			T1	2		T31	1		T44	1
valid_sources[0x0b]	26467	1			T9	4		T5	587		T40	3
valid_sources[0x0c]	26264	1			T25	1		T28	1		T11	3
valid_sources[0x0d]	24730	1			T2	2		T25	1		T26	2
valid_sources[0x0e]	27524	1			T5	550		T41	3		T55	1
valid_sources[0x0f]	26121	1			T1	2		T5	508		T40	1
valid_sources[0x10]	25302	1			T5	494		T40	1		T14	1
valid_sources[0x11]	27191	1			T5	553		T40	1		T14	1
valid_sources[0x12]	25361	1			T2	1		T44	2		T5	523
valid_sources[0x13]	24117	1			T2	1		T3	1		T31	1
valid_sources[0x14]	25824	1			T28	1		T5	492		T55	1
valid_sources[0x15]	26222	1			T1	1		T2	1		T3	3
valid_sources[0x16]	27903	1			T3	2		T5	504		T50	2
valid_sources[0x17]	26376	1			T5	529		T85	1		T96	4
valid_sources[0x18]	27092	1			T2	1		T3	3		T25	1
valid_sources[0x19]	25153	1			T27	7		T5	559		T40	2
valid_sources[0x1a]	25653	1			T5	522		T50	1		T20	3
valid_sources[0x1b]	26165	1			T3	1		T26	3		T11	1
valid_sources[0x1c]	25840	1			T9	2		T11	3		T44	1
valid_sources[0x1d]	24757	1			T26	1		T31	1		T44	1
valid_sources[0x1e]	26544	1			T1	1		T28	1		T11	1
valid_sources[0x1f]	26206	1			T2	3		T25	1		T11	1
valid_sources[0x20]	27661	1			T26	1		T28	1		T11	2
valid_sources[0x21]	24966	1			T2	1		T5	485		T40	3
valid_sources[0x22]	28309	1			T26	2		T28	1		T11	1
valid_sources[0x23]	26531	1			T26	3		T5	618		T41	7
valid_sources[0x24]	26553	1			T3	1		T5	561		T40	5
valid_sources[0x25]	24217	1			T1	1		T2	1		T25	1
valid_sources[0x26]	28041	1			T5	543		T50	2		T45	5
valid_sources[0x27]	24668	1			T2	3		T3	2		T26	1
valid_sources[0x28]	26262	1			T1	1		T25	1		T31	1
valid_sources[0x29]	27081	1			T25	1		T26	1		T11	1
valid_sources[0x2a]	25809	1			T1	1		T26	1		T11	3
valid_sources[0x2b]	27670	1			T25	1		T5	457		T46	3
valid_sources[0x2c]	25224	1			T1	1		T11	3		T44	1
valid_sources[0x2d]	25943	1			T5	530		T14	2		T42	1
valid_sources[0x2e]	26265	1			T11	8		T5	598		T40	2
valid_sources[0x2f]	25107	1			T5	530		T41	4		T50	4
valid_sources[0x30]	25218	1			T2	2		T27	7		T31	1
valid_sources[0x31]	24943	1			T27	2		T5	498		T40	1
valid_sources[0x32]	25908	1			T1	1		T9	9		T28	1
valid_sources[0x33]	26580	1			T44	1		T5	536		T40	2
valid_sources[0x34]	27842	1			T1	1		T11	3		T5	560
valid_sources[0x35]	26505	1			T26	1		T27	12		T5	518
valid_sources[0x36]	25038	1			T26	1		T5	537		T50	3
valid_sources[0x37]	26128	1			T3	1		T25	2		T5	513
valid_sources[0x38]	25890	1			T5	530		T40	1		T55	1
valid_sources[0x39]	25498	1			T1	2		T25	1		T44	1
valid_sources[0x3a]	25624	1			T11	1		T31	2		T5	482
valid_sources[0x3b]	25718	1			T25	1		T73	2		T5	444
valid_sources[0x3c]	24983	1			T3	1		T25	2		T11	1
valid_sources[0x3d]	26023	1			T25	1		T26	1		T5	498
valid_sources[0x3e]	26697	1			T3	1		T5	545		T50	1
valid_sources[0x3f]	24299	1			T5	535		T40	1		T24	1
valid_sources[0x40]	25771	1			T1	1		T26	1		T5	538
valid_sources[0x41]	26228	1			T28	2		T5	545		T40	1
valid_sources[0x42]	25318	1			T27	1		T5	501		T40	2
valid_sources[0x43]	26067	1			T5	512		T49	1		T20	1
valid_sources[0x44]	25164	1			T5	551		T41	4		T50	2
valid_sources[0x45]	26177	1			T1	1		T5	522		T40	1
valid_sources[0x46]	26888	1			T5	522		T14	1		T50	1
valid_sources[0x47]	26342	1			T3	1		T31	1		T73	1
valid_sources[0x48]	25346	1			T2	1		T25	2		T5	493
valid_sources[0x49]	25630	1			T1	1		T28	1		T5	573
valid_sources[0x4a]	25272	1			T11	1		T5	493		T50	1
valid_sources[0x4b]	26406	1			T2	1		T3	3		T28	2
valid_sources[0x4c]	26948	1			T3	2		T5	555		T40	1
valid_sources[0x4d]	25823	1			T5	535		T50	2		T55	2
valid_sources[0x4e]	25209	1			T5	515		T50	1		T81	1
valid_sources[0x4f]	25401	1			T5	541		T40	2		T46	1
valid_sources[0x50]	26717	1			T26	3		T31	1		T5	536
valid_sources[0x51]	27878	1			T5	519		T50	2		T46	1
valid_sources[0x52]	25758	1			T11	3		T5	539		T40	2
valid_sources[0x53]	26159	1			T25	1		T5	536		T50	1
valid_sources[0x54]	25001	1			T3	3		T5	583		T40	1
valid_sources[0x55]	25993	1			T5	483		T50	2		T55	2
valid_sources[0x56]	26140	1			T27	1		T11	1		T73	1
valid_sources[0x57]	26210	1			T1	1		T31	1		T5	597
valid_sources[0x58]	25742	1			T28	3		T11	1		T31	1
valid_sources[0x59]	25290	1			T25	1		T5	505		T96	7
valid_sources[0x5a]	25682	1			T25	1		T11	1		T31	2
valid_sources[0x5b]	27630	1			T26	1		T28	2		T5	547
valid_sources[0x5c]	25912	1			T1	1		T25	1		T5	550
valid_sources[0x5d]	25901	1			T2	1		T25	1		T27	6
valid_sources[0x5e]	25498	1			T11	1		T5	550		T40	3
valid_sources[0x5f]	27182	1			T3	1		T9	56		T11	2
valid_sources[0x60]	25816	1			T5	565		T40	3		T41	2
valid_sources[0x61]	24612	1			T1	1		T11	1		T31	1
valid_sources[0x62]	25764	1			T1	1		T26	1		T5	500
valid_sources[0x63]	24293	1			T5	558		T50	3		T46	1
valid_sources[0x64]	28171	1			T1	1		T25	1		T5	520
valid_sources[0x65]	24944	1			T25	2		T11	2		T5	533
valid_sources[0x66]	24974	1			T1	1		T2	4		T25	1
valid_sources[0x67]	25756	1			T26	1		T5	477		T40	1
valid_sources[0x68]	24114	1			T11	3		T5	494		T40	1
valid_sources[0x69]	27232	1			T1	1		T3	1		T28	1
valid_sources[0x6a]	26105	1			T1	1		T3	2		T25	1
valid_sources[0x6b]	25681	1			T5	504		T41	1		T50	2
valid_sources[0x6c]	26155	1			T1	2		T26	1		T5	517
valid_sources[0x6d]	24959	1			T25	1		T26	1		T5	526
valid_sources[0x6e]	26014	1			T25	1		T5	535		T41	1
valid_sources[0x6f]	25856	1			T1	2		T3	1		T44	1
valid_sources[0x70]	24599	1			T3	1		T28	1		T5	562
valid_sources[0x71]	25024	1			T3	1		T26	1		T5	524
valid_sources[0x72]	26796	1			T1	1		T2	1		T25	1
valid_sources[0x73]	25973	1			T5	597		T50	1		T81	1
valid_sources[0x74]	24434	1			T3	1		T44	1		T5	580
valid_sources[0x75]	26839	1			T25	1		T5	569		T50	1
valid_sources[0x76]	25083	1			T28	1		T11	3		T5	508
valid_sources[0x77]	26690	1			T5	537		T46	1		T119	2
valid_sources[0x78]	26182	1			T28	2		T5	480		T40	1
valid_sources[0x79]	25179	1			T3	2		T5	545		T50	3
valid_sources[0x7a]	27599	1			T2	6		T11	3		T5	541
valid_sources[0x7b]	26000	1			T3	2		T25	2		T26	1
valid_sources[0x7c]	27128	1			T73	1		T5	554		T50	1
valid_sources[0x7d]	25481	1			T1	1		T2	1		T73	3
valid_sources[0x7e]	27842	1			T11	1		T5	564		T40	1
valid_sources[0x7f]	25520	1			T3	2		T11	2		T5	582
valid_sources[0x80]	24952	1			T5	479		T50	1		T96	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1495881

1

T1

2

T2

12

T3

12

values[0x0]

all_enables

biggest_size

2222423

1

T2

6

T3

25

T4

22

values[0x1]

all_enables

biggest_size

2221274

1

T1

3

T2

5

T3

14