Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
62.50	62.50	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	62.50	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	24	28	53.85

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	24	28	53.85	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2845	1			T4	2		T10	6		T26	1
non_zero_bins[1]	2074	1			T4	1		T9	11		T26	2
zero	9795	1			T1	2		T2	7		T3	4

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	566	1			T5	14		T46	1		T196	1
uni	3940	1			T2	1		T4	1		T9	1
gen	4639	1			T1	1		T2	3		T3	2
res	891	1			T4	1		T9	2		T10	2
ins	4678	1			T1	1		T2	3		T3	2

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

9709

1

T1

2

T2

3

T3

1

mubi_true

5005

1

T2

4

T3

3

T4

2

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

14

1

T78

1

T290

1

T152

1

pass

14700

1

T1

2

T2

7

T3

4

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	24	28	53.85	24
Automatically Generated Cross Bins	52	24	28	53.85	24
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	*	[fail]	*	--	--	6

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	137	1			T5	1		T96	1		T38	2
upd	non_zero_bins[0]	pass	mubi_true	108	1			T5	1		T196	1		T95	1
upd	non_zero_bins[1]	pass	mubi_false	97	1			T5	4		T81	1		T95	1
upd	non_zero_bins[1]	pass	mubi_true	97	1			T5	4		T46	1		T96	1
upd	zero	pass	mubi_false	61	1			T5	2		T39	1		T100	1
upd	zero	pass	mubi_true	66	1			T5	2		T38	2		T98	1
uni	zero	pass	mubi_false	2932	1			T2	1		T4	1		T9	1
uni	zero	pass	mubi_true	1008	1			T25	1		T5	24		T50	4
gen	non_zero_bins[0]	pass	mubi_false	521	1			T4	1		T10	3		T26	1
gen	non_zero_bins[0]	pass	mubi_true	569	1			T5	10		T41	1		T42	1
gen	non_zero_bins[1]	pass	mubi_false	345	1			T5	9		T50	1		T55	1
gen	non_zero_bins[1]	pass	mubi_true	413	1			T9	11		T11	7		T5	5
gen	zero	fail	mubi_false	13	1			T78	1		T290	1		T291	1
gen	zero	pass	mubi_false	2053	1			T1	1		T9	1		T10	1
gen	zero	pass	mubi_true	725	1			T2	3		T3	2		T26	1
res	non_zero_bins[0]	pass	mubi_false	177	1			T10	2		T11	2		T5	1
res	non_zero_bins[0]	pass	mubi_true	216	1			T5	3		T45	1		T48	1
res	non_zero_bins[1]	pass	mubi_false	151	1			T5	3		T38	2		T39	1
res	non_zero_bins[1]	pass	mubi_true	154	1			T4	1		T26	1		T5	2
res	zero	fail	mubi_false	1	1			T152	1		-	-		-	-
res	zero	pass	mubi_false	113	1			T9	2		T5	1		T40	2
res	zero	pass	mubi_true	79	1			T5	2		T39	1		T292	4
ins	non_zero_bins[0]	pass	mubi_false	587	1			T11	1		T5	11		T42	1
ins	non_zero_bins[0]	pass	mubi_true	530	1			T4	1		T10	1		T5	11
ins	non_zero_bins[1]	pass	mubi_false	408	1			T5	11		T40	1		T42	1
ins	non_zero_bins[1]	pass	mubi_true	409	1			T26	1		T5	5		T41	1
ins	zero	pass	mubi_false	2113	1			T1	1		T2	2		T3	1
ins	zero	pass	mubi_true	631	1			T2	1		T3	1		T26	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded