Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.14	100.00	94.44		98.65	97.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	98.14	100.00	94.44		98.65	97.62	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.14	100.00	94.44		98.65	97.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.16	100.00	94.44		98.65	97.73	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.20	100.00	90.59			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		108	108	100.00
ALWAYS	42	3	3	100.00
CONT_ASSIGN	44	1	1	100.00
ALWAYS	47	104	104	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	3	3
44	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
78	1	1
79	1	1
80	1	1
83	1	1
84	1	1
85	1	1
			MISSING_ELSE
89	1	1
90	1	1
93	1	1
94	1	1
			MISSING_ELSE
98	1	1
101	1	1
102	1	1
			MISSING_ELSE
106	1	1
107	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
117	1	1
118	1	1
119	1	1
			MISSING_ELSE
123	1	1
124	1	1
125	1	1
			MISSING_ELSE
129	1	1
130	1	1
131	1	1
			MISSING_ELSE
135	1	1
136	1	1
137	1	1
138	1	1
140	1	1
141	1	1
143	1	1
148	1	1
149	1	1
150	1	1
153	1	1
154	1	1
155	1	1
156	1	1
			MISSING_ELSE
160	1	1
161	1	1
162	1	1
165	1	1
166	1	1
167	1	1
168	1	1
			MISSING_ELSE
172	1	1
175	1	1
178	1	1
186	1	1
188	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
211	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T15,T33,T74
1	1	Covered	T2,T26,T27

 LINE       66
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T20,T56,T69
1	1	Covered	T3,T9,T10

 LINE       186
 EXPRESSION (local_escalate_i || csrng_ack_err_i)
             --------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T27
1	0	Covered	T14,T15,T33

 LINE       188
 EXPRESSION (local_escalate_i ? Error : ((state_q == Error) ? Error : RejectCsrngEntropy))
             --------1-------

-1-	Status	Tests
0	Covered	T2,T3,T27
1	Covered	T14,T15,T33

 LINE       188
 SUB-EXPRESSION ((state_q == Error) ? Error : RejectCsrngEntropy)
                 ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T27
1	Not Covered

 LINE       188
 SUB-EXPRESSION (state_q == Error)
                ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T27
1	Covered	T14,T15,T33

 LINE       201
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	20	100.00	(Not included in score)
Transitions	74	73	98.65
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	156	Covered	T9,T10,T11
AutoCaptGenCnt	143	Covered	T3,T9,T10
AutoCaptReseedCnt	141	Covered	T9,T10,T11
AutoDispatch	125	Covered	T3,T9,T10
AutoFirstAckWait	119	Covered	T3,T9,T10
AutoLoadIns	69	Covered	T3,T9,T10
AutoSendGenCmd	150	Covered	T9,T10,T11
AutoSendReseedCmd	162	Covered	T9,T10,T11
BootDone	98	Covered	T2,T26,T31
BootGenAckWait	90	Covered	T2,T26,T31
BootInsAckWait	80	Covered	T2,T26,T27
BootLoadGen	85	Covered	T2,T26,T27
BootLoadIns	65	Covered	T2,T26,T27
BootLoadUni	102	Covered	T2,T26,T31
BootPulse	94	Covered	T2,T26,T31
BootUniAckWait	107	Covered	T2,T26,T31
Error	188	Covered	T14,T15,T33
Idle	112	Covered	T1,T2,T3
RejectCsrngEntropy	188	Covered	T2,T3,T27
SWPortMode	74	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	131	Covered	T9,T10,T11
AutoAckWait->Error	188	Covered	T112,T113
AutoAckWait->Idle	211	Covered	T20,T69,T114
AutoAckWait->RejectCsrngEntropy	188	Covered	T78,T101,T104
AutoCaptGenCnt->AutoSendGenCmd	150	Covered	T9,T10,T11
AutoCaptGenCnt->Error	188	Covered	T115
AutoCaptGenCnt->Idle	211	Covered	T116,T117,T118
AutoCaptGenCnt->RejectCsrngEntropy	188	Covered	T3,T119,T89
AutoCaptReseedCnt->AutoSendReseedCmd	162	Covered	T9,T10,T11
AutoCaptReseedCnt->Error	188	Covered	T120,T121
AutoCaptReseedCnt->Idle	211	Covered	T122,T123,T124
AutoCaptReseedCnt->RejectCsrngEntropy	188	Covered	T125,T126,T127
AutoDispatch->AutoCaptGenCnt	143	Covered	T3,T9,T10
AutoDispatch->AutoCaptReseedCnt	141	Covered	T9,T10,T11
AutoDispatch->Error	188	Covered	T128
AutoDispatch->Idle	138	Covered	T9,T10,T11
AutoDispatch->RejectCsrngEntropy	188	Covered	T129,T130,T131
AutoFirstAckWait->AutoDispatch	125	Covered	T3,T9,T10
AutoFirstAckWait->Error	188	Covered	T132,T133
AutoFirstAckWait->Idle	211	Covered	T20,T134,T135
AutoFirstAckWait->RejectCsrngEntropy	188	Covered	T80,T136,T137
AutoLoadIns->AutoFirstAckWait	119	Covered	T3,T9,T10
AutoLoadIns->Error	188	Covered	T8,T138,T139
AutoLoadIns->Idle	211	Covered	T3,T27,T85
AutoLoadIns->RejectCsrngEntropy	188	Covered	T21,T140,T141
AutoSendGenCmd->AutoAckWait	156	Covered	T9,T10,T11
AutoSendGenCmd->Error	188	Covered	T142
AutoSendGenCmd->Idle	211	Covered	T143,T144,T145
AutoSendGenCmd->RejectCsrngEntropy	188	Covered	T105,T106,T146
AutoSendReseedCmd->AutoAckWait	168	Covered	T9,T10,T11
AutoSendReseedCmd->Error	188	Covered	T147,T148,T149
AutoSendReseedCmd->Idle	211	Covered	T23,T150,T151
AutoSendReseedCmd->RejectCsrngEntropy	188	Covered	T152,T153,T107
BootDone->BootLoadUni	102	Covered	T2,T26,T31
BootDone->Error	188	Covered	T54,T154,T155
BootDone->Idle	211	Covered	T156,T157,T158
BootDone->RejectCsrngEntropy	188	Covered	T85,T159,T160
BootGenAckWait->BootPulse	94	Covered	T2,T26,T31
BootGenAckWait->Error	188	Covered	T15,T161,T162
BootGenAckWait->Idle	211	Covered	T163,T58,T164
BootGenAckWait->RejectCsrngEntropy	188	Covered	T165,T108,T166
BootInsAckWait->BootLoadGen	85	Covered	T2,T26,T27
BootInsAckWait->Error	188	Covered	T74,T167,T168
BootInsAckWait->Idle	211	Covered	T15,T33,T74
BootInsAckWait->RejectCsrngEntropy	188	Covered	T2,T73,T79
BootLoadGen->BootGenAckWait	90	Covered	T2,T26,T31
BootLoadGen->Error	188	Covered	T76,T169
BootLoadGen->Idle	211	Covered	T170,T171,T172
BootLoadGen->RejectCsrngEntropy	188	Covered	T27,T28,T173
BootLoadIns->BootInsAckWait	80	Covered	T2,T26,T27
BootLoadIns->Error	188	Covered	T53,T174,T175
BootLoadIns->Idle	211	Covered	T176,T177,T178
BootLoadIns->RejectCsrngEntropy	188	Covered	T44,T56,T179
BootLoadUni->BootUniAckWait	107	Covered	T2,T26,T31
BootLoadUni->Error	188	Covered	T180,T181
BootLoadUni->Idle	211	Not Covered
BootLoadUni->RejectCsrngEntropy	188	Covered	T31,T86,T182
BootPulse->BootDone	98	Covered	T2,T26,T31
BootPulse->Error	188	Covered	T183,T184,T185
BootPulse->Idle	211	Covered	T97,T186,T187
BootPulse->RejectCsrngEntropy	188	Covered	T188,T189,T190
BootUniAckWait->Error	188	Covered	T191,T192
BootUniAckWait->Idle	112	Covered	T2,T26,T31
BootUniAckWait->RejectCsrngEntropy	188	Covered	T193,T83,T88
Idle->AutoLoadIns	69	Covered	T3,T9,T10
Idle->BootLoadIns	65	Covered	T2,T26,T27
Idle->Error	188	Covered	T17,T18,T19
Idle->RejectCsrngEntropy	188	Covered	T27,T28,T31
Idle->SWPortMode	74	Covered	T1,T2,T3
RejectCsrngEntropy->Error	188	Covered	T51,T194,T195
RejectCsrngEntropy->Idle	211	Covered	T2,T3,T27
SWPortMode->Error	188	Covered	T14,T16,T77
SWPortMode->Idle	211	Covered	T1,T4,T28
SWPortMode->RejectCsrngEntropy	188	Covered	T2,T3,T44

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		42	41	97.62
IF	42	2	2	100.00
CASE	62	35	35	100.00
IF	186	5	4	80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	42	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	62	case (state_q)
-2-:	64	if ((boot_req_mode_i && edn_enable_i))
-3-:	66	if ((auto_req_mode_i && edn_enable_i))
-4-:	70	if (edn_enable_i)
-5-:	84	if (csrng_cmd_ack_i)
-6-:	93	if (csrng_cmd_ack_i)
-7-:	101	if ((!boot_req_mode_i))
-8-:	110	if (csrng_cmd_ack_i)
-9-:	118	if (sw_cmd_req_load_i)
-10-:	124	if (csrng_cmd_ack_i)
-11-:	130	if (csrng_cmd_ack_i)
-12-:	136	if ((!auto_req_mode_i))
-13-:	140	if (max_reqs_cnt_zero_i)
-14-:	155	if (cmd_sent_i)
-15-:	167	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T26,T27
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T9,T10
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T26,T27
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T2,T26,T27
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T2,T26,T27
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T26,T27
BootGenAckWait	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T2,T26,T31
BootGenAckWait	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T2,T26,T31
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T26,T31
BootDone	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T26,T31
BootDone	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T2,T31,T44
BootLoadUni	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T26,T31
BootUniAckWait	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T26,T55,T196
BootUniAckWait	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T2,T26,T31
AutoLoadIns	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T3,T9,T10
AutoLoadIns	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T3,T9,T10
AutoFirstAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T3,T9,T10
AutoFirstAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T3,T9,T10
AutoAckWait	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T9,T10,T11
AutoAckWait	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T9,T10,T11
AutoDispatch	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T9,T10,T11
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T9,T10,T11
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T3,T9,T10
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T9,T10
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T9,T10,T11
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T9,T10,T11
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T9,T10,T11
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T9,T10,T11
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
RejectCsrngEntropy	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T27
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T15,T33
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T33,T75,T6

	LineNo.	Expression
-1-:	186	if ((local_escalate_i || csrng_ack_err_i))
-2-:	188	(local_escalate_i) ? 
-3-:	188	((state_q == Error)) ? 
-4-:	201	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy})))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T14,T15,T33
1	0	1	-	Not Covered
1	0	0	-	Covered	T2,T3,T27
0	-	-	1	Covered	T1,T2,T3
0	-	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	243839149	144576	0	0
FpvSecCmErrorStEscalate_A	243839149	145619	0	0
u_state_regs_A	243804310	243625110	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	144576	0	0
T6	0	1072	0	0
T7	0	190	0	0
T14	1042	478	0	0
T15	1737	1032	0	0
T16	0	632	0	0
T20	3151	0	0	0
T33	0	303	0	0
T41	2786	0	0	0
T42	3422	0	0	0
T45	2442	0	0	0
T49	1415	0	0	0
T50	8887	0	0	0
T55	1642	0	0	0
T56	1565	0	0	0
T74	0	1134	0	0
T75	0	215	0	0
T76	0	1066	0	0
T77	0	348	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	145619	0	0
T6	0	1073	0	0
T7	0	191	0	0
T14	1042	479	0	0
T15	1737	1033	0	0
T16	0	633	0	0
T20	3151	0	0	0
T33	0	304	0	0
T41	2786	0	0	0
T42	3422	0	0	0
T45	2442	0	0	0
T49	1415	0	0	0
T50	8887	0	0	0
T55	1642	0	0	0
T56	1565	0	0	0
T74	0	1135	0	0
T75	0	216	0	0
T76	0	1067	0	0
T77	0	349	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243804310	243625110	0	0
T1	1125	961	0	0
T2	1768	1697	0	0
T3	2638	2544	0	0
T4	6365	6241	0	0
T9	2877	2813	0	0
T10	6193	6107	0	0
T25	1034	965	0	0
T26	1741	1665	0	0
T27	2525	2428	0	0
T28	2270	2201	0	0