Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.20	100.00	90.59			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.20	100.00	90.59			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.20	100.00	90.59			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.20	100.00	90.59			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.20	100.00	90.59			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.20	100.00	90.59			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.20	100.00	90.59			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T2,T9
DataWait	75	Covered	T1,T2,T9
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T14,T15,T33
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T187,T197
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T2,T9
DataWait->AckPls	80	Covered	T1,T2,T9
DataWait->Disabled	107	Covered	T164,T198,T199
DataWait->Error	99	Covered	T15,T33,T75
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T17,T18,T19
EndPointClear->Disabled	107	Covered	T176,T59,T200
EndPointClear->Error	99	Covered	T17,T53,T201
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T2,T9
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T14,T15,T33

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T2,T9
Idle	-	1	0	-	Covered	T1,T2,T9
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T2,T9
DataWait	-	-	-	0	Covered	T2,T9,T10
AckPls	-	-	-	-	Covered	T1,T2,T9
Error	-	-	-	-	Covered	T14,T15,T33
default	-	-	-	-	Covered	T74,T76,T77

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T14,T15,T33
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	1706874043	1026282	0	0
FpvSecCmErrorStEscalate_A	1706874043	1033583	0	0
u_state_regs_A	1706839204	1705584804	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1706874043	1026282	0	0
T6	0	7854	0	0
T7	0	1680	0	0
T14	7294	3346	0	0
T15	12159	7224	0	0
T16	0	4424	0	0
T20	22057	0	0	0
T33	0	2471	0	0
T41	19502	0	0	0
T42	23954	0	0	0
T45	17094	0	0	0
T49	9905	0	0	0
T50	62209	0	0	0
T55	11494	0	0	0
T56	10955	0	0	0
T74	0	7888	0	0
T75	0	1855	0	0
T76	0	7412	0	0
T77	0	2386	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1706874043	1033583	0	0
T6	0	7861	0	0
T7	0	1687	0	0
T14	7294	3353	0	0
T15	12159	7231	0	0
T16	0	4431	0	0
T20	22057	0	0	0
T33	0	2478	0	0
T41	19502	0	0	0
T42	23954	0	0	0
T45	17094	0	0	0
T49	9905	0	0	0
T50	62209	0	0	0
T55	11494	0	0	0
T56	10955	0	0	0
T74	0	7895	0	0
T75	0	1862	0	0
T76	0	7419	0	0
T77	0	2393	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1706839204	1705584804	0	0
T1	7959	6811	0	0
T2	12376	11879	0	0
T3	18466	17808	0	0
T4	44555	43687	0	0
T9	20139	19691	0	0
T10	43351	42749	0	0
T25	7238	6755	0	0
T26	12187	11655	0	0
T27	17675	16996	0	0
T28	15890	15407	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T2,T9,T40
DataWait	75	Covered	T2,T9,T40
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T14,T15,T33
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T2,T9,T40
DataWait->AckPls	80	Covered	T2,T9,T40
DataWait->Disabled	107	Covered	T164,T202
DataWait->Error	99	Covered	T185,T192,T203
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T17,T18,T19
EndPointClear->Disabled	107	Covered	T176,T59,T200
EndPointClear->Error	99	Covered	T17,T53,T201
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T2,T9,T40
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T14,T15,T33

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T2,T9,T40
Idle	-	1	0	-	Covered	T2,T9,T40
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T2,T9,T40
DataWait	-	-	-	0	Covered	T2,T9,T40
AckPls	-	-	-	-	Covered	T2,T9,T40
Error	-	-	-	-	Covered	T14,T15,T33
default	-	-	-	-	Covered	T17,T18,T19

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T14,T15,T33
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	243839149	146876	0	0
FpvSecCmErrorStEscalate_A	243839149	147919	0	0
u_state_regs_A	243839149	243659949	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	146876	0	0
T6	0	1122	0	0
T7	0	240	0	0
T14	1042	478	0	0
T15	1737	1032	0	0
T16	0	632	0	0
T20	3151	0	0	0
T33	0	353	0	0
T41	2786	0	0	0
T42	3422	0	0	0
T45	2442	0	0	0
T49	1415	0	0	0
T50	8887	0	0	0
T55	1642	0	0	0
T56	1565	0	0	0
T74	0	1134	0	0
T75	0	265	0	0
T76	0	1066	0	0
T77	0	348	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	147919	0	0
T6	0	1123	0	0
T7	0	241	0	0
T14	1042	479	0	0
T15	1737	1033	0	0
T16	0	633	0	0
T20	3151	0	0	0
T33	0	354	0	0
T41	2786	0	0	0
T42	3422	0	0	0
T45	2442	0	0	0
T49	1415	0	0	0
T50	8887	0	0	0
T55	1642	0	0	0
T56	1565	0	0	0
T74	0	1135	0	0
T75	0	266	0	0
T76	0	1067	0	0
T77	0	349	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	243659949	0	0
T1	1139	975	0	0
T2	1768	1697	0	0
T3	2638	2544	0	0
T4	6365	6241	0	0
T9	2877	2813	0	0
T10	6193	6107	0	0
T25	1034	965	0	0
T26	1741	1665	0	0
T27	2525	2428	0	0
T28	2270	2201	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T9,T27
DataWait	75	Covered	T1,T9,T27
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T14,T15,T33
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T9,T27
DataWait->AckPls	80	Covered	T1,T9,T27
DataWait->Disabled	107	Covered	T204,T205,T206
DataWait->Error	99	Covered	T75,T207,T208
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T17,T18,T19
EndPointClear->Disabled	107	Covered	T176,T59,T200
EndPointClear->Error	99	Covered	T17,T53,T201
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T9,T27
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T14,T15,T33

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T9,T27
Idle	-	1	0	-	Covered	T1,T9,T27
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T9,T27
DataWait	-	-	-	0	Covered	T9,T27,T11
AckPls	-	-	-	-	Covered	T1,T9,T27
Error	-	-	-	-	Covered	T14,T15,T33
default	-	-	-	-	Covered	T17,T18,T19

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T14,T15,T33
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	243839149	146876	0	0
FpvSecCmErrorStEscalate_A	243839149	147919	0	0
u_state_regs_A	243839149	243659949	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	146876	0	0
T6	0	1122	0	0
T7	0	240	0	0
T14	1042	478	0	0
T15	1737	1032	0	0
T16	0	632	0	0
T20	3151	0	0	0
T33	0	353	0	0
T41	2786	0	0	0
T42	3422	0	0	0
T45	2442	0	0	0
T49	1415	0	0	0
T50	8887	0	0	0
T55	1642	0	0	0
T56	1565	0	0	0
T74	0	1134	0	0
T75	0	265	0	0
T76	0	1066	0	0
T77	0	348	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	147919	0	0
T6	0	1123	0	0
T7	0	241	0	0
T14	1042	479	0	0
T15	1737	1033	0	0
T16	0	633	0	0
T20	3151	0	0	0
T33	0	354	0	0
T41	2786	0	0	0
T42	3422	0	0	0
T45	2442	0	0	0
T49	1415	0	0	0
T50	8887	0	0	0
T55	1642	0	0	0
T56	1565	0	0	0
T74	0	1135	0	0
T75	0	266	0	0
T76	0	1067	0	0
T77	0	349	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	243659949	0	0
T1	1139	975	0	0
T2	1768	1697	0	0
T3	2638	2544	0	0
T4	6365	6241	0	0
T9	2877	2813	0	0
T10	6193	6107	0	0
T25	1034	965	0	0
T26	1741	1665	0	0
T27	2525	2428	0	0
T28	2270	2201	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T3,T41,T42
DataWait	75	Covered	T3,T41,T42
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T14,T15,T33
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T3,T41,T42
DataWait->AckPls	80	Covered	T3,T41,T42
DataWait->Disabled	107	Covered	T198,T116,T209
DataWait->Error	99	Covered	T210,T161,T211
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T17,T18,T19
EndPointClear->Disabled	107	Covered	T176,T59,T200
EndPointClear->Error	99	Covered	T17,T53,T201
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T3,T41,T42
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T14,T15,T33

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T3,T41,T42
Idle	-	1	0	-	Covered	T3,T41,T42
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T3,T41,T42
DataWait	-	-	-	0	Covered	T3,T41,T42
AckPls	-	-	-	-	Covered	T3,T41,T42
Error	-	-	-	-	Covered	T14,T15,T33
default	-	-	-	-	Covered	T17,T18,T19

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T14,T15,T33
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	243839149	146876	0	0
FpvSecCmErrorStEscalate_A	243839149	147919	0	0
u_state_regs_A	243839149	243659949	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	146876	0	0
T6	0	1122	0	0
T7	0	240	0	0
T14	1042	478	0	0
T15	1737	1032	0	0
T16	0	632	0	0
T20	3151	0	0	0
T33	0	353	0	0
T41	2786	0	0	0
T42	3422	0	0	0
T45	2442	0	0	0
T49	1415	0	0	0
T50	8887	0	0	0
T55	1642	0	0	0
T56	1565	0	0	0
T74	0	1134	0	0
T75	0	265	0	0
T76	0	1066	0	0
T77	0	348	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	147919	0	0
T6	0	1123	0	0
T7	0	241	0	0
T14	1042	479	0	0
T15	1737	1033	0	0
T16	0	633	0	0
T20	3151	0	0	0
T33	0	354	0	0
T41	2786	0	0	0
T42	3422	0	0	0
T45	2442	0	0	0
T49	1415	0	0	0
T50	8887	0	0	0
T55	1642	0	0	0
T56	1565	0	0	0
T74	0	1135	0	0
T75	0	266	0	0
T76	0	1067	0	0
T77	0	349	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	243659949	0	0
T1	1139	975	0	0
T2	1768	1697	0	0
T3	2638	2544	0	0
T4	6365	6241	0	0
T9	2877	2813	0	0
T10	6193	6107	0	0
T25	1034	965	0	0
T26	1741	1665	0	0
T27	2525	2428	0	0
T28	2270	2201	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T9,T41,T42
DataWait	75	Covered	T9,T41,T42
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T14,T15,T33
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T9,T41,T42
DataWait->AckPls	80	Covered	T9,T41,T42
DataWait->Disabled	107	Covered	T212,T213,T214
DataWait->Error	99	Covered	T74,T113,T215
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T17,T18,T19
EndPointClear->Disabled	107	Covered	T176,T59,T200
EndPointClear->Error	99	Covered	T17,T53,T201
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T9,T41,T42
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T14,T15,T33

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T9,T41,T42
Idle	-	1	0	-	Covered	T9,T41,T42
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T9,T41,T42
DataWait	-	-	-	0	Covered	T9,T41,T42
AckPls	-	-	-	-	Covered	T9,T41,T42
Error	-	-	-	-	Covered	T14,T15,T33
default	-	-	-	-	Covered	T17,T18,T19

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T14,T15,T33
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	243839149	146876	0	0
FpvSecCmErrorStEscalate_A	243839149	147919	0	0
u_state_regs_A	243839149	243659949	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	146876	0	0
T6	0	1122	0	0
T7	0	240	0	0
T14	1042	478	0	0
T15	1737	1032	0	0
T16	0	632	0	0
T20	3151	0	0	0
T33	0	353	0	0
T41	2786	0	0	0
T42	3422	0	0	0
T45	2442	0	0	0
T49	1415	0	0	0
T50	8887	0	0	0
T55	1642	0	0	0
T56	1565	0	0	0
T74	0	1134	0	0
T75	0	265	0	0
T76	0	1066	0	0
T77	0	348	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	147919	0	0
T6	0	1123	0	0
T7	0	241	0	0
T14	1042	479	0	0
T15	1737	1033	0	0
T16	0	633	0	0
T20	3151	0	0	0
T33	0	354	0	0
T41	2786	0	0	0
T42	3422	0	0	0
T45	2442	0	0	0
T49	1415	0	0	0
T50	8887	0	0	0
T55	1642	0	0	0
T56	1565	0	0	0
T74	0	1135	0	0
T75	0	266	0	0
T76	0	1067	0	0
T77	0	349	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	243659949	0	0
T1	1139	975	0	0
T2	1768	1697	0	0
T3	2638	2544	0	0
T4	6365	6241	0	0
T9	2877	2813	0	0
T10	6193	6107	0	0
T25	1034	965	0	0
T26	1741	1665	0	0
T27	2525	2428	0	0
T28	2270	2201	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T9,T40,T42
DataWait	75	Covered	T9,T40,T42
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T14,T15,T33
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T9,T40,T42
DataWait->AckPls	80	Covered	T9,T40,T42
DataWait->Disabled	107	Covered	T117,T216
DataWait->Error	99	Covered	T184,T217
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T17,T18,T19
EndPointClear->Disabled	107	Covered	T176,T59,T200
EndPointClear->Error	99	Covered	T17,T53,T201
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T9,T40,T42
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T14,T15,T33

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T9,T40,T42
Idle	-	1	0	-	Covered	T9,T40,T42
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T9,T40,T42
DataWait	-	-	-	0	Covered	T9,T40,T42
AckPls	-	-	-	-	Covered	T9,T40,T42
Error	-	-	-	-	Covered	T14,T15,T33
default	-	-	-	-	Covered	T17,T18,T19

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T14,T15,T33
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	243839149	146876	0	0
FpvSecCmErrorStEscalate_A	243839149	147919	0	0
u_state_regs_A	243839149	243659949	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	146876	0	0
T6	0	1122	0	0
T7	0	240	0	0
T14	1042	478	0	0
T15	1737	1032	0	0
T16	0	632	0	0
T20	3151	0	0	0
T33	0	353	0	0
T41	2786	0	0	0
T42	3422	0	0	0
T45	2442	0	0	0
T49	1415	0	0	0
T50	8887	0	0	0
T55	1642	0	0	0
T56	1565	0	0	0
T74	0	1134	0	0
T75	0	265	0	0
T76	0	1066	0	0
T77	0	348	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	147919	0	0
T6	0	1123	0	0
T7	0	241	0	0
T14	1042	479	0	0
T15	1737	1033	0	0
T16	0	633	0	0
T20	3151	0	0	0
T33	0	354	0	0
T41	2786	0	0	0
T42	3422	0	0	0
T45	2442	0	0	0
T49	1415	0	0	0
T50	8887	0	0	0
T55	1642	0	0	0
T56	1565	0	0	0
T74	0	1135	0	0
T75	0	266	0	0
T76	0	1067	0	0
T77	0	349	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	243659949	0	0
T1	1139	975	0	0
T2	1768	1697	0	0
T3	2638	2544	0	0
T4	6365	6241	0	0
T9	2877	2813	0	0
T10	6193	6107	0	0
T25	1034	965	0	0
T26	1741	1665	0	0
T27	2525	2428	0	0
T28	2270	2201	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T9,T10,T25
DataWait	75	Covered	T9,T10,T25
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T14,T15,T33
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T187
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T9,T10,T25
DataWait->AckPls	80	Covered	T9,T10,T25
DataWait->Disabled	107	Covered	T199,T145,T218
DataWait->Error	99	Covered	T15,T33,T6
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T17,T18,T19
EndPointClear->Disabled	107	Covered	T176,T59,T200
EndPointClear->Error	99	Covered	T17,T53,T201
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T9,T10,T25
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T14,T75,T16

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T9,T10,T25
Idle	-	1	0	-	Covered	T9,T10,T25
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T9,T10,T25
DataWait	-	-	-	0	Covered	T9,T10,T25
AckPls	-	-	-	-	Covered	T9,T10,T25
Error	-	-	-	-	Covered	T14,T15,T33
default	-	-	-	-	Covered	T74,T76,T77

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T14,T15,T33
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	243839149	145026	0	0
FpvSecCmErrorStEscalate_A	243839149	146069	0	0
u_state_regs_A	243804310	243625110	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	145026	0	0
T6	0	1122	0	0
T7	0	240	0	0
T14	1042	478	0	0
T15	1737	1032	0	0
T16	0	632	0	0
T20	3151	0	0	0
T33	0	353	0	0
T41	2786	0	0	0
T42	3422	0	0	0
T45	2442	0	0	0
T49	1415	0	0	0
T50	8887	0	0	0
T55	1642	0	0	0
T56	1565	0	0	0
T74	0	1084	0	0
T75	0	265	0	0
T76	0	1016	0	0
T77	0	298	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	146069	0	0
T6	0	1123	0	0
T7	0	241	0	0
T14	1042	479	0	0
T15	1737	1033	0	0
T16	0	633	0	0
T20	3151	0	0	0
T33	0	354	0	0
T41	2786	0	0	0
T42	3422	0	0	0
T45	2442	0	0	0
T49	1415	0	0	0
T50	8887	0	0	0
T55	1642	0	0	0
T56	1565	0	0	0
T74	0	1085	0	0
T75	0	266	0	0
T76	0	1017	0	0
T77	0	299	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243804310	243625110	0	0
T1	1125	961	0	0
T2	1768	1697	0	0
T3	2638	2544	0	0
T4	6365	6241	0	0
T9	2877	2813	0	0
T10	6193	6107	0	0
T25	1034	965	0	0
T26	1741	1665	0	0
T27	2525	2428	0	0
T28	2270	2201	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T28,T40,T41
DataWait	75	Covered	T28,T40,T41
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T14,T15,T33
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T197
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T28,T40,T41
DataWait->AckPls	80	Covered	T28,T40,T41
DataWait->Disabled	107	Covered	T143,T144,T219
DataWait->Error	99	Covered	T7,T157,T220
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T17,T18,T19
EndPointClear->Disabled	107	Covered	T176,T59,T200
EndPointClear->Error	99	Covered	T17,T53,T201
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T28,T40,T41
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T14,T15,T33

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T28,T40,T41
Idle	-	1	0	-	Covered	T28,T40,T41
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T28,T40,T41
DataWait	-	-	-	0	Covered	T28,T40,T41
AckPls	-	-	-	-	Covered	T28,T40,T41
Error	-	-	-	-	Covered	T14,T15,T33
default	-	-	-	-	Covered	T17,T18,T19

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T14,T15,T33
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	243839149	146876	0	0
FpvSecCmErrorStEscalate_A	243839149	147919	0	0
u_state_regs_A	243839149	243659949	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	146876	0	0
T6	0	1122	0	0
T7	0	240	0	0
T14	1042	478	0	0
T15	1737	1032	0	0
T16	0	632	0	0
T20	3151	0	0	0
T33	0	353	0	0
T41	2786	0	0	0
T42	3422	0	0	0
T45	2442	0	0	0
T49	1415	0	0	0
T50	8887	0	0	0
T55	1642	0	0	0
T56	1565	0	0	0
T74	0	1134	0	0
T75	0	265	0	0
T76	0	1066	0	0
T77	0	348	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	147919	0	0
T6	0	1123	0	0
T7	0	241	0	0
T14	1042	479	0	0
T15	1737	1033	0	0
T16	0	633	0	0
T20	3151	0	0	0
T33	0	354	0	0
T41	2786	0	0	0
T42	3422	0	0	0
T45	2442	0	0	0
T49	1415	0	0	0
T50	8887	0	0	0
T55	1642	0	0	0
T56	1565	0	0	0
T74	0	1135	0	0
T75	0	266	0	0
T76	0	1067	0	0
T77	0	349	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243839149	243659949	0	0
T1	1139	975	0	0
T2	1768	1697	0	0
T3	2638	2544	0	0
T4	6365	6241	0	0
T9	2877	2813	0	0
T10	6193	6107	0	0
T25	1034	965	0	0
T26	1741	1665	0	0
T27	2525	2428	0	0
T28	2270	2201	0	0