Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	652104	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5224701

1

T1

54

T2

38

T3

9

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1554581	1			T1	12		T2	289		T3	21
values[0x0]	1998492	1			T1	26		T2	18		T3	5
values[0x1]	2323732	1			T1	30		T2	17		T3	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	323824	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5552981

1

T1

59

T2

129

T3

14

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	21278	1			T2	1		T24	1		T46	2
valid_sources[0x01]	25616	1			T24	1		T31	1		T11	3
valid_sources[0x02]	21977	1			T27	4		T10	1		T75	8
valid_sources[0x03]	22361	1			T1	2		T2	2		T24	1
valid_sources[0x04]	22323	1			T1	1		T23	1		T27	4
valid_sources[0x05]	21653	1			T2	1		T24	1		T46	1
valid_sources[0x06]	25950	1			T46	3		T76	1		T19	1
valid_sources[0x07]	23464	1			T1	2		T49	1		T300	1
valid_sources[0x08]	23961	1			T1	1		T24	1		T112	1
valid_sources[0x09]	24322	1			T24	1		T16	29		T32	2
valid_sources[0x0a]	21990	1			T27	1		T31	1		T75	5
valid_sources[0x0b]	22627	1			T1	1		T24	2		T46	1
valid_sources[0x0c]	24969	1			T2	1		T46	2		T11	1
valid_sources[0x0d]	21336	1			T2	4		T24	1		T4	1
valid_sources[0x0e]	22668	1			T2	1		T31	1		T42	1
valid_sources[0x0f]	24502	1			T24	1		T12	2		T49	2
valid_sources[0x10]	22774	1			T24	1		T75	1		T112	8
valid_sources[0x11]	20811	1			T2	4		T46	3		T63	1
valid_sources[0x12]	26034	1			T24	1		T27	2		T10	1
valid_sources[0x13]	21928	1			T2	1		T27	2		T32	2
valid_sources[0x14]	22381	1			T26	168		T10	1		T32	2
valid_sources[0x15]	23778	1			T2	6		T6	1		T19	4
valid_sources[0x16]	25658	1			T2	3		T31	1		T47	3
valid_sources[0x17]	25328	1			T27	2		T108	2		T97	1
valid_sources[0x18]	23445	1			T2	3		T4	3		T19	4
valid_sources[0x19]	24442	1			T24	1		T46	1		T10	3
valid_sources[0x1a]	21395	1			T2	1		T24	1		T27	1
valid_sources[0x1b]	23645	1			T4	6		T10	1		T19	4
valid_sources[0x1c]	22494	1			T32	1		T42	1		T97	1
valid_sources[0x1d]	23792	1			T46	3		T10	2		T11	1
valid_sources[0x1e]	22682	1			T46	1		T6	3		T108	1
valid_sources[0x1f]	20343	1			T46	1		T31	1		T108	1
valid_sources[0x20]	22853	1			T1	1		T2	6		T108	1
valid_sources[0x21]	21842	1			T24	1		T46	3		T31	2
valid_sources[0x22]	21015	1			T27	5		T108	4		T19	1
valid_sources[0x23]	22533	1			T2	9		T23	1		T46	3
valid_sources[0x24]	22814	1			T11	4		T93	1		T110	4
valid_sources[0x25]	22199	1			T24	2		T32	2		T97	1
valid_sources[0x26]	21965	1			T24	1		T6	1		T42	1
valid_sources[0x27]	22451	1			T27	2		T19	1		T12	2
valid_sources[0x28]	24365	1			T10	1		T19	1		T49	4
valid_sources[0x29]	22512	1			T1	1		T14	19		T19	1
valid_sources[0x2a]	23514	1			T27	9		T31	2		T19	1
valid_sources[0x2b]	22530	1			T1	2		T4	2		T10	1
valid_sources[0x2c]	22769	1			T27	3		T108	1		T97	1
valid_sources[0x2d]	21586	1			T1	1		T4	2		T46	1
valid_sources[0x2e]	21343	1			T2	3		T27	2		T32	1
valid_sources[0x2f]	24692	1			T46	4		T32	4		T108	1
valid_sources[0x30]	22304	1			T1	1		T2	2		T24	1
valid_sources[0x31]	23840	1			T27	1		T46	2		T10	1
valid_sources[0x32]	23858	1			T32	2		T42	1		T108	1
valid_sources[0x33]	22993	1			T46	5		T75	6		T97	1
valid_sources[0x34]	24981	1			T2	4		T27	1		T97	1
valid_sources[0x35]	23368	1			T23	2		T24	1		T10	1
valid_sources[0x36]	22550	1			T24	1		T63	1		T106	2
valid_sources[0x37]	22693	1			T27	3		T32	4		T75	4
valid_sources[0x38]	23019	1			T1	1		T46	6		T42	3
valid_sources[0x39]	22975	1			T46	2		T15	637		T43	1
valid_sources[0x3a]	23554	1			T24	1		T4	1		T42	1
valid_sources[0x3b]	22450	1			T1	1		T46	4		T75	6
valid_sources[0x3c]	20179	1			T2	3		T31	9		T42	1
valid_sources[0x3d]	22129	1			T46	2		T108	1		T19	2
valid_sources[0x3e]	24246	1			T1	2		T10	1		T19	1
valid_sources[0x3f]	21258	1			T42	3		T19	1		T93	4
valid_sources[0x40]	22560	1			T108	1		T12	1		T110	7
valid_sources[0x41]	23538	1			T27	2		T10	1		T97	4
valid_sources[0x42]	20995	1			T24	2		T27	2		T46	2
valid_sources[0x43]	22295	1			T31	1		T75	3		T76	1
valid_sources[0x44]	23667	1			T42	2		T76	1		T12	3
valid_sources[0x45]	21524	1			T2	17		T42	1		T97	8
valid_sources[0x46]	24458	1			T27	6		T42	1		T62	82
valid_sources[0x47]	22303	1			T1	1		T11	1		T42	3
valid_sources[0x48]	24878	1			T24	2		T10	3		T32	2
valid_sources[0x49]	22919	1			T27	1		T46	1		T10	1
valid_sources[0x4a]	23337	1			T2	5		T27	2		T10	3
valid_sources[0x4b]	22225	1			T1	1		T6	1		T108	3
valid_sources[0x4c]	23629	1			T46	3		T10	1		T75	2
valid_sources[0x4d]	23116	1			T24	1		T27	2		T46	2
valid_sources[0x4e]	22062	1			T31	1		T75	3		T42	2
valid_sources[0x4f]	23313	1			T46	1		T76	1		T112	1
valid_sources[0x50]	23278	1			T46	1		T32	2		T14	8
valid_sources[0x51]	23565	1			T47	4		T108	1		T19	1
valid_sources[0x52]	21610	1			T24	1		T32	1		T14	4
valid_sources[0x53]	22687	1			T2	2		T46	1		T93	1
valid_sources[0x54]	22710	1			T1	1		T46	6		T32	1
valid_sources[0x55]	23372	1			T24	2		T10	1		T19	1
valid_sources[0x56]	23608	1			T2	2		T19	2		T12	1
valid_sources[0x57]	21700	1			T2	3		T27	1		T46	5
valid_sources[0x58]	23514	1			T1	1		T27	3		T46	1
valid_sources[0x59]	22485	1			T1	1		T46	3		T19	2
valid_sources[0x5a]	23775	1			T1	1		T2	4		T14	6
valid_sources[0x5b]	22910	1			T1	1		T46	1		T42	1
valid_sources[0x5c]	22863	1			T1	1		T46	1		T31	1
valid_sources[0x5d]	22466	1			T2	1		T46	3		T55	1
valid_sources[0x5e]	22431	1			T46	1		T31	1		T11	1
valid_sources[0x5f]	23335	1			T46	3		T31	1		T42	1
valid_sources[0x60]	23830	1			T24	1		T27	1		T108	2
valid_sources[0x61]	24618	1			T24	1		T27	1		T10	2
valid_sources[0x62]	23163	1			T27	1		T11	1		T42	1
valid_sources[0x63]	23474	1			T46	2		T10	2		T49	2
valid_sources[0x64]	21379	1			T2	1		T24	1		T31	1
valid_sources[0x65]	24234	1			T49	1		T300	1		T45	1
valid_sources[0x66]	24410	1			T19	1		T106	1		T45	2
valid_sources[0x67]	24723	1			T1	1		T2	3		T24	2
valid_sources[0x68]	22428	1			T1	2		T24	1		T27	1
valid_sources[0x69]	24998	1			T2	15		T24	1		T46	3
valid_sources[0x6a]	21858	1			T4	1		T27	3		T46	1
valid_sources[0x6b]	22412	1			T2	10		T42	1		T19	3
valid_sources[0x6c]	23735	1			T2	1		T46	2		T42	1
valid_sources[0x6d]	22489	1			T42	2		T108	1		T76	1
valid_sources[0x6e]	21608	1			T1	1		T24	2		T27	1
valid_sources[0x6f]	22921	1			T2	1		T24	2		T31	1
valid_sources[0x70]	23747	1			T1	1		T10	1		T108	3
valid_sources[0x71]	23060	1			T24	1		T46	1		T108	1
valid_sources[0x72]	23063	1			T11	1		T19	1		T93	5
valid_sources[0x73]	23705	1			T1	1		T46	1		T19	2
valid_sources[0x74]	21847	1			T108	1		T93	1		T112	1
valid_sources[0x75]	22438	1			T46	4		T10	1		T48	111
valid_sources[0x76]	23506	1			T27	5		T46	5		T32	1
valid_sources[0x77]	22893	1			T46	2		T47	27		T76	1
valid_sources[0x78]	24672	1			T1	1		T16	18		T31	1
valid_sources[0x79]	23630	1			T10	2		T31	2		T32	2
valid_sources[0x7a]	22579	1			T1	1		T2	8		T24	1
valid_sources[0x7b]	21136	1			T108	2		T76	1		T19	2
valid_sources[0x7c]	22264	1			T1	1		T24	2		T27	1
valid_sources[0x7d]	21012	1			T1	1		T24	1		T4	2
valid_sources[0x7e]	21963	1			T46	4		T76	1		T19	1
valid_sources[0x7f]	23556	1			T1	2		T6	3		T108	2
valid_sources[0x80]	23004	1			T46	4		T31	1		T39	64

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1315692

1

T1

3

T2

6

T3

4

values[0x0]

all_enables

biggest_size

1956090

1

T1

24

T2

17

T3

4

values[0x1]

all_enables

biggest_size

1952919

1

T1

27

T2

15

T3

1