Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
62.50	62.50	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	62.50	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	24	28	53.85

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	24	28	53.85	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2757	1			T1	1		T2	1		T24	1
non_zero_bins[1]	1852	1			T2	2		T24	2		T26	1
zero	9229	1			T1	2		T2	1		T3	3

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	529	1			T24	1		T26	1		T48	1
uni	3649	1			T2	1		T3	1		T24	1
gen	4393	1			T2	1		T3	1		T23	2
res	871	1			T1	2		T2	1		T27	1
ins	4396	1			T1	1		T2	1		T3	1

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

9080

1

T1

1

T2

2

T3

3

mubi_true

4758

1

T1

2

T2

2

T23

2

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

16

1

T32

1

T78

1

T79

1

pass

13822

1

T1

3

T2

4

T3

3

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	24	28	53.85	24
Automatically Generated Cross Bins	52	24	28	53.85	24
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	*	[fail]	*	--	--	6

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	119	1			T39	1		T40	1		T104	2
upd	non_zero_bins[0]	pass	mubi_true	120	1			T65	1		T41	2		T104	1
upd	non_zero_bins[1]	pass	mubi_false	86	1			T48	1		T39	1		T52	1
upd	non_zero_bins[1]	pass	mubi_true	88	1			T24	1		T71	1		T68	1
upd	zero	pass	mubi_false	57	1			T26	1		T42	1		T62	1
upd	zero	pass	mubi_true	59	1			T40	1		T68	1		T104	1
uni	zero	pass	mubi_false	2739	1			T2	1		T3	1		T24	1
uni	zero	pass	mubi_true	910	1			T108	1		T111	1		T39	7
gen	non_zero_bins[0]	pass	mubi_false	492	1			T10	15		T48	1		T108	1
gen	non_zero_bins[0]	pass	mubi_true	566	1			T2	1		T26	1		T14	4
gen	non_zero_bins[1]	pass	mubi_false	323	1			T24	1		T27	1		T10	1
gen	non_zero_bins[1]	pass	mubi_true	328	1			T19	1		T45	1		T39	3
gen	zero	fail	mubi_false	10	1			T32	1		T298	1		T299	1
gen	zero	pass	mubi_false	1870	1			T3	1		T4	1		T5	1
gen	zero	pass	mubi_true	804	1			T23	2		T5	1		T25	2
res	non_zero_bins[0]	pass	mubi_false	225	1			T75	1		T14	2		T19	2
res	non_zero_bins[0]	pass	mubi_true	188	1			T27	1		T300	1		T241	1
res	non_zero_bins[1]	pass	mubi_false	116	1			T106	1		T40	1		T52	1
res	non_zero_bins[1]	pass	mubi_true	139	1			T2	1		T39	1		T40	1
res	zero	fail	mubi_false	6	1			T78	1		T79	1		T50	1
res	zero	pass	mubi_false	111	1			T10	2		T12	2		T49	1
res	zero	pass	mubi_true	86	1			T1	2		T22	2		T45	1
ins	non_zero_bins[0]	pass	mubi_false	532	1			T1	1		T24	1		T46	1
ins	non_zero_bins[0]	pass	mubi_true	515	1			T46	1		T10	1		T48	1
ins	non_zero_bins[1]	pass	mubi_false	395	1			T2	1		T27	1		T14	1
ins	non_zero_bins[1]	pass	mubi_true	377	1			T26	1		T65	1		T39	3
ins	zero	pass	mubi_false	1999	1			T3	1		T23	2		T4	1
ins	zero	pass	mubi_true	578	1			T5	2		T25	2		T26	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded