Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.60	100.00	94.44		95.95	97.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	97.60	100.00	94.44		95.95	97.62	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.60	100.00	94.44		95.95	97.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.62	100.00	94.44		95.95	97.73	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		108	108	100.00
ALWAYS	42	3	3	100.00
CONT_ASSIGN	44	1	1	100.00
ALWAYS	47	104	104	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	3	3
44	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
78	1	1
79	1	1
80	1	1
83	1	1
84	1	1
85	1	1
			MISSING_ELSE
89	1	1
90	1	1
93	1	1
94	1	1
			MISSING_ELSE
98	1	1
101	1	1
102	1	1
			MISSING_ELSE
106	1	1
107	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
117	1	1
118	1	1
119	1	1
			MISSING_ELSE
123	1	1
124	1	1
125	1	1
			MISSING_ELSE
129	1	1
130	1	1
131	1	1
			MISSING_ELSE
135	1	1
136	1	1
137	1	1
138	1	1
140	1	1
141	1	1
143	1	1
148	1	1
149	1	1
150	1	1
153	1	1
154	1	1
155	1	1
156	1	1
			MISSING_ELSE
160	1	1
161	1	1
162	1	1
165	1	1
166	1	1
167	1	1
168	1	1
			MISSING_ELSE
172	1	1
175	1	1
178	1	1
186	1	1
188	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
211	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T23,T5,T25
1	1	Covered	T23,T5,T25

 LINE       66
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T24
1	0	Covered	T1,T32,T76
1	1	Covered	T1,T16,T10

 LINE       186
 EXPRESSION (local_escalate_i || csrng_ack_err_i)
             --------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T16,T31,T32
1	0	Covered	T4,T5,T6

 LINE       188
 EXPRESSION (local_escalate_i ? Error : ((state_q == Error) ? Error : RejectCsrngEntropy))
             --------1-------

-1-	Status	Tests
0	Covered	T16,T31,T32
1	Covered	T4,T5,T6

 LINE       188
 SUB-EXPRESSION ((state_q == Error) ? Error : RejectCsrngEntropy)
                 ---------1--------

-1-	Status	Tests
0	Covered	T16,T31,T32
1	Not Covered

 LINE       188
 SUB-EXPRESSION (state_q == Error)
                ---------1--------

-1-	Status	Tests
0	Covered	T4,T5,T16
1	Covered	T4,T5,T6

 LINE       201
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T23,T5

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	20	100.00	(Not included in score)
Transitions	74	71	95.95
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	156	Covered	T1,T10,T14
AutoCaptGenCnt	143	Covered	T1,T10,T14
AutoCaptReseedCnt	141	Covered	T1,T10,T14
AutoDispatch	125	Covered	T1,T10,T14
AutoFirstAckWait	119	Covered	T1,T10,T11
AutoLoadIns	69	Covered	T1,T16,T10
AutoSendGenCmd	150	Covered	T1,T10,T14
AutoSendReseedCmd	162	Covered	T1,T10,T14
BootDone	98	Covered	T23,T5,T25
BootGenAckWait	90	Covered	T23,T5,T25
BootInsAckWait	80	Covered	T23,T5,T25
BootLoadGen	85	Covered	T23,T5,T25
BootLoadIns	65	Covered	T23,T5,T25
BootLoadUni	102	Covered	T26,T48,T31
BootPulse	94	Covered	T23,T5,T25
BootUniAckWait	107	Covered	T26,T48,T31
Error	188	Covered	T4,T5,T6
Idle	112	Covered	T1,T2,T3
RejectCsrngEntropy	188	Covered	T16,T31,T32
SWPortMode	74	Covered	T2,T3,T24

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	131	Covered	T1,T10,T14
AutoAckWait->Error	188	Covered	T120,T121,T122
AutoAckWait->Idle	211	Covered	T1,T20,T21
AutoAckWait->RejectCsrngEntropy	188	Covered	T112,T123,T124
AutoCaptGenCnt->AutoSendGenCmd	150	Covered	T1,T10,T14
AutoCaptGenCnt->Error	188	Covered	T125,T126,T127
AutoCaptGenCnt->Idle	211	Covered	T91,T128,T129
AutoCaptGenCnt->RejectCsrngEntropy	188	Covered	T130,T114,T131
AutoCaptReseedCnt->AutoSendReseedCmd	162	Covered	T1,T10,T14
AutoCaptReseedCnt->Error	188	Not Covered
AutoCaptReseedCnt->Idle	211	Covered	T132,T133,T134
AutoCaptReseedCnt->RejectCsrngEntropy	188	Covered	T135,T136,T137
AutoDispatch->AutoCaptGenCnt	143	Covered	T1,T10,T14
AutoDispatch->AutoCaptReseedCnt	141	Covered	T1,T10,T14
AutoDispatch->Error	188	Covered	T138,T139
AutoDispatch->Idle	138	Covered	T10,T14,T22
AutoDispatch->RejectCsrngEntropy	188	Covered	T140,T141,T142
AutoFirstAckWait->AutoDispatch	125	Covered	T1,T10,T14
AutoFirstAckWait->Error	188	Covered	T143,T144,T145
AutoFirstAckWait->Idle	211	Covered	T1,T21,T146
AutoFirstAckWait->RejectCsrngEntropy	188	Covered	T11,T113,T147
AutoLoadIns->AutoFirstAckWait	119	Covered	T1,T10,T11
AutoLoadIns->Error	188	Covered	T7,T58,T148
AutoLoadIns->Idle	211	Covered	T16,T97,T93
AutoLoadIns->RejectCsrngEntropy	188	Covered	T149,T150,T151
AutoSendGenCmd->AutoAckWait	156	Covered	T1,T10,T14
AutoSendGenCmd->Error	188	Covered	T152,T153,T154
AutoSendGenCmd->Idle	211	Covered	T155
AutoSendGenCmd->RejectCsrngEntropy	188	Covered	T74,T115,T156
AutoSendReseedCmd->AutoAckWait	168	Covered	T1,T10,T14
AutoSendReseedCmd->Error	188	Covered	T157,T158
AutoSendReseedCmd->Idle	211	Covered	T159,T160,T161
AutoSendReseedCmd->RejectCsrngEntropy	188	Covered	T78,T79,T50
BootDone->BootLoadUni	102	Covered	T26,T48,T31
BootDone->Error	188	Covered	T5,T57,T162
BootDone->Idle	211	Covered	T23,T86,T81
BootDone->RejectCsrngEntropy	188	Covered	T163,T164,T165
BootGenAckWait->BootPulse	94	Covered	T23,T5,T25
BootGenAckWait->Error	188	Covered	T166,T167
BootGenAckWait->Idle	211	Covered	T25,T6,T63
BootGenAckWait->RejectCsrngEntropy	188	Covered	T32,T117,T168
BootInsAckWait->BootLoadGen	85	Covered	T23,T5,T25
BootInsAckWait->Error	188	Not Covered
BootInsAckWait->Idle	211	Covered	T5,T54,T55
BootInsAckWait->RejectCsrngEntropy	188	Covered	T43,T169,T170
BootLoadGen->BootGenAckWait	90	Covered	T23,T5,T25
BootLoadGen->Error	188	Covered	T171,T172,T173
BootLoadGen->Idle	211	Covered	T174,T175,T176
BootLoadGen->RejectCsrngEntropy	188	Covered	T16,T97,T177
BootLoadIns->BootInsAckWait	80	Covered	T23,T5,T25
BootLoadIns->Error	188	Covered	T54,T55,T178
BootLoadIns->Idle	211	Covered	T179,T180,T181
BootLoadIns->RejectCsrngEntropy	188	Covered	T182,T183,T184
BootLoadUni->BootUniAckWait	107	Covered	T26,T48,T31
BootLoadUni->Error	188	Covered	T185,T186,T187
BootLoadUni->Idle	211	Not Covered
BootLoadUni->RejectCsrngEntropy	188	Covered	T31,T76,T72
BootPulse->BootDone	98	Covered	T23,T5,T25
BootPulse->Error	188	Covered	T6,T188,T189
BootPulse->Idle	211	Covered	T77,T190,T88
BootPulse->RejectCsrngEntropy	188	Covered	T191,T192,T193
BootUniAckWait->Error	188	Covered	T194,T195,T196
BootUniAckWait->Idle	112	Covered	T26,T48,T31
BootUniAckWait->RejectCsrngEntropy	188	Covered	T93,T197,T198
Idle->AutoLoadIns	69	Covered	T1,T16,T10
Idle->BootLoadIns	65	Covered	T23,T5,T25
Idle->Error	188	Covered	T15,T17,T18
Idle->RejectCsrngEntropy	188	Covered	T16,T31,T11
Idle->SWPortMode	74	Covered	T2,T3,T24
RejectCsrngEntropy->Error	188	Covered	T199,T200,T201
RejectCsrngEntropy->Idle	211	Covered	T16,T31,T32
SWPortMode->Error	188	Covered	T4,T15,T69
SWPortMode->Idle	211	Covered	T32,T11,T76
SWPortMode->RejectCsrngEntropy	188	Covered	T32,T97,T93

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		42	41	97.62
IF	42	2	2	100.00
CASE	62	35	35	100.00
IF	186	5	4	80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	42	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	62	case (state_q)
-2-:	64	if ((boot_req_mode_i && edn_enable_i))
-3-:	66	if ((auto_req_mode_i && edn_enable_i))
-4-:	70	if (edn_enable_i)
-5-:	84	if (csrng_cmd_ack_i)
-6-:	93	if (csrng_cmd_ack_i)
-7-:	101	if ((!boot_req_mode_i))
-8-:	110	if (csrng_cmd_ack_i)
-9-:	118	if (sw_cmd_req_load_i)
-10-:	124	if (csrng_cmd_ack_i)
-11-:	130	if (csrng_cmd_ack_i)
-12-:	136	if ((!auto_req_mode_i))
-13-:	140	if (max_reqs_cnt_zero_i)
-14-:	155	if (cmd_sent_i)
-15-:	167	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T23,T5,T25
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T16,T10
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T24
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T23,T5,T25
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T23,T5,T25
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T23,T5,T25
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T23,T5,T25
BootGenAckWait	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T23,T5,T25
BootGenAckWait	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T23,T5,T25
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T23,T5,T25
BootDone	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T26,T48,T31
BootDone	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T23,T5,T25
BootLoadUni	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T26,T48,T31
BootUniAckWait	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T26,T48,T75
BootUniAckWait	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T26,T48,T31
AutoLoadIns	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T1,T10,T11
AutoLoadIns	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T1,T16,T10
AutoFirstAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T1,T10,T11
AutoFirstAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T10,T11
AutoAckWait	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T1,T10,T14
AutoAckWait	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T1,T10,T14
AutoDispatch	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T10,T14,T22
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T1,T10,T14
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T1,T10,T14
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T10,T14
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T10,T14
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T1,T10,T14
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T10,T14
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T10,T14
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T10,T14
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T24
RejectCsrngEntropy	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T16,T31,T32
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T15,T63,T53

	LineNo.	Expression
-1-:	186	if ((local_escalate_i || csrng_ack_err_i))
-2-:	188	(local_escalate_i) ? 
-3-:	188	((state_q == Error)) ? 
-4-:	201	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy})))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T4,T5,T6
1	0	1	-	Not Covered
1	0	0	-	Covered	T16,T31,T32
0	-	-	1	Covered	T1,T23,T5
0	-	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	206319264	138929	0	0
FpvSecCmErrorStEscalate_A	206319264	139970	0	0
u_state_regs_A	206283299	206100810	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	138929	0	0
T4	2007	1068	0	0
T5	2987	1163	0	0
T6	0	655	0	0
T10	3142	0	0	0
T15	0	13778	0	0
T16	2148	0	0	0
T25	1072	0	0	0
T26	2260	0	0	0
T27	3789	0	0	0
T46	1546	0	0	0
T48	3349	0	0	0
T51	1464	0	0	0
T53	0	178	0	0
T54	0	402	0	0
T55	0	1135	0	0
T63	0	257	0	0
T69	0	275	0	0
T70	0	598	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	139970	0	0
T4	2007	1069	0	0
T5	2987	1164	0	0
T6	0	656	0	0
T10	3142	0	0	0
T15	0	14038	0	0
T16	2148	0	0	0
T25	1072	0	0	0
T26	2260	0	0	0
T27	3789	0	0	0
T46	1546	0	0	0
T48	3349	0	0	0
T51	1464	0	0	0
T53	0	179	0	0
T54	0	403	0	0
T55	0	1136	0	0
T63	0	258	0	0
T69	0	276	0	0
T70	0	599	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206283299	206100810	0	0
T1	1718	1645	0	0
T2	3069	2990	0	0
T3	1430	1364	0	0
T4	1895	1753	0	0
T5	1792	1615	0	0
T23	825	755	0	0
T24	2255	2170	0	0
T25	1072	1015	0	0
T26	2260	2190	0	0
T27	3789	3720	0	0