Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T23,T5

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T2,T3,T23
DataWait	75	Covered	T2,T3,T23
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T5,T6
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T77,T190,T88
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T2,T3,T23
DataWait->AckPls	80	Covered	T2,T3,T23
DataWait->Disabled	107	Covered	T25,T202,T155
DataWait->Error	99	Covered	T6,T63,T56
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T15,T17,T18
EndPointClear->Disabled	107	Covered	T20,T203,T204
EndPointClear->Error	99	Covered	T15,T54,T55
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T2,T3,T23
Idle->Disabled	107	Covered	T1,T23,T5
Idle->Error	99	Covered	T4,T5,T6

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T2,T3,T23
Idle	-	1	0	-	Covered	T2,T3,T23
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T2,T3,T23
DataWait	-	-	-	0	Covered	T2,T3,T23
AckPls	-	-	-	-	Covered	T2,T3,T23
Error	-	-	-	-	Covered	T4,T5,T6
default	-	-	-	-	Covered	T4,T15,T69

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T1,T23,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	1444234848	985553	0	0
FpvSecCmErrorStEscalate_A	1444234848	992840	0	0
u_state_regs_A	1444198883	1442921460	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1444234848	985553	0	0
T4	14049	7426	0	0
T5	20909	8141	0	0
T6	0	4585	0	0
T10	21994	0	0	0
T15	0	96446	0	0
T16	15036	0	0	0
T25	7504	0	0	0
T26	15820	0	0	0
T27	26523	0	0	0
T46	10822	0	0	0
T48	23443	0	0	0
T51	10248	0	0	0
T53	0	1596	0	0
T54	0	2814	0	0
T55	0	7945	0	0
T63	0	2149	0	0
T69	0	1875	0	0
T70	0	4136	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1444234848	992840	0	0
T4	14049	7433	0	0
T5	20909	8148	0	0
T6	0	4592	0	0
T10	21994	0	0	0
T15	0	98266	0	0
T16	15036	0	0	0
T25	7504	0	0	0
T26	15820	0	0	0
T27	26523	0	0	0
T46	10822	0	0	0
T48	23443	0	0	0
T51	10248	0	0	0
T53	0	1603	0	0
T54	0	2821	0	0
T55	0	7952	0	0
T63	0	2156	0	0
T69	0	1882	0	0
T70	0	4143	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1444198883	1442921460	0	0
T1	12026	11515	0	0
T2	21483	20930	0	0
T3	10010	9548	0	0
T4	13937	12943	0	0
T5	19714	18475	0	0
T23	5775	5285	0	0
T24	15785	15190	0	0
T25	7504	7105	0	0
T26	15820	15330	0	0
T27	26523	26040	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T23,T5

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T2,T25,T26
DataWait	75	Covered	T2,T25,T26
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T5,T6
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T2,T25,T26
DataWait->AckPls	80	Covered	T2,T25,T26
DataWait->Disabled	107	Covered	T25,T205
DataWait->Error	99	Covered	T206,T199,T207
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T15,T17,T18
EndPointClear->Disabled	107	Covered	T20,T203,T204
EndPointClear->Error	99	Covered	T15,T54,T55
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T2,T25,T26
Idle->Disabled	107	Covered	T1,T23,T5
Idle->Error	99	Covered	T4,T5,T6

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T2,T25,T26
Idle	-	1	0	-	Covered	T2,T25,T26
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T2,T25,T26
DataWait	-	-	-	0	Covered	T2,T25,T26
AckPls	-	-	-	-	Covered	T2,T25,T26
Error	-	-	-	-	Covered	T4,T5,T6
default	-	-	-	-	Covered	T15,T17,T18

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T1,T23,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	206319264	141129	0	0
FpvSecCmErrorStEscalate_A	206319264	142170	0	0
u_state_regs_A	206319264	206136775	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	141129	0	0
T4	2007	1068	0	0
T5	2987	1163	0	0
T6	0	655	0	0
T10	3142	0	0	0
T15	0	13778	0	0
T16	2148	0	0	0
T25	1072	0	0	0
T26	2260	0	0	0
T27	3789	0	0	0
T46	1546	0	0	0
T48	3349	0	0	0
T51	1464	0	0	0
T53	0	228	0	0
T54	0	402	0	0
T55	0	1135	0	0
T63	0	307	0	0
T69	0	275	0	0
T70	0	598	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	142170	0	0
T4	2007	1069	0	0
T5	2987	1164	0	0
T6	0	656	0	0
T10	3142	0	0	0
T15	0	14038	0	0
T16	2148	0	0	0
T25	1072	0	0	0
T26	2260	0	0	0
T27	3789	0	0	0
T46	1546	0	0	0
T48	3349	0	0	0
T51	1464	0	0	0
T53	0	229	0	0
T54	0	403	0	0
T55	0	1136	0	0
T63	0	308	0	0
T69	0	276	0	0
T70	0	599	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	206136775	0	0
T1	1718	1645	0	0
T2	3069	2990	0	0
T3	1430	1364	0	0
T4	2007	1865	0	0
T5	2987	2810	0	0
T23	825	755	0	0
T24	2255	2170	0	0
T25	1072	1015	0	0
T26	2260	2190	0	0
T27	3789	3720	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T23,T5

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T3,T23,T26
DataWait	75	Covered	T3,T23,T26
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T5,T6
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T208
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T3,T23,T26
DataWait->AckPls	80	Covered	T3,T23,T26
DataWait->Disabled	107	Covered	T202,T209,T174
DataWait->Error	99	Covered	T6,T63,T56
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T15,T17,T18
EndPointClear->Disabled	107	Covered	T20,T203,T204
EndPointClear->Error	99	Covered	T15,T54,T55
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T3,T23,T26
Idle->Disabled	107	Covered	T1,T23,T5
Idle->Error	99	Covered	T5,T53,T57

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T3,T23,T26
Idle	-	1	0	-	Covered	T3,T23,T26
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T3,T23,T26
DataWait	-	-	-	0	Covered	T3,T23,T26
AckPls	-	-	-	-	Covered	T3,T23,T26
Error	-	-	-	-	Covered	T4,T5,T6
default	-	-	-	-	Covered	T4,T15,T69

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T1,T23,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	206319264	138779	0	0
FpvSecCmErrorStEscalate_A	206319264	139820	0	0
u_state_regs_A	206283299	206100810	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	138779	0	0
T4	2007	1018	0	0
T5	2987	1163	0	0
T6	0	655	0	0
T10	3142	0	0	0
T15	0	13778	0	0
T16	2148	0	0	0
T25	1072	0	0	0
T26	2260	0	0	0
T27	3789	0	0	0
T46	1546	0	0	0
T48	3349	0	0	0
T51	1464	0	0	0
T53	0	228	0	0
T54	0	402	0	0
T55	0	1135	0	0
T63	0	307	0	0
T69	0	225	0	0
T70	0	548	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	139820	0	0
T4	2007	1019	0	0
T5	2987	1164	0	0
T6	0	656	0	0
T10	3142	0	0	0
T15	0	14038	0	0
T16	2148	0	0	0
T25	1072	0	0	0
T26	2260	0	0	0
T27	3789	0	0	0
T46	1546	0	0	0
T48	3349	0	0	0
T51	1464	0	0	0
T53	0	229	0	0
T54	0	403	0	0
T55	0	1136	0	0
T63	0	308	0	0
T69	0	226	0	0
T70	0	549	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206283299	206100810	0	0
T1	1718	1645	0	0
T2	3069	2990	0	0
T3	1430	1364	0	0
T4	1895	1753	0	0
T5	1792	1615	0	0
T23	825	755	0	0
T24	2255	2170	0	0
T25	1072	1015	0	0
T26	2260	2190	0	0
T27	3789	3720	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T23,T5

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T2,T26,T10
DataWait	75	Covered	T2,T26,T10
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T5,T6
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T210,T211,T212
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T2,T26,T10
DataWait->AckPls	80	Covered	T2,T26,T10
DataWait->Disabled	107	Covered	T155,T176,T213
DataWait->Error	99	Covered	T57,T148,T143
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T15,T17,T18
EndPointClear->Disabled	107	Covered	T20,T203,T204
EndPointClear->Error	99	Covered	T15,T54,T55
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T2,T26,T10
Idle->Disabled	107	Covered	T1,T23,T5
Idle->Error	99	Covered	T4,T5,T6

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T2,T26,T10
Idle	-	1	0	-	Covered	T2,T26,T10
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T2,T26,T10
DataWait	-	-	-	0	Covered	T2,T26,T10
AckPls	-	-	-	-	Covered	T2,T26,T10
Error	-	-	-	-	Covered	T4,T5,T6
default	-	-	-	-	Covered	T15,T17,T18

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T1,T23,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	206319264	141129	0	0
FpvSecCmErrorStEscalate_A	206319264	142170	0	0
u_state_regs_A	206319264	206136775	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	141129	0	0
T4	2007	1068	0	0
T5	2987	1163	0	0
T6	0	655	0	0
T10	3142	0	0	0
T15	0	13778	0	0
T16	2148	0	0	0
T25	1072	0	0	0
T26	2260	0	0	0
T27	3789	0	0	0
T46	1546	0	0	0
T48	3349	0	0	0
T51	1464	0	0	0
T53	0	228	0	0
T54	0	402	0	0
T55	0	1135	0	0
T63	0	307	0	0
T69	0	275	0	0
T70	0	598	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	142170	0	0
T4	2007	1069	0	0
T5	2987	1164	0	0
T6	0	656	0	0
T10	3142	0	0	0
T15	0	14038	0	0
T16	2148	0	0	0
T25	1072	0	0	0
T26	2260	0	0	0
T27	3789	0	0	0
T46	1546	0	0	0
T48	3349	0	0	0
T51	1464	0	0	0
T53	0	229	0	0
T54	0	403	0	0
T55	0	1136	0	0
T63	0	308	0	0
T69	0	276	0	0
T70	0	599	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	206136775	0	0
T1	1718	1645	0	0
T2	3069	2990	0	0
T3	1430	1364	0	0
T4	2007	1865	0	0
T5	2987	2810	0	0
T23	825	755	0	0
T24	2255	2170	0	0
T25	1072	1015	0	0
T26	2260	2190	0	0
T27	3789	3720	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T23,T5

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T2,T24
DataWait	75	Covered	T1,T2,T24
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T5,T6
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T77,T190,T214
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T2,T24
DataWait->AckPls	80	Covered	T1,T2,T24
DataWait->Disabled	107	Covered	T215,T216
DataWait->Error	99	Covered	T217,T218,T219
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T15,T17,T18
EndPointClear->Disabled	107	Covered	T20,T203,T204
EndPointClear->Error	99	Covered	T15,T54,T55
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T2,T24
Idle->Disabled	107	Covered	T1,T23,T5
Idle->Error	99	Covered	T4,T5,T6

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T2,T24
Idle	-	1	0	-	Covered	T1,T2,T24
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T2,T24
DataWait	-	-	-	0	Covered	T1,T2,T24
AckPls	-	-	-	-	Covered	T1,T2,T24
Error	-	-	-	-	Covered	T4,T5,T6
default	-	-	-	-	Covered	T15,T17,T18

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T1,T23,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	206319264	141129	0	0
FpvSecCmErrorStEscalate_A	206319264	142170	0	0
u_state_regs_A	206319264	206136775	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	141129	0	0
T4	2007	1068	0	0
T5	2987	1163	0	0
T6	0	655	0	0
T10	3142	0	0	0
T15	0	13778	0	0
T16	2148	0	0	0
T25	1072	0	0	0
T26	2260	0	0	0
T27	3789	0	0	0
T46	1546	0	0	0
T48	3349	0	0	0
T51	1464	0	0	0
T53	0	228	0	0
T54	0	402	0	0
T55	0	1135	0	0
T63	0	307	0	0
T69	0	275	0	0
T70	0	598	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	142170	0	0
T4	2007	1069	0	0
T5	2987	1164	0	0
T6	0	656	0	0
T10	3142	0	0	0
T15	0	14038	0	0
T16	2148	0	0	0
T25	1072	0	0	0
T26	2260	0	0	0
T27	3789	0	0	0
T46	1546	0	0	0
T48	3349	0	0	0
T51	1464	0	0	0
T53	0	229	0	0
T54	0	403	0	0
T55	0	1136	0	0
T63	0	308	0	0
T69	0	276	0	0
T70	0	599	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	206136775	0	0
T1	1718	1645	0	0
T2	3069	2990	0	0
T3	1430	1364	0	0
T4	2007	1865	0	0
T5	2987	2810	0	0
T23	825	755	0	0
T24	2255	2170	0	0
T25	1072	1015	0	0
T26	2260	2190	0	0
T27	3789	3720	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T23,T5

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T26,T42,T43
DataWait	75	Covered	T26,T42,T43
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T5,T6
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T220
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T26,T42,T43
DataWait->AckPls	80	Covered	T26,T42,T43
DataWait->Disabled	107	Covered	T221
DataWait->Error	99	Covered	T222,T187,T126
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T15,T17,T18
EndPointClear->Disabled	107	Covered	T20,T203,T204
EndPointClear->Error	99	Covered	T15,T54,T55
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T26,T42,T43
Idle->Disabled	107	Covered	T1,T23,T5
Idle->Error	99	Covered	T4,T5,T6

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T26,T42,T43
Idle	-	1	0	-	Covered	T26,T42,T43
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T26,T42,T43
DataWait	-	-	-	0	Covered	T26,T42,T43
AckPls	-	-	-	-	Covered	T26,T42,T43
Error	-	-	-	-	Covered	T4,T5,T6
default	-	-	-	-	Covered	T15,T17,T18

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T1,T23,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	206319264	141129	0	0
FpvSecCmErrorStEscalate_A	206319264	142170	0	0
u_state_regs_A	206319264	206136775	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	141129	0	0
T4	2007	1068	0	0
T5	2987	1163	0	0
T6	0	655	0	0
T10	3142	0	0	0
T15	0	13778	0	0
T16	2148	0	0	0
T25	1072	0	0	0
T26	2260	0	0	0
T27	3789	0	0	0
T46	1546	0	0	0
T48	3349	0	0	0
T51	1464	0	0	0
T53	0	228	0	0
T54	0	402	0	0
T55	0	1135	0	0
T63	0	307	0	0
T69	0	275	0	0
T70	0	598	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	142170	0	0
T4	2007	1069	0	0
T5	2987	1164	0	0
T6	0	656	0	0
T10	3142	0	0	0
T15	0	14038	0	0
T16	2148	0	0	0
T25	1072	0	0	0
T26	2260	0	0	0
T27	3789	0	0	0
T46	1546	0	0	0
T48	3349	0	0	0
T51	1464	0	0	0
T53	0	229	0	0
T54	0	403	0	0
T55	0	1136	0	0
T63	0	308	0	0
T69	0	276	0	0
T70	0	599	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	206136775	0	0
T1	1718	1645	0	0
T2	3069	2990	0	0
T3	1430	1364	0	0
T4	2007	1865	0	0
T5	2987	2810	0	0
T23	825	755	0	0
T24	2255	2170	0	0
T25	1072	1015	0	0
T26	2260	2190	0	0
T27	3789	3720	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T23,T5

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T2,T26,T48
DataWait	75	Covered	T2,T5,T26
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T5,T6
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T88
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T2,T26,T48
DataWait->AckPls	80	Covered	T2,T26,T48
DataWait->Disabled	107	Covered	T128,T223,T175
DataWait->Error	99	Covered	T5,T188,T194
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T15,T17,T18
EndPointClear->Disabled	107	Covered	T20,T203,T204
EndPointClear->Error	99	Covered	T15,T54,T55
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T2,T5,T26
Idle->Disabled	107	Covered	T1,T23,T5
Idle->Error	99	Covered	T4,T6,T63

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T2,T26,T48
Idle	-	1	0	-	Covered	T2,T5,T26
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T2,T26,T48
DataWait	-	-	-	0	Covered	T2,T5,T26
AckPls	-	-	-	-	Covered	T2,T26,T48
Error	-	-	-	-	Covered	T4,T5,T6
default	-	-	-	-	Covered	T15,T17,T18

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T1,T23,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	206319264	141129	0	0
FpvSecCmErrorStEscalate_A	206319264	142170	0	0
u_state_regs_A	206319264	206136775	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	141129	0	0
T4	2007	1068	0	0
T5	2987	1163	0	0
T6	0	655	0	0
T10	3142	0	0	0
T15	0	13778	0	0
T16	2148	0	0	0
T25	1072	0	0	0
T26	2260	0	0	0
T27	3789	0	0	0
T46	1546	0	0	0
T48	3349	0	0	0
T51	1464	0	0	0
T53	0	228	0	0
T54	0	402	0	0
T55	0	1135	0	0
T63	0	307	0	0
T69	0	275	0	0
T70	0	598	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	142170	0	0
T4	2007	1069	0	0
T5	2987	1164	0	0
T6	0	656	0	0
T10	3142	0	0	0
T15	0	14038	0	0
T16	2148	0	0	0
T25	1072	0	0	0
T26	2260	0	0	0
T27	3789	0	0	0
T46	1546	0	0	0
T48	3349	0	0	0
T51	1464	0	0	0
T53	0	229	0	0
T54	0	403	0	0
T55	0	1136	0	0
T63	0	308	0	0
T69	0	276	0	0
T70	0	599	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	206136775	0	0
T1	1718	1645	0	0
T2	3069	2990	0	0
T3	1430	1364	0	0
T4	2007	1865	0	0
T5	2987	2810	0	0
T23	825	755	0	0
T24	2255	2170	0	0
T25	1072	1015	0	0
T26	2260	2190	0	0
T27	3789	3720	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T23,T5

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T44,T12,T45
DataWait	75	Covered	T44,T12,T45
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T5,T6
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T224
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T44,T12,T45
DataWait->AckPls	80	Covered	T44,T12,T45
DataWait->Disabled	107	Covered	T91,T225,T226
DataWait->Error	99	Covered	T167,T227
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T15,T17,T18
EndPointClear->Disabled	107	Covered	T20,T203,T204
EndPointClear->Error	99	Covered	T15,T54,T55
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T44,T12,T45
Idle->Disabled	107	Covered	T1,T23,T5
Idle->Error	99	Covered	T4,T5,T6

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T44,T12,T45
Idle	-	1	0	-	Covered	T44,T12,T45
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T44,T12,T45
DataWait	-	-	-	0	Covered	T44,T12,T45
AckPls	-	-	-	-	Covered	T44,T12,T45
Error	-	-	-	-	Covered	T4,T5,T6
default	-	-	-	-	Covered	T15,T17,T18

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T1,T23,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	206319264	141129	0	0
FpvSecCmErrorStEscalate_A	206319264	142170	0	0
u_state_regs_A	206319264	206136775	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	141129	0	0
T4	2007	1068	0	0
T5	2987	1163	0	0
T6	0	655	0	0
T10	3142	0	0	0
T15	0	13778	0	0
T16	2148	0	0	0
T25	1072	0	0	0
T26	2260	0	0	0
T27	3789	0	0	0
T46	1546	0	0	0
T48	3349	0	0	0
T51	1464	0	0	0
T53	0	228	0	0
T54	0	402	0	0
T55	0	1135	0	0
T63	0	307	0	0
T69	0	275	0	0
T70	0	598	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	142170	0	0
T4	2007	1069	0	0
T5	2987	1164	0	0
T6	0	656	0	0
T10	3142	0	0	0
T15	0	14038	0	0
T16	2148	0	0	0
T25	1072	0	0	0
T26	2260	0	0	0
T27	3789	0	0	0
T46	1546	0	0	0
T48	3349	0	0	0
T51	1464	0	0	0
T53	0	229	0	0
T54	0	403	0	0
T55	0	1136	0	0
T63	0	308	0	0
T69	0	276	0	0
T70	0	599	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	206136775	0	0
T1	1718	1645	0	0
T2	3069	2990	0	0
T3	1430	1364	0	0
T4	2007	1865	0	0
T5	2987	2810	0	0
T23	825	755	0	0
T24	2255	2170	0	0
T25	1072	1015	0	0
T26	2260	2190	0	0
T27	3789	3720	0	0