Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T16,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T5,T16

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T33,T34,T96
1	1	0	Not Covered
1	1	1	Covered	T1,T5,T16

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T36,T37,T38
1	0	1	Covered	T1,T5,T16
1	1	0	Not Covered
1	1	1	Covered	T1,T10,T14

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T16
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	411961982	1095982	0	0
DepthKnown_A	412638528	412273550	0	0
RvalidKnown_A	412638528	412273550	0	0
WreadyKnown_A	412638528	412273550	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	412307990	1183221	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411961982	1095982	0	0
T1	3436	1898	0	0
T2	6138	0	0	0
T3	2860	0	0	0
T4	728	0	0	0
T5	246	0	0	0
T10	0	2187	0	0
T11	0	380	0	0
T14	0	1755	0	0
T16	0	57	0	0
T19	0	965	0	0
T22	0	2844	0	0
T23	1650	0	0	0
T24	4510	0	0	0
T25	2144	0	0	0
T26	4520	0	0	0
T27	7578	0	0	0
T32	0	197	0	0
T76	0	137	0	0
T97	0	547	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412638528	412273550	0	0
T1	3436	3290	0	0
T2	6138	5980	0	0
T3	2860	2728	0	0
T4	4014	3730	0	0
T5	5974	5620	0	0
T23	1650	1510	0	0
T24	4510	4340	0	0
T25	2144	2030	0	0
T26	4520	4380	0	0
T27	7578	7440	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412638528	412273550	0	0
T1	3436	3290	0	0
T2	6138	5980	0	0
T3	2860	2728	0	0
T4	4014	3730	0	0
T5	5974	5620	0	0
T23	1650	1510	0	0
T24	4510	4340	0	0
T25	2144	2030	0	0
T26	4520	4380	0	0
T27	7578	7440	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412638528	412273550	0	0
T1	3436	3290	0	0
T2	6138	5980	0	0
T3	2860	2728	0	0
T4	4014	3730	0	0
T5	5974	5620	0	0
T23	1650	1510	0	0
T24	4510	4340	0	0
T25	2144	2030	0	0
T26	4520	4380	0	0
T27	7578	7440	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	412307990	1183221	0	0
T1	3436	1898	0	0
T2	6138	0	0	0
T3	2860	0	0	0
T4	4014	0	0	0
T5	5974	2282	0	0
T6	0	397	0	0
T10	0	2187	0	0
T11	0	380	0	0
T14	0	1755	0	0
T16	0	57	0	0
T23	1650	0	0	0
T24	4510	0	0	0
T25	2144	0	0	0
T26	4520	0	0	0
T27	7578	0	0	0
T32	0	197	0	0
T76	0	137	0	0
T97	0	547	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T33,T8,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T5,T16

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T33
1	1	0	Not Covered
1	1	1	Covered	T1,T5,T16

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T38
1	0	1	Covered	T1,T5,T16
1	1	0	Not Covered
1	1	1	Covered	T1,T10,T14

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T16
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	205980991	541154	0	0
DepthKnown_A	206319264	206136775	0	0
RvalidKnown_A	206319264	206136775	0	0
WreadyKnown_A	206319264	206136775	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	206153995	584631	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	205980991	541154	0	0
T1	1718	932	0	0
T2	3069	0	0	0
T3	1430	0	0	0
T4	364	0	0	0
T5	123	0	0	0
T10	0	1018	0	0
T11	0	191	0	0
T14	0	838	0	0
T16	0	17	0	0
T19	0	477	0	0
T22	0	1379	0	0
T23	825	0	0	0
T24	2255	0	0	0
T25	1072	0	0	0
T26	2260	0	0	0
T27	3789	0	0	0
T32	0	82	0	0
T76	0	32	0	0
T97	0	219	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	206136775	0	0
T1	1718	1645	0	0
T2	3069	2990	0	0
T3	1430	1364	0	0
T4	2007	1865	0	0
T5	2987	2810	0	0
T23	825	755	0	0
T24	2255	2170	0	0
T25	1072	1015	0	0
T26	2260	2190	0	0
T27	3789	3720	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	206136775	0	0
T1	1718	1645	0	0
T2	3069	2990	0	0
T3	1430	1364	0	0
T4	2007	1865	0	0
T5	2987	2810	0	0
T23	825	755	0	0
T24	2255	2170	0	0
T25	1072	1015	0	0
T26	2260	2190	0	0
T27	3789	3720	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	206136775	0	0
T1	1718	1645	0	0
T2	3069	2990	0	0
T3	1430	1364	0	0
T4	2007	1865	0	0
T5	2987	2810	0	0
T23	825	755	0	0
T24	2255	2170	0	0
T25	1072	1015	0	0
T26	2260	2190	0	0
T27	3789	3720	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	206153995	584631	0	0
T1	1718	932	0	0
T2	3069	0	0	0
T3	1430	0	0	0
T4	2007	0	0	0
T5	2987	1143	0	0
T6	0	204	0	0
T10	0	1018	0	0
T11	0	191	0	0
T14	0	838	0	0
T16	0	17	0	0
T23	825	0	0	0
T24	2255	0	0	0
T25	1072	0	0	0
T26	2260	0	0	0
T27	3789	0	0	0
T32	0	82	0	0
T76	0	32	0	0
T97	0	219	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T16,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T5,T16

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T34,T96
1	1	0	Not Covered
1	1	1	Covered	T1,T5,T16

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T36,T37,T98
1	0	1	Covered	T1,T5,T16
1	1	0	Not Covered
1	1	1	Covered	T1,T10,T14

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T16
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	205980991	554828	0	0
DepthKnown_A	206319264	206136775	0	0
RvalidKnown_A	206319264	206136775	0	0
WreadyKnown_A	206319264	206136775	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	206153995	598590	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	205980991	554828	0	0
T1	1718	966	0	0
T2	3069	0	0	0
T3	1430	0	0	0
T4	364	0	0	0
T5	123	0	0	0
T10	0	1169	0	0
T11	0	189	0	0
T14	0	917	0	0
T16	0	40	0	0
T19	0	488	0	0
T22	0	1465	0	0
T23	825	0	0	0
T24	2255	0	0	0
T25	1072	0	0	0
T26	2260	0	0	0
T27	3789	0	0	0
T32	0	115	0	0
T76	0	105	0	0
T97	0	328	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	206136775	0	0
T1	1718	1645	0	0
T2	3069	2990	0	0
T3	1430	1364	0	0
T4	2007	1865	0	0
T5	2987	2810	0	0
T23	825	755	0	0
T24	2255	2170	0	0
T25	1072	1015	0	0
T26	2260	2190	0	0
T27	3789	3720	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	206136775	0	0
T1	1718	1645	0	0
T2	3069	2990	0	0
T3	1430	1364	0	0
T4	2007	1865	0	0
T5	2987	2810	0	0
T23	825	755	0	0
T24	2255	2170	0	0
T25	1072	1015	0	0
T26	2260	2190	0	0
T27	3789	3720	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206319264	206136775	0	0
T1	1718	1645	0	0
T2	3069	2990	0	0
T3	1430	1364	0	0
T4	2007	1865	0	0
T5	2987	2810	0	0
T23	825	755	0	0
T24	2255	2170	0	0
T25	1072	1015	0	0
T26	2260	2190	0	0
T27	3789	3720	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	206153995	598590	0	0
T1	1718	966	0	0
T2	3069	0	0	0
T3	1430	0	0	0
T4	2007	0	0	0
T5	2987	1139	0	0
T6	0	193	0	0
T10	0	1169	0	0
T11	0	189	0	0
T14	0	917	0	0
T16	0	40	0	0
T23	825	0	0	0
T24	2255	0	0	0
T25	1072	0	0	0
T26	2260	0	0	0
T27	3789	0	0	0
T32	0	115	0	0
T76	0	105	0	0
T97	0	328	0	0