Summary for Variable cp_acmd
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
5 |
0 |
5 |
100.00 |
Automatically Generated Bins for cp_acmd
Excluded/Illegal bins
NAME | COUNT | STATUS |
auto[INV] |
0 |
Excluded |
auto[GENB] |
0 |
Excluded |
auto[GENU] |
0 |
Excluded |
unused |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[INS] |
4509 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
2 |
auto[RES] |
1109 |
1 |
|
|
T2 |
1 |
|
T4 |
1 |
|
T10 |
1 |
auto[GEN] |
4584 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
4 |
auto[UPD] |
537 |
1 |
|
|
T1 |
1 |
|
T21 |
1 |
|
T5 |
1 |
auto[UNI] |
3708 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T10 |
2 |
Summary for Variable cp_clen
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_clen
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
some_cmd_data |
4593 |
1 |
|
|
T1 |
3 |
|
T2 |
2 |
|
T10 |
4 |
no_cmd_data |
9861 |
1 |
|
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
6 |
Summary for Variable cp_cmd_src
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
5 |
0 |
5 |
100.00 |
User Defined Bins for cp_cmd_src
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
sw_cmd_req |
12623 |
1 |
|
|
T1 |
4 |
|
T2 |
4 |
|
T3 |
3 |
reseed_cmd |
561 |
1 |
|
|
T4 |
1 |
|
T10 |
1 |
|
T11 |
1 |
generate_cmd |
523 |
1 |
|
|
T4 |
1 |
|
T10 |
1 |
|
T11 |
1 |
boot_gen_cmd |
426 |
1 |
|
|
T3 |
2 |
|
T4 |
2 |
|
T21 |
1 |
boot_ins_cmd |
321 |
1 |
|
|
T3 |
1 |
|
T4 |
2 |
|
T21 |
1 |
Summary for Variable cp_flags
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_flags
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
true |
4827 |
1 |
|
|
T1 |
2 |
|
T2 |
1 |
|
T3 |
3 |
false |
9627 |
1 |
|
|
T1 |
2 |
|
T2 |
3 |
|
T3 |
3 |
Summary for Variable cp_glen
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_glen
Excluded/Illegal bins
NAME | COUNT | STATUS |
zero |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
multiple |
1437 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T3 |
1 |
one |
2702 |
1 |
|
|
T3 |
3 |
|
T4 |
2 |
|
T10 |
2 |
Summary for Variable cp_mode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_mode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
sw_mode |
11663 |
1 |
|
|
T1 |
4 |
|
T2 |
4 |
|
T10 |
2 |
boot_mode |
831 |
1 |
|
|
T3 |
3 |
|
T4 |
6 |
|
T21 |
2 |
auto_mode |
1960 |
1 |
|
|
T3 |
3 |
|
T10 |
4 |
|
T11 |
6 |
Summary for Cross cr_generate_intended
Samples crossed: cp_acmd cp_clen cp_glen cp_mode cp_cmd_src
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
9 |
0 |
9 |
100.00 |
|
Automatically Generated Cross Bins |
9 |
0 |
9 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cr_generate_intended
Excluded/Illegal bins
cp_acmd | cp_clen | cp_glen | cp_mode | cp_cmd_src | COUNT | STATUS | |
[auto[INV]] |
[some_cmd_data , no_cmd_data] |
[multiple , one] |
[sw_mode , boot_mode , auto_mode] |
[sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] |
-- |
Excluded |
(60 bins) |
[auto[GENB] , auto[GENU]] |
[some_cmd_data , no_cmd_data] |
[multiple , one] |
[sw_mode , boot_mode , auto_mode] |
[sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] |
-- |
Excluded |
(120 bins) |
Covered bins
cp_acmd | cp_clen | cp_glen | cp_mode | cp_cmd_src | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[GEN] |
some_cmd_data |
multiple |
sw_mode |
sw_cmd_req |
183 |
1 |
|
|
T1 |
1 |
|
T37 |
1 |
|
T13 |
1 |
auto[GEN] |
some_cmd_data |
multiple |
auto_mode |
generate_cmd |
134 |
1 |
|
|
T44 |
1 |
|
T211 |
1 |
|
T43 |
1 |
auto[GEN] |
some_cmd_data |
one |
sw_mode |
sw_cmd_req |
58 |
1 |
|
|
T10 |
1 |
|
T21 |
1 |
|
T55 |
1 |
auto[GEN] |
some_cmd_data |
one |
auto_mode |
generate_cmd |
131 |
1 |
|
|
T10 |
1 |
|
T13 |
1 |
|
T14 |
1 |
auto[GEN] |
no_cmd_data |
multiple |
sw_mode |
sw_cmd_req |
48 |
1 |
|
|
T2 |
1 |
|
T81 |
1 |
|
T330 |
1 |
auto[GEN] |
no_cmd_data |
multiple |
boot_mode |
boot_gen_cmd |
75 |
1 |
|
|
T21 |
1 |
|
T37 |
1 |
|
T234 |
1 |
auto[GEN] |
no_cmd_data |
multiple |
auto_mode |
generate_cmd |
35 |
1 |
|
|
T76 |
1 |
|
T7 |
1 |
|
T260 |
1 |
auto[GEN] |
no_cmd_data |
one |
sw_mode |
sw_cmd_req |
1567 |
1 |
|
|
T5 |
4 |
|
T6 |
7 |
|
T35 |
14 |
auto[GEN] |
no_cmd_data |
one |
auto_mode |
generate_cmd |
161 |
1 |
|
|
T11 |
1 |
|
T12 |
1 |
|
T68 |
1 |
User Defined Cross Bins for cr_generate_intended
Excluded/Illegal bins
NAME | COUNT | STATUS |
not_gen |
0 |
Excluded |
gen_auto_wrong_src |
0 |
Excluded |
gen_boot_wrong_src |
0 |
Excluded |
gen_boot_seq_wrong_clen |
0 |
Excluded |
gen_boot_seq_wrong_glen |
0 |
Excluded |
gen_sw_wrong_src |
0 |
Excluded |
Summary for Cross cr_instantiate_intended
Samples crossed: cp_acmd cp_clen cp_flags cp_mode cp_cmd_src
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
9 |
0 |
9 |
100.00 |
|
Automatically Generated Cross Bins |
9 |
0 |
9 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cr_instantiate_intended
Excluded/Illegal bins
cp_acmd | cp_clen | cp_flags | cp_mode | cp_cmd_src | COUNT | STATUS | |
[auto[INV]] |
[some_cmd_data , no_cmd_data] |
[true , false] |
[sw_mode , boot_mode , auto_mode] |
[sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] |
-- |
Excluded |
(60 bins) |
[auto[GENB] , auto[GENU]] |
[some_cmd_data , no_cmd_data] |
[true , false] |
[sw_mode , boot_mode , auto_mode] |
[sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] |
-- |
Excluded |
(120 bins) |
Covered bins
cp_acmd | cp_clen | cp_flags | cp_mode | cp_cmd_src | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[INS] |
some_cmd_data |
true |
sw_mode |
sw_cmd_req |
857 |
1 |
|
|
T1 |
1 |
|
T21 |
1 |
|
T5 |
1 |
auto[INS] |
some_cmd_data |
true |
auto_mode |
sw_cmd_req |
76 |
1 |
|
|
T20 |
1 |
|
T76 |
1 |
|
T85 |
1 |
auto[INS] |
some_cmd_data |
false |
sw_mode |
sw_cmd_req |
832 |
1 |
|
|
T2 |
1 |
|
T5 |
4 |
|
T37 |
1 |
auto[INS] |
some_cmd_data |
false |
auto_mode |
sw_cmd_req |
97 |
1 |
|
|
T10 |
1 |
|
T13 |
1 |
|
T14 |
2 |
auto[INS] |
no_cmd_data |
true |
sw_mode |
sw_cmd_req |
219 |
1 |
|
|
T36 |
1 |
|
T65 |
2 |
|
T66 |
2 |
auto[INS] |
no_cmd_data |
true |
auto_mode |
sw_cmd_req |
218 |
1 |
|
|
T3 |
1 |
|
T11 |
1 |
|
T12 |
1 |
auto[INS] |
no_cmd_data |
false |
sw_mode |
sw_cmd_req |
1754 |
1 |
|
|
T5 |
4 |
|
T6 |
8 |
|
T35 |
14 |
auto[INS] |
no_cmd_data |
false |
boot_mode |
boot_ins_cmd |
161 |
1 |
|
|
T3 |
1 |
|
T4 |
1 |
|
T21 |
1 |
auto[INS] |
no_cmd_data |
false |
auto_mode |
sw_cmd_req |
135 |
1 |
|
|
T11 |
1 |
|
T12 |
1 |
|
T68 |
1 |
User Defined Cross Bins for cr_instantiate_intended
Excluded/Illegal bins
NAME | COUNT | STATUS |
not_ins |
0 |
Excluded |
ins_auto_wrong_src |
0 |
Excluded |
ins_boot_wrong_src |
0 |
Excluded |
ins_boot_seq_wrong_clen |
0 |
Excluded |
ins_boot_seq_wrong_flag0 |
0 |
Excluded |
ins_sw_wrong_src |
0 |
Excluded |
Summary for Cross cr_reseed_intended
Samples crossed: cp_acmd cp_clen cp_flags cp_mode cp_cmd_src
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cr_reseed_intended
Excluded/Illegal bins
cp_acmd | cp_clen | cp_flags | cp_mode | cp_cmd_src | COUNT | STATUS | |
[auto[INV]] |
[some_cmd_data , no_cmd_data] |
[true , false] |
[sw_mode , boot_mode , auto_mode] |
[sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] |
-- |
Excluded |
(60 bins) |
[auto[GENB] , auto[GENU]] |
[some_cmd_data , no_cmd_data] |
[true , false] |
[sw_mode , boot_mode , auto_mode] |
[sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] |
-- |
Excluded |
(120 bins) |
Covered bins
cp_acmd | cp_clen | cp_flags | cp_mode | cp_cmd_src | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[RES] |
some_cmd_data |
true |
sw_mode |
sw_cmd_req |
217 |
1 |
|
|
T5 |
2 |
|
T23 |
1 |
|
T6 |
2 |
auto[RES] |
some_cmd_data |
true |
auto_mode |
reseed_cmd |
139 |
1 |
|
|
T13 |
1 |
|
T20 |
2 |
|
T85 |
1 |
auto[RES] |
some_cmd_data |
false |
sw_mode |
sw_cmd_req |
204 |
1 |
|
|
T2 |
1 |
|
T55 |
1 |
|
T6 |
1 |
auto[RES] |
some_cmd_data |
false |
auto_mode |
reseed_cmd |
127 |
1 |
|
|
T14 |
1 |
|
T76 |
1 |
|
T108 |
1 |
auto[RES] |
no_cmd_data |
true |
sw_mode |
sw_cmd_req |
60 |
1 |
|
|
T65 |
1 |
|
T98 |
1 |
|
T97 |
2 |
auto[RES] |
no_cmd_data |
true |
auto_mode |
reseed_cmd |
31 |
1 |
|
|
T211 |
1 |
|
T276 |
1 |
|
T63 |
1 |
auto[RES] |
no_cmd_data |
false |
sw_mode |
sw_cmd_req |
52 |
1 |
|
|
T40 |
1 |
|
T65 |
1 |
|
T234 |
1 |
auto[RES] |
no_cmd_data |
false |
auto_mode |
reseed_cmd |
202 |
1 |
|
|
T10 |
1 |
|
T11 |
1 |
|
T12 |
1 |
User Defined Cross Bins for cr_reseed_intended
Excluded/Illegal bins
NAME | COUNT | STATUS |
not_res |
0 |
Excluded |
res_auto_wrong_src |
0 |
Excluded |
res_boot_wrong_src |
0 |
Excluded |
res_sw_wrong_src |
0 |
Excluded |
Summary for Cross cr_update_intended
Samples crossed: cp_acmd cp_clen cp_mode cp_cmd_src
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
2 |
0 |
2 |
100.00 |
|
Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cr_update_intended
Excluded/Illegal bins
cp_acmd | cp_clen | cp_mode | cp_cmd_src | COUNT | STATUS | |
[auto[INV]] |
[some_cmd_data , no_cmd_data] |
[sw_mode , boot_mode , auto_mode] |
[sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] |
-- |
Excluded |
(30 bins) |
[auto[GENB] , auto[GENU]] |
[some_cmd_data , no_cmd_data] |
[sw_mode , boot_mode , auto_mode] |
[sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] |
-- |
Excluded |
(60 bins) |
Covered bins
cp_acmd | cp_clen | cp_mode | cp_cmd_src | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[UPD] |
some_cmd_data |
sw_mode |
sw_cmd_req |
396 |
1 |
|
|
T1 |
1 |
|
T5 |
1 |
|
T37 |
1 |
auto[UPD] |
no_cmd_data |
sw_mode |
sw_cmd_req |
122 |
1 |
|
|
T21 |
1 |
|
T6 |
1 |
|
T36 |
2 |
User Defined Cross Bins for cr_update_intended
Excluded/Illegal bins
NAME | COUNT | STATUS |
not_upd |
0 |
Excluded |
upd_auto_wrong_src |
0 |
Excluded |
upd_boot_wrong_src |
0 |
Excluded |
upd_sw_wrong_src |
0 |
Excluded |
Summary for Cross cr_uninstantiate_intended
Samples crossed: cp_acmd cp_mode cp_cmd_src
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cr_uninstantiate_intended
Excluded/Illegal bins
cp_acmd | cp_mode | cp_cmd_src | COUNT | STATUS | |
[auto[INV]] |
[sw_mode , boot_mode , auto_mode] |
[sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] |
-- |
Excluded |
(15 bins) |
[auto[GENB] , auto[GENU]] |
[sw_mode , boot_mode , auto_mode] |
[sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] |
-- |
Excluded |
(30 bins) |
Covered bins
cp_acmd | cp_mode | cp_cmd_src | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[UNI] |
sw_mode |
sw_cmd_req |
3691 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T10 |
1 |
User Defined Cross Bins for cr_uninstantiate_intended
Excluded/Illegal bins
NAME | COUNT | STATUS |
not_uni |
0 |
Excluded |
uni_auto_wrong_src |
0 |
Excluded |
uni_boot_wrong_src |
0 |
Excluded |
uni_sw_wrong_src |
0 |
Excluded |
Summary for Cross cr_acmd_mode_cmd_src_unintended
Samples crossed: cp_acmd cp_mode cp_cmd_src
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
5 |
0 |
5 |
100.00 |
|
Automatically Generated Cross Bins |
5 |
0 |
5 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cr_acmd_mode_cmd_src_unintended
Excluded/Illegal bins
cp_acmd | cp_mode | cp_cmd_src | COUNT | STATUS | |
[auto[INV]] |
[sw_mode , boot_mode , auto_mode] |
[sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] |
-- |
Excluded |
(15 bins) |
[auto[GENB] , auto[GENU]] |
[sw_mode , boot_mode , auto_mode] |
[sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] |
-- |
Excluded |
(30 bins) |
Covered bins
cp_acmd | cp_mode | cp_cmd_src | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[INS] |
auto_mode |
sw_cmd_req |
526 |
1 |
|
|
T3 |
1 |
|
T10 |
1 |
|
T11 |
2 |
auto[RES] |
auto_mode |
sw_cmd_req |
15 |
1 |
|
|
T331 |
1 |
|
T260 |
1 |
|
T227 |
1 |
auto[GEN] |
auto_mode |
sw_cmd_req |
416 |
1 |
|
|
T3 |
2 |
|
T11 |
2 |
|
T12 |
2 |
auto[UPD] |
auto_mode |
sw_cmd_req |
19 |
1 |
|
|
T211 |
1 |
|
T332 |
1 |
|
T333 |
1 |
auto[UNI] |
auto_mode |
sw_cmd_req |
17 |
1 |
|
|
T10 |
1 |
|
T76 |
1 |
|
T43 |
1 |
User Defined Cross Bins for cr_acmd_mode_cmd_src_unintended
Excluded/Illegal bins
NAME | COUNT | STATUS |
not_sw_cmd |
0 |
Excluded |
not_auto_mode |
0 |
Excluded |