Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	660894	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5203014

1

T1

28

T2

27

T3

25

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1556527	1			T1	83		T2	101		T3	30
values[0x0]	1992420	1			T1	12		T2	13		T3	16
values[0x1]	2314961	1			T1	15		T2	12		T3	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	329481	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5534427

1

T1

49

T2

59

T3

30

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	23196	1			T4	9		T21	1		T5	1
valid_sources[0x01]	23111	1			T10	2		T13	1		T39	1
valid_sources[0x02]	22928	1			T1	1		T2	1		T5	1
valid_sources[0x03]	23458	1			T12	1		T5	1		T39	3
valid_sources[0x04]	23458	1			T12	1		T13	1		T6	359
valid_sources[0x05]	21529	1			T10	3		T21	1		T11	2
valid_sources[0x06]	23205	1			T22	1		T5	2		T39	6
valid_sources[0x07]	22678	1			T1	4		T12	2		T5	2
valid_sources[0x08]	23737	1			T1	2		T2	3		T6	303
valid_sources[0x09]	23563	1			T5	1		T6	259		T35	132
valid_sources[0x0a]	22933	1			T2	1		T5	1		T55	3
valid_sources[0x0b]	20321	1			T5	2		T13	1		T6	94
valid_sources[0x0c]	22791	1			T10	2		T5	3		T6	165
valid_sources[0x0d]	23404	1			T1	1		T5	2		T64	1
valid_sources[0x0e]	22251	1			T2	2		T12	1		T5	2
valid_sources[0x0f]	22145	1			T1	2		T2	1		T12	2
valid_sources[0x10]	22854	1			T1	2		T2	1		T12	1
valid_sources[0x11]	22312	1			T4	1		T10	1		T5	4
valid_sources[0x12]	25281	1			T3	1		T21	1		T39	9
valid_sources[0x13]	23606	1			T3	2		T12	1		T5	2
valid_sources[0x14]	22642	1			T3	1		T5	1		T6	575
valid_sources[0x15]	22135	1			T5	1		T6	234		T36	447
valid_sources[0x16]	22891	1			T1	6		T3	2		T5	2
valid_sources[0x17]	23084	1			T21	1		T5	1		T13	1
valid_sources[0x18]	23384	1			T12	1		T6	277		T36	325
valid_sources[0x19]	22949	1			T21	2		T5	6		T55	1
valid_sources[0x1a]	23749	1			T2	1		T21	1		T12	1
valid_sources[0x1b]	22008	1			T2	1		T21	2		T5	1
valid_sources[0x1c]	23975	1			T5	3		T6	243		T36	576
valid_sources[0x1d]	22720	1			T12	1		T5	4		T13	1
valid_sources[0x1e]	22709	1			T2	2		T21	4		T13	1
valid_sources[0x1f]	22937	1			T2	2		T10	1		T21	1
valid_sources[0x20]	23673	1			T12	1		T13	1		T6	13
valid_sources[0x21]	22061	1			T1	3		T2	1		T12	1
valid_sources[0x22]	23823	1			T3	2		T5	3		T55	4
valid_sources[0x23]	24282	1			T1	1		T10	2		T5	4
valid_sources[0x24]	23630	1			T1	1		T2	1		T5	2
valid_sources[0x25]	21717	1			T10	2		T21	2		T5	3
valid_sources[0x26]	22137	1			T1	1		T2	1		T3	1
valid_sources[0x27]	22397	1			T5	1		T6	208		T35	320
valid_sources[0x28]	23324	1			T21	1		T5	2		T39	2
valid_sources[0x29]	22608	1			T1	3		T2	1		T5	1
valid_sources[0x2a]	22695	1			T12	1		T5	2		T47	3
valid_sources[0x2b]	24804	1			T10	2		T12	1		T5	2
valid_sources[0x2c]	23333	1			T22	5		T5	3		T6	377
valid_sources[0x2d]	22432	1			T1	1		T2	1		T5	4
valid_sources[0x2e]	22451	1			T5	1		T13	1		T6	121
valid_sources[0x2f]	22851	1			T21	1		T5	2		T6	11
valid_sources[0x30]	23122	1			T2	1		T12	1		T39	5
valid_sources[0x31]	23034	1			T5	2		T13	1		T6	268
valid_sources[0x32]	23070	1			T1	1		T10	4		T5	1
valid_sources[0x33]	22830	1			T5	1		T13	2		T6	387
valid_sources[0x34]	23518	1			T1	3		T13	1		T6	182
valid_sources[0x35]	23755	1			T10	1		T11	12		T5	1
valid_sources[0x36]	23567	1			T1	2		T2	1		T3	1
valid_sources[0x37]	23249	1			T5	2		T13	1		T6	22
valid_sources[0x38]	23521	1			T39	3		T6	18		T35	179
valid_sources[0x39]	22315	1			T3	1		T5	2		T37	94
valid_sources[0x3a]	22287	1			T21	1		T5	2		T13	1
valid_sources[0x3b]	21796	1			T2	2		T6	371		T35	122
valid_sources[0x3c]	24041	1			T2	2		T3	1		T5	1
valid_sources[0x3d]	22337	1			T1	1		T5	1		T39	1
valid_sources[0x3e]	23126	1			T2	1		T4	1		T5	2
valid_sources[0x3f]	23856	1			T5	1		T13	1		T6	443
valid_sources[0x40]	22654	1			T21	1		T5	2		T13	1
valid_sources[0x41]	24136	1			T1	1		T2	2		T5	2
valid_sources[0x42]	22767	1			T10	7		T12	1		T5	2
valid_sources[0x43]	22863	1			T21	1		T12	1		T5	1
valid_sources[0x44]	21147	1			T5	4		T13	2		T6	221
valid_sources[0x45]	23095	1			T1	1		T2	1		T5	2
valid_sources[0x46]	23282	1			T12	1		T5	3		T6	77
valid_sources[0x47]	23007	1			T5	5		T13	2		T6	226
valid_sources[0x48]	21660	1			T2	1		T10	1		T21	3
valid_sources[0x49]	22318	1			T2	2		T12	1		T5	2
valid_sources[0x4a]	24041	1			T5	1		T6	286		T36	375
valid_sources[0x4b]	22960	1			T21	1		T5	2		T13	1
valid_sources[0x4c]	22639	1			T2	1		T10	1		T21	1
valid_sources[0x4d]	23234	1			T10	1		T21	1		T5	2
valid_sources[0x4e]	23267	1			T2	1		T10	2		T5	1
valid_sources[0x4f]	23683	1			T2	1		T5	1		T6	153
valid_sources[0x50]	21608	1			T5	4		T6	225		T36	334
valid_sources[0x51]	22282	1			T2	1		T3	2		T5	1
valid_sources[0x52]	23166	1			T10	2		T5	1		T39	4
valid_sources[0x53]	22406	1			T10	1		T21	1		T55	5
valid_sources[0x54]	22661	1			T1	1		T5	2		T13	1
valid_sources[0x55]	21714	1			T1	1		T10	2		T5	3
valid_sources[0x56]	22106	1			T1	2		T55	4		T6	502
valid_sources[0x57]	23230	1			T10	1		T5	3		T39	2
valid_sources[0x58]	22510	1			T1	1		T2	1		T12	1
valid_sources[0x59]	21764	1			T1	1		T2	1		T5	1
valid_sources[0x5a]	22482	1			T1	2		T5	1		T6	417
valid_sources[0x5b]	23385	1			T55	3		T13	3		T6	192
valid_sources[0x5c]	22928	1			T5	3		T13	2		T23	114
valid_sources[0x5d]	23260	1			T2	1		T5	2		T39	2
valid_sources[0x5e]	22140	1			T5	1		T39	1		T6	200
valid_sources[0x5f]	24040	1			T10	2		T39	6		T6	154
valid_sources[0x60]	23916	1			T2	1		T3	1		T39	4
valid_sources[0x61]	22833	1			T21	1		T5	2		T13	1
valid_sources[0x62]	22813	1			T12	1		T13	1		T39	3
valid_sources[0x63]	23162	1			T21	1		T5	5		T39	4
valid_sources[0x64]	23092	1			T12	1		T5	3		T39	2
valid_sources[0x65]	22983	1			T2	1		T10	1		T12	1
valid_sources[0x66]	23813	1			T3	1		T5	1		T6	104
valid_sources[0x67]	23040	1			T10	1		T21	1		T5	2
valid_sources[0x68]	22560	1			T21	1		T5	5		T55	1
valid_sources[0x69]	22890	1			T5	2		T6	50		T35	568
valid_sources[0x6a]	22296	1			T21	1		T5	1		T13	2
valid_sources[0x6b]	22977	1			T1	1		T10	1		T5	3
valid_sources[0x6c]	22942	1			T2	1		T3	2		T10	2
valid_sources[0x6d]	23484	1			T1	2		T11	7		T5	2
valid_sources[0x6e]	22983	1			T5	3		T13	1		T39	1
valid_sources[0x6f]	22834	1			T5	3		T6	38		T36	353
valid_sources[0x70]	23332	1			T21	1		T12	1		T5	4
valid_sources[0x71]	21655	1			T5	1		T13	1		T6	77
valid_sources[0x72]	22287	1			T1	2		T2	3		T3	1
valid_sources[0x73]	21456	1			T5	1		T6	159		T35	6
valid_sources[0x74]	23370	1			T3	1		T5	3		T39	6
valid_sources[0x75]	24277	1			T1	1		T2	2		T5	3
valid_sources[0x76]	21805	1			T5	1		T13	1		T39	1
valid_sources[0x77]	20849	1			T3	2		T5	1		T6	12
valid_sources[0x78]	21624	1			T3	1		T10	1		T5	1
valid_sources[0x79]	22251	1			T13	1		T6	33		T46	1
valid_sources[0x7a]	21795	1			T1	1		T2	2		T10	1
valid_sources[0x7b]	24840	1			T12	1		T5	1		T6	354
valid_sources[0x7c]	21598	1			T3	1		T21	1		T5	3
valid_sources[0x7d]	22083	1			T2	3		T4	2		T10	1
valid_sources[0x7e]	23111	1			T2	1		T5	6		T39	10
valid_sources[0x7f]	23341	1			T2	1		T39	4		T6	27
valid_sources[0x80]	21169	1			T2	1		T5	2		T6	336

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1310572

1

T1

3

T2

5

T3

11

values[0x0]

all_enables

biggest_size

1949300

1

T1

11

T2

12

T3

9

values[0x1]

all_enables

biggest_size

1943142

1

T1

14

T2

10

T3

5