Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
62.50	62.50	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	62.50	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	24	28	53.85

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	24	28	53.85	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2614	1			T1	3		T2	1		T10	4
non_zero_bins[1]	2018	1			T2	1		T10	1		T5	4
zero	9720	1			T1	1		T2	2		T3	4

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	518	1			T1	1		T21	1		T5	1
uni	3836	1			T1	1		T2	1		T10	1
gen	4542	1			T1	1		T2	1		T3	2
res	874	1			T2	1		T10	2		T5	2
ins	4582	1			T1	1		T2	1		T3	2

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

9485

1

T1

2

T2

3

T3

1

mubi_true

4867

1

T1

2

T2

1

T3

3

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

22

1

T60

1

T273

1

T274

1

pass

14330

1

T1

4

T2

4

T3

4

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	24	28	53.85	24
Automatically Generated Cross Bins	52	24	28	53.85	24
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	*	[fail]	*	--	--	6

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	107	1			T6	1		T65	3		T66	1
upd	non_zero_bins[0]	pass	mubi_true	114	1			T1	1		T5	1		T37	1
upd	non_zero_bins[1]	pass	mubi_false	81	1			T39	1		T35	1		T65	2
upd	non_zero_bins[1]	pass	mubi_true	94	1			T6	1		T66	2		T98	2
upd	zero	pass	mubi_false	68	1			T21	1		T36	2		T65	1
upd	zero	pass	mubi_true	54	1			T6	1		T65	1		T275	1
uni	zero	pass	mubi_false	2822	1			T1	1		T2	1		T10	1
uni	zero	pass	mubi_true	1014	1			T5	1		T6	9		T35	4
gen	non_zero_bins[0]	pass	mubi_false	465	1			T1	1		T10	1		T21	1
gen	non_zero_bins[0]	pass	mubi_true	488	1			T10	3		T6	3		T36	3
gen	non_zero_bins[1]	pass	mubi_false	401	1			T5	2		T6	2		T14	13
gen	non_zero_bins[1]	pass	mubi_true	381	1			T37	1		T13	13		T23	1
gen	zero	fail	mubi_false	21	1			T60	1		T273	1		T274	1
gen	zero	pass	mubi_false	2058	1			T5	4		T37	1		T41	1
gen	zero	pass	mubi_true	728	1			T2	1		T3	2		T4	1
res	non_zero_bins[0]	pass	mubi_false	183	1			T55	1		T6	1		T14	2
res	non_zero_bins[0]	pass	mubi_true	211	1			T5	1		T23	1		T6	1
res	non_zero_bins[1]	pass	mubi_false	140	1			T2	1		T36	2		T65	2
res	non_zero_bins[1]	pass	mubi_true	142	1			T5	1		T13	2		T6	1
res	zero	fail	mubi_false	1	1			T146	1		-	-		-	-
res	zero	pass	mubi_false	103	1			T10	2		T40	1		T65	1
res	zero	pass	mubi_true	94	1			T65	1		T211	2		T276	2
ins	non_zero_bins[0]	pass	mubi_false	520	1			T2	1		T5	3		T37	1
ins	non_zero_bins[0]	pass	mubi_true	526	1			T1	1		T21	1		T5	1
ins	non_zero_bins[1]	pass	mubi_false	387	1			T10	1		T5	1		T6	7
ins	non_zero_bins[1]	pass	mubi_true	392	1			T39	1		T6	3		T36	4
ins	zero	pass	mubi_false	2128	1			T3	1		T4	1		T21	1
ins	zero	pass	mubi_true	629	1			T3	1		T11	1		T12	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded