SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.auto_req_mode | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.boot_req_mode | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.cmd_fifo_rst | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.edn_enable | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 25 | 1 | T100 | 2 | T324 | 2 | T25 | 1 | ||||
others[1] | 17 | 1 | T173 | 2 | T263 | 2 | T156 | 2 | ||||
others[2] | 22 | 1 | T207 | 2 | T325 | 2 | T103 | 2 | ||||
others[3] | 51 | 1 | T69 | 2 | T24 | 1 | T101 | 2 | ||||
false | 3560 | 1 | T1 | 1 | T2 | 1 | T3 | 11 | ||||
true | 750 | 1 | T10 | 1 | T11 | 1 | T12 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 30 | 1 | T135 | 2 | T109 | 2 | T285 | 2 | ||||
others[1] | 15 | 1 | T12 | 2 | T24 | 1 | T115 | 2 | ||||
others[2] | 17 | 1 | T84 | 2 | T170 | 2 | T158 | 2 | ||||
others[3] | 43 | 1 | T11 | 2 | T46 | 2 | T326 | 2 | ||||
false | 3658 | 1 | T1 | 1 | T2 | 1 | T3 | 8 | ||||
true | 662 | 1 | T3 | 3 | T4 | 5 | T21 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 11 | 1 | T74 | 1 | T24 | 1 | T327 | 1 | ||||
others[1] | 11 | 1 | T44 | 1 | T120 | 1 | T125 | 1 | ||||
others[2] | 16 | 1 | T75 | 1 | T86 | 1 | T26 | 1 | ||||
others[3] | 15 | 1 | T80 | 1 | T25 | 1 | T328 | 1 | ||||
false | 3538 | 1 | T1 | 1 | T2 | 1 | T3 | 9 | ||||
true | 834 | 1 | T3 | 2 | T4 | 1 | T10 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 27 | 1 | T3 | 2 | T25 | 1 | T329 | 2 | ||||
others[1] | 22 | 1 | T24 | 1 | T121 | 2 | T131 | 2 | ||||
others[2] | 24 | 1 | T68 | 2 | T77 | 2 | T62 | 2 | ||||
others[3] | 47 | 1 | T60 | 2 | T171 | 2 | T26 | 1 | ||||
false | 1936 | 1 | T3 | 5 | T4 | 2 | T10 | 2 | ||||
true | 2369 | 1 | T1 | 1 | T2 | 1 | T3 | 4 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |