Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.60	100.00	94.44		95.95	97.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	97.60	100.00	94.44		95.95	97.62	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.60	100.00	94.44		95.95	97.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.62	100.00	94.44		95.95	97.73	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		108	108	100.00
ALWAYS	42	3	3	100.00
CONT_ASSIGN	44	1	1	100.00
ALWAYS	47	104	104	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	3	3
44	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
78	1	1
79	1	1
80	1	1
83	1	1
84	1	1
85	1	1
			MISSING_ELSE
89	1	1
90	1	1
93	1	1
94	1	1
			MISSING_ELSE
98	1	1
101	1	1
102	1	1
			MISSING_ELSE
106	1	1
107	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
117	1	1
118	1	1
119	1	1
			MISSING_ELSE
123	1	1
124	1	1
125	1	1
			MISSING_ELSE
129	1	1
130	1	1
131	1	1
			MISSING_ELSE
135	1	1
136	1	1
137	1	1
138	1	1
140	1	1
141	1	1
143	1	1
148	1	1
149	1	1
150	1	1
153	1	1
154	1	1
155	1	1
156	1	1
			MISSING_ELSE
160	1	1
161	1	1
162	1	1
165	1	1
166	1	1
167	1	1
168	1	1
			MISSING_ELSE
172	1	1
175	1	1
178	1	1
186	1	1
188	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
211	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T41
1	1	Covered	T3,T4,T21

 LINE       66
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T20,T108,T78
1	1	Covered	T10,T11,T12

 LINE       186
 EXPRESSION (local_escalate_i || csrng_ack_err_i)
             --------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T11,T12
1	0	Covered	T4,T16,T17

 LINE       188
 EXPRESSION (local_escalate_i ? Error : ((state_q == Error) ? Error : RejectCsrngEntropy))
             --------1-------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T4,T16,T17

 LINE       188
 SUB-EXPRESSION ((state_q == Error) ? Error : RejectCsrngEntropy)
                 ---------1--------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Not Covered

 LINE       188
 SUB-EXPRESSION (state_q == Error)
                ---------1--------

-1-	Status	Tests
0	Covered	T3,T4,T11
1	Covered	T4,T16,T17

 LINE       201
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T11

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	20	100.00	(Not included in score)
Transitions	74	71	95.95
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	156	Covered	T10,T13,T14
AutoCaptGenCnt	143	Covered	T10,T13,T14
AutoCaptReseedCnt	141	Covered	T10,T13,T14
AutoDispatch	125	Covered	T10,T13,T14
AutoFirstAckWait	119	Covered	T10,T12,T13
AutoLoadIns	69	Covered	T10,T11,T12
AutoSendGenCmd	150	Covered	T10,T13,T14
AutoSendReseedCmd	162	Covered	T10,T13,T14
BootDone	98	Covered	T4,T21,T37
BootGenAckWait	90	Covered	T3,T4,T21
BootInsAckWait	80	Covered	T3,T4,T21
BootLoadGen	85	Covered	T3,T4,T21
BootLoadIns	65	Covered	T3,T4,T21
BootLoadUni	102	Covered	T21,T37,T55
BootPulse	94	Covered	T4,T21,T37
BootUniAckWait	107	Covered	T21,T37,T55
Error	188	Covered	T4,T16,T17
Idle	112	Covered	T1,T2,T3
RejectCsrngEntropy	188	Covered	T3,T11,T12
SWPortMode	74	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	131	Covered	T10,T13,T14
AutoAckWait->Error	188	Not Covered
AutoAckWait->Idle	211	Covered	T20,T108,T78
AutoAckWait->RejectCsrngEntropy	188	Covered	T68,T60,T109
AutoCaptGenCnt->AutoSendGenCmd	150	Covered	T10,T13,T14
AutoCaptGenCnt->Error	188	Covered	T8,T110,T111
AutoCaptGenCnt->Idle	211	Covered	T112,T113,T114
AutoCaptGenCnt->RejectCsrngEntropy	188	Covered	T46,T77,T115
AutoCaptReseedCnt->AutoSendReseedCmd	162	Covered	T10,T13,T14
AutoCaptReseedCnt->Error	188	Covered	T9,T116
AutoCaptReseedCnt->Idle	211	Covered	T117,T118,T119
AutoCaptReseedCnt->RejectCsrngEntropy	188	Covered	T88,T120,T121
AutoDispatch->AutoCaptGenCnt	143	Covered	T10,T13,T14
AutoDispatch->AutoCaptReseedCnt	141	Covered	T10,T13,T14
AutoDispatch->Error	188	Covered	T122,T123,T124
AutoDispatch->Idle	138	Covered	T10,T13,T14
AutoDispatch->RejectCsrngEntropy	188	Covered	T125,T126,T127
AutoFirstAckWait->AutoDispatch	125	Covered	T10,T13,T14
AutoFirstAckWait->Error	188	Covered	T128,T129
AutoFirstAckWait->Idle	211	Covered	T108,T78,T130
AutoFirstAckWait->RejectCsrngEntropy	188	Covered	T12,T131,T132
AutoLoadIns->AutoFirstAckWait	119	Covered	T10,T12,T13
AutoLoadIns->Error	188	Covered	T51,T133,T134
AutoLoadIns->Idle	211	Covered	T44,T7,T135
AutoLoadIns->RejectCsrngEntropy	188	Covered	T11,T100,T83
AutoSendGenCmd->AutoAckWait	156	Covered	T10,T13,T14
AutoSendGenCmd->Error	188	Covered	T136,T137
AutoSendGenCmd->Idle	211	Covered	T138,T139,T140
AutoSendGenCmd->RejectCsrngEntropy	188	Covered	T141,T103,T104
AutoSendReseedCmd->AutoAckWait	168	Covered	T10,T13,T14
AutoSendReseedCmd->Error	188	Not Covered
AutoSendReseedCmd->Idle	211	Covered	T142,T63,T143
AutoSendReseedCmd->RejectCsrngEntropy	188	Covered	T144,T145,T146
BootDone->BootLoadUni	102	Covered	T21,T37,T55
BootDone->Error	188	Covered	T147,T148,T149
BootDone->Idle	211	Covered	T79,T150,T151
BootDone->RejectCsrngEntropy	188	Covered	T44,T84,T135
BootGenAckWait->BootPulse	94	Covered	T4,T21,T37
BootGenAckWait->Error	188	Covered	T54,T152
BootGenAckWait->Idle	211	Covered	T73,T153,T154
BootGenAckWait->RejectCsrngEntropy	188	Covered	T3,T61,T155
BootInsAckWait->BootLoadGen	85	Covered	T3,T4,T21
BootInsAckWait->Error	188	Covered	T73,T49,T154
BootInsAckWait->Idle	211	Covered	T4,T41,T70
BootInsAckWait->RejectCsrngEntropy	188	Covered	T156,T157,T158
BootLoadGen->BootGenAckWait	90	Covered	T3,T4,T21
BootLoadGen->Error	188	Covered	T159,T160
BootLoadGen->Idle	211	Covered	T161,T162,T163
BootLoadGen->RejectCsrngEntropy	188	Covered	T69,T164,T165
BootLoadIns->BootInsAckWait	80	Covered	T3,T4,T21
BootLoadIns->Error	188	Covered	T4,T50,T166
BootLoadIns->Idle	211	Covered	T167,T168
BootLoadIns->RejectCsrngEntropy	188	Covered	T169,T170,T171
BootLoadUni->BootUniAckWait	107	Covered	T21,T37,T55
BootLoadUni->Error	188	Covered	T172
BootLoadUni->Idle	211	Not Covered
BootLoadUni->RejectCsrngEntropy	188	Covered	T101,T62,T173
BootPulse->BootDone	98	Covered	T4,T21,T37
BootPulse->Error	188	Covered	T174,T175
BootPulse->Idle	211	Covered	T87,T176,T177
BootPulse->RejectCsrngEntropy	188	Covered	T178,T179,T180
BootUniAckWait->Error	188	Covered	T181,T182,T183
BootUniAckWait->Idle	112	Covered	T21,T37,T55
BootUniAckWait->RejectCsrngEntropy	188	Covered	T74,T75,T86
Idle->AutoLoadIns	69	Covered	T10,T11,T12
Idle->BootLoadIns	65	Covered	T3,T4,T21
Idle->Error	188	Covered	T16,T18,T19
Idle->RejectCsrngEntropy	188	Covered	T11,T12,T69
Idle->SWPortMode	74	Covered	T1,T2,T3
RejectCsrngEntropy->Error	188	Covered	T184,T185,T52
RejectCsrngEntropy->Idle	211	Covered	T3,T11,T12
SWPortMode->Error	188	Covered	T16,T17,T71
SWPortMode->Idle	211	Covered	T3,T11,T12
SWPortMode->RejectCsrngEntropy	188	Covered	T3,T68,T46

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		42	41	97.62
IF	42	2	2	100.00
CASE	62	35	35	100.00
IF	186	5	4	80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	42	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	62	case (state_q)
-2-:	64	if ((boot_req_mode_i && edn_enable_i))
-3-:	66	if ((auto_req_mode_i && edn_enable_i))
-4-:	70	if (edn_enable_i)
-5-:	84	if (csrng_cmd_ack_i)
-6-:	93	if (csrng_cmd_ack_i)
-7-:	101	if ((!boot_req_mode_i))
-8-:	110	if (csrng_cmd_ack_i)
-9-:	118	if (sw_cmd_req_load_i)
-10-:	124	if (csrng_cmd_ack_i)
-11-:	130	if (csrng_cmd_ack_i)
-12-:	136	if ((!auto_req_mode_i))
-13-:	140	if (max_reqs_cnt_zero_i)
-14-:	155	if (cmd_sent_i)
-15-:	167	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T21
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T21
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T21
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T21
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T21
BootGenAckWait	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T21
BootGenAckWait	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T21
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T21,T37
BootDone	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T21,T37,T55
BootDone	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T4,T41,T69
BootLoadUni	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T37,T55
BootUniAckWait	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T21,T37,T55
BootUniAckWait	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T21,T37,T55
AutoLoadIns	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T10,T12,T13
AutoLoadIns	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T10,T11,T12
AutoFirstAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T10,T12,T13
AutoFirstAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T10,T12,T13
AutoAckWait	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T10,T13,T14
AutoAckWait	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T10,T13,T14
AutoDispatch	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T10,T13,T14
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T10,T13,T14
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T10,T13,T14
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T13,T14
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T10,T13,T14
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T10,T13,T14
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T13,T14
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T10,T13,T14
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T10,T13,T14
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
RejectCsrngEntropy	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T11,T12
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T16,T17
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T16,T7,T70

	LineNo.	Expression
-1-:	186	if ((local_escalate_i || csrng_ack_err_i))
-2-:	188	(local_escalate_i) ? 
-3-:	188	((state_q == Error)) ? 
-4-:	201	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy})))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T4,T16,T17
1	0	1	-	Not Covered
1	0	0	-	Covered	T3,T11,T12
0	-	-	1	Covered	T3,T4,T11
0	-	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	206999575	133812	0	0
FpvSecCmErrorStEscalate_A	206999575	134715	0	0
u_state_regs_A	206961496	206790979	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206999575	133812	0	0
T4	451	222	0	0
T5	12250	0	0	0
T7	0	160	0	0
T8	0	628	0	0
T10	3140	0	0	0
T11	2336	0	0	0
T12	2053	0	0	0
T16	0	18166	0	0
T17	0	387	0	0
T21	1153	0	0	0
T22	1203	0	0	0
T37	3398	0	0	0
T47	1313	0	0	0
T48	0	300	0	0
T55	1560	0	0	0
T70	0	600	0	0
T71	0	506	0	0
T72	0	1060	0	0
T73	0	1125	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206999575	134715	0	0
T4	451	223	0	0
T5	12250	0	0	0
T7	0	161	0	0
T8	0	629	0	0
T10	3140	0	0	0
T11	2336	0	0	0
T12	2053	0	0	0
T16	0	18426	0	0
T17	0	388	0	0
T21	1153	0	0	0
T22	1203	0	0	0
T37	3398	0	0	0
T47	1313	0	0	0
T48	0	301	0	0
T55	1560	0	0	0
T70	0	601	0	0
T71	0	507	0	0
T72	0	1061	0	0
T73	0	1126	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206961496	206790979	0	0
T1	2516	2425	0	0
T2	4298	4223	0	0
T3	2087	2012	0	0
T4	329	201	0	0
T5	12250	11526	0	0
T10	3140	3051	0	0
T11	2336	2258	0	0
T12	2053	1977	0	0
T21	1153	1069	0	0
T22	1203	1106	0	0