Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T13,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T10,T11

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T30,T31,T32
1	1	0	Not Covered
1	1	1	Covered	T4,T10,T11

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T28,T33,T34
1	0	1	Covered	T4,T10,T11
1	1	0	Not Covered
1	1	1	Covered	T10,T13,T14

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T4,T10,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	413282978	640545	0	0
DepthKnown_A	413999150	413658116	0	0
RvalidKnown_A	413999150	413658116	0	0
WreadyKnown_A	413999150	413658116	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	413662584	730678	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413282978	640545	0	0
T5	24500	0	0	0
T10	6280	2864	0	0
T11	4672	331	0	0
T12	4106	389	0	0
T13	5022	1976	0	0
T14	0	2456	0	0
T20	0	3206	0	0
T21	2306	0	0	0
T22	2406	0	0	0
T37	6796	0	0	0
T44	0	529	0	0
T46	0	575	0	0
T47	2626	0	0	0
T55	3120	0	0	0
T68	0	435	0	0
T76	0	3493	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413999150	413658116	0	0
T1	5032	4850	0	0
T2	8596	8446	0	0
T3	4174	4024	0	0
T4	902	646	0	0
T5	24500	23052	0	0
T10	6280	6102	0	0
T11	4672	4516	0	0
T12	4106	3954	0	0
T21	2306	2138	0	0
T22	2406	2212	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413999150	413658116	0	0
T1	5032	4850	0	0
T2	8596	8446	0	0
T3	4174	4024	0	0
T4	902	646	0	0
T5	24500	23052	0	0
T10	6280	6102	0	0
T11	4672	4516	0	0
T12	4106	3954	0	0
T21	2306	2138	0	0
T22	2406	2212	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413999150	413658116	0	0
T1	5032	4850	0	0
T2	8596	8446	0	0
T3	4174	4024	0	0
T4	902	646	0	0
T5	24500	23052	0	0
T10	6280	6102	0	0
T11	4672	4516	0	0
T12	4106	3954	0	0
T21	2306	2138	0	0
T22	2406	2212	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	413662584	730678	0	0
T4	902	220	0	0
T5	24500	0	0	0
T10	6280	2864	0	0
T11	4672	331	0	0
T12	4106	389	0	0
T13	0	1976	0	0
T14	0	2456	0	0
T20	0	3206	0	0
T21	2306	0	0	0
T22	2406	0	0	0
T37	6796	0	0	0
T44	0	529	0	0
T46	0	575	0	0
T47	2626	0	0	0
T55	3120	0	0	0
T68	0	435	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T20,T16,T90
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T10,T11

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T91
1	1	0	Not Covered
1	1	1	Covered	T4,T10,T11

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T28,T33,T34
1	0	1	Covered	T4,T10,T11
1	1	0	Not Covered
1	1	1	Covered	T10,T13,T14

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T4,T10,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	206641489	314500	0	0
DepthKnown_A	206999575	206829058	0	0
RvalidKnown_A	206999575	206829058	0	0
WreadyKnown_A	206999575	206829058	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	206831292	359476	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206641489	314500	0	0
T5	12250	0	0	0
T10	3140	1381	0	0
T11	2336	168	0	0
T12	2053	199	0	0
T13	2511	983	0	0
T14	0	1185	0	0
T20	0	1593	0	0
T21	1153	0	0	0
T22	1203	0	0	0
T37	3398	0	0	0
T44	0	218	0	0
T46	0	291	0	0
T47	1313	0	0	0
T55	1560	0	0	0
T68	0	219	0	0
T76	0	1710	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206999575	206829058	0	0
T1	2516	2425	0	0
T2	4298	4223	0	0
T3	2087	2012	0	0
T4	451	323	0	0
T5	12250	11526	0	0
T10	3140	3051	0	0
T11	2336	2258	0	0
T12	2053	1977	0	0
T21	1153	1069	0	0
T22	1203	1106	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206999575	206829058	0	0
T1	2516	2425	0	0
T2	4298	4223	0	0
T3	2087	2012	0	0
T4	451	323	0	0
T5	12250	11526	0	0
T10	3140	3051	0	0
T11	2336	2258	0	0
T12	2053	1977	0	0
T21	1153	1069	0	0
T22	1203	1106	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206999575	206829058	0	0
T1	2516	2425	0	0
T2	4298	4223	0	0
T3	2087	2012	0	0
T4	451	323	0	0
T5	12250	11526	0	0
T10	3140	3051	0	0
T11	2336	2258	0	0
T12	2053	1977	0	0
T21	1153	1069	0	0
T22	1203	1106	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	206831292	359476	0	0
T4	451	111	0	0
T5	12250	0	0	0
T10	3140	1381	0	0
T11	2336	168	0	0
T12	2053	199	0	0
T13	0	983	0	0
T14	0	1185	0	0
T20	0	1593	0	0
T21	1153	0	0	0
T22	1203	0	0	0
T37	3398	0	0	0
T44	0	218	0	0
T46	0	291	0	0
T47	1313	0	0	0
T55	1560	0	0	0
T68	0	219	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T13,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T10,T11

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T30,T31,T32
1	1	0	Not Covered
1	1	1	Covered	T4,T10,T11

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T92,T93,T94
1	0	1	Covered	T4,T10,T11
1	1	0	Not Covered
1	1	1	Covered	T10,T13,T14

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T4,T10,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	206641489	326045	0	0
DepthKnown_A	206999575	206829058	0	0
RvalidKnown_A	206999575	206829058	0	0
WreadyKnown_A	206999575	206829058	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	206831292	371202	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206641489	326045	0	0
T5	12250	0	0	0
T10	3140	1483	0	0
T11	2336	163	0	0
T12	2053	190	0	0
T13	2511	993	0	0
T14	0	1271	0	0
T20	0	1613	0	0
T21	1153	0	0	0
T22	1203	0	0	0
T37	3398	0	0	0
T44	0	311	0	0
T46	0	284	0	0
T47	1313	0	0	0
T55	1560	0	0	0
T68	0	216	0	0
T76	0	1783	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206999575	206829058	0	0
T1	2516	2425	0	0
T2	4298	4223	0	0
T3	2087	2012	0	0
T4	451	323	0	0
T5	12250	11526	0	0
T10	3140	3051	0	0
T11	2336	2258	0	0
T12	2053	1977	0	0
T21	1153	1069	0	0
T22	1203	1106	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206999575	206829058	0	0
T1	2516	2425	0	0
T2	4298	4223	0	0
T3	2087	2012	0	0
T4	451	323	0	0
T5	12250	11526	0	0
T10	3140	3051	0	0
T11	2336	2258	0	0
T12	2053	1977	0	0
T21	1153	1069	0	0
T22	1203	1106	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206999575	206829058	0	0
T1	2516	2425	0	0
T2	4298	4223	0	0
T3	2087	2012	0	0
T4	451	323	0	0
T5	12250	11526	0	0
T10	3140	3051	0	0
T11	2336	2258	0	0
T12	2053	1977	0	0
T21	1153	1069	0	0
T22	1203	1106	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	206831292	371202	0	0
T4	451	109	0	0
T5	12250	0	0	0
T10	3140	1483	0	0
T11	2336	163	0	0
T12	2053	190	0	0
T13	0	993	0	0
T14	0	1271	0	0
T20	0	1613	0	0
T21	1153	0	0	0
T22	1203	0	0	0
T37	3398	0	0	0
T44	0	311	0	0
T46	0	284	0	0
T47	1313	0	0	0
T55	1560	0	0	0
T68	0	216	0	0