Unified Coverage Report :: Group :: tb.dut.u_edn_cov_if::edn_cfg_cg

Group : tb.dut.u_edn_cov_if::edn_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
edn_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : edn_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance edn_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	21	0	21	100.00

Variables for Group Instance edn_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mode	3	0	3	100.00	100	1	1	0
cp_num_boot_reqs	2	0	2	100.00	100	1	1	0
cp_num_endpoints	7	0	7	100.00	100	1	1	8

Crosses for Group Instance edn_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_num_endpoints_mode	21	0	21	100.00	100	1	1	0

Summary for Variable cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_mode

Excluded/Illegal bins

NAME	COUNT	STATUS
both	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
boot_req_mode	138	1			T2	1		T22	1		T23	1
auto_req_mode	143	1			T8	1		T17	1		T9	1
sw_mode	2960	1			T1	2		T21	1		T4	66

---

Summary for Variable cp_num_boot_reqs

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_boot_reqs

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

multiple

309

1

T2

1

T22

1

T23

1

single

91

1

T21

1

T76

1

T8

1

---

Summary for Variable cp_num_endpoints

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_num_endpoints

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	1346	1			T2	1		T21	1		T22	1
auto[2]	166	1			T60	5		T39	1		T225	1
auto[3]	36	1			T10	1		T285	1		T286	1
auto[4]	89	1			T9	1		T89	1		T215	60
auto[5]	136	1			T8	1		T40	1		T71	67
auto[6]	38	1			T46	1		T287	6		T288	1
auto[7]	1430	1			T1	2		T23	1		T38	23

---

Summary for Cross cr_num_endpoints_mode

Samples crossed: cp_num_endpoints cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	21	0	21	100.00

Automatically Generated Cross Bins for cr_num_endpoints_mode

Excluded/Illegal bins

cp_num_endpoints	cp_mode	COUNT	STATUS
[auto[0]]	[boot_req_mode , auto_req_mode , sw_mode]	--	Excluded	(3 bins)

Covered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	boot_req_mode	80	1			T2	1		T22	1		T24	1
auto[1]	auto_req_mode	79	1			T19	1		T47	1		T73	1
auto[1]	sw_mode	1187	1			T21	1		T4	66		T25	8
auto[2]	boot_req_mode	5	1			T225	1		T289	1		T290	1
auto[2]	auto_req_mode	5	1			T291	1		T292	1		T293	1
auto[2]	sw_mode	156	1			T60	5		T39	1		T294	1
auto[3]	boot_req_mode	4	1			T286	1		T295	1		T296	1
auto[3]	auto_req_mode	3	1			T10	1		T297	1		T298	1
auto[3]	sw_mode	29	1			T285	1		T299	4		T300	1
auto[4]	boot_req_mode	3	1			T301	1		T302	1		T303	1
auto[4]	auto_req_mode	3	1			T9	1		T89	1		T304	1
auto[4]	sw_mode	83	1			T215	60		T305	1		T306	1
auto[5]	boot_req_mode	3	1			T307	1		T308	1		T309	1
auto[5]	auto_req_mode	9	1			T8	1		T310	1		T311	1
auto[5]	sw_mode	124	1			T40	1		T71	67		T42	1
auto[6]	boot_req_mode	3	1			T288	1		T312	1		T313	1
auto[6]	auto_req_mode	5	1			T46	1		T314	1		T315	1
auto[6]	sw_mode	30	1			T287	6		T316	9		T317	4
auto[7]	boot_req_mode	40	1			T23	1		T44	1		T68	1
auto[7]	auto_req_mode	39	1			T17	1		T18	1		T50	1
auto[7]	sw_mode	1351	1			T1	2		T38	23		T177	8