SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
58.33 | 58.33 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
edn_sw_cmd_sts_cg | 58.33 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
58.33 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 12 | 5 | 7 | 58.33 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_cmd_ack_cg | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 0 | |
cp_cmd_rdy_cg | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 0 | |
cp_cmd_reg_rdy_cg | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 0 | |
cp_cmd_sts_cg | 6 | 5 | 1 | 16.67 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
no_ack | 27918 | 1 | T1 | 30 | T21 | 12 | T22 | 6 | ||||
ack | 22241 | 1 | T1 | 16 | T21 | 7 | T22 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
not_ready | 27078 | 1 | T1 | 28 | T21 | 11 | T22 | 5 | ||||
ready | 23081 | 1 | T1 | 18 | T21 | 8 | T22 | 8 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
not_ready | 511 | 1 | T4 | 9 | T8 | 1 | T37 | 7 | ||||
ready | 49648 | 1 | T1 | 46 | T21 | 19 | T22 | 13 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 6 | 5 | 1 | 16.67 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
auto[CMD_STS_INVALID_ACMD] | 0 | 1 | 1 | |
auto[CMD_STS_INVALID_GEN_CMD] | 0 | 1 | 1 | |
auto[CMD_STS_INVALID_CMD_SEQ] | 0 | 1 | 1 | |
auto[CMD_STS_RESEED_CNT_EXCEEDED] | 0 | 1 | 1 | |
auto[CMD_STS_UNDRIVEN] | 0 | 1 | 1 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[CMD_STS_SUCCESS] | 50159 | 1 | T1 | 46 | T21 | 19 | T22 | 13 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |