Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	671804	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5450485

1

T1

66

T2

4

T3

67

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1612838	1			T1	113		T2	1		T3	6
values[0x0]	2083713	1			T1	35		T2	3		T3	36
values[0x1]	2425738	1			T1	37		T2	1		T3	38

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	331719	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5790570

1

T1

86

T2

4

T3

69

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	25023	1			T4	222		T8	3		T60	2
valid_sources[0x01]	22937	1			T22	1		T4	223		T25	6
valid_sources[0x02]	26115	1			T21	1		T4	251		T37	1338
valid_sources[0x03]	22657	1			T4	230		T25	4		T60	2
valid_sources[0x04]	22138	1			T4	283		T25	1		T60	3
valid_sources[0x05]	24090	1			T4	254		T25	3		T76	1
valid_sources[0x06]	23205	1			T21	2		T4	255		T25	1
valid_sources[0x07]	23489	1			T4	213		T25	2		T60	6
valid_sources[0x08]	23367	1			T4	241		T25	6		T60	1
valid_sources[0x09]	24196	1			T4	264		T25	3		T60	3
valid_sources[0x0a]	22624	1			T4	218		T25	3		T37	1244
valid_sources[0x0b]	24453	1			T4	217		T25	1		T76	1
valid_sources[0x0c]	24480	1			T4	246		T25	2		T60	2
valid_sources[0x0d]	25180	1			T4	287		T25	3		T60	3
valid_sources[0x0e]	25455	1			T4	219		T25	1		T60	3
valid_sources[0x0f]	25053	1			T4	236		T25	4		T76	1
valid_sources[0x10]	24203	1			T4	242		T25	6		T37	1342
valid_sources[0x11]	23799	1			T4	226		T7	1		T76	1
valid_sources[0x12]	25426	1			T4	208		T25	4		T8	2
valid_sources[0x13]	25137	1			T4	220		T37	1308		T38	230
valid_sources[0x14]	24292	1			T21	1		T4	248		T25	1
valid_sources[0x15]	24234	1			T4	239		T25	6		T60	1
valid_sources[0x16]	23159	1			T21	1		T4	245		T25	2
valid_sources[0x17]	23548	1			T4	209		T8	4		T60	1
valid_sources[0x18]	24533	1			T21	1		T22	2		T4	231
valid_sources[0x19]	21884	1			T21	1		T23	20		T4	206
valid_sources[0x1a]	25473	1			T4	273		T76	1		T60	1
valid_sources[0x1b]	25401	1			T4	232		T25	3		T76	1
valid_sources[0x1c]	22754	1			T4	268		T25	1		T60	3
valid_sources[0x1d]	25427	1			T21	1		T4	251		T25	2
valid_sources[0x1e]	23481	1			T22	3		T4	241		T25	7
valid_sources[0x1f]	25362	1			T21	1		T4	317		T25	4
valid_sources[0x20]	23683	1			T4	228		T60	2		T37	1342
valid_sources[0x21]	23726	1			T21	1		T4	258		T25	2
valid_sources[0x22]	22501	1			T22	1		T4	224		T25	1
valid_sources[0x23]	23329	1			T4	273		T25	1		T7	1
valid_sources[0x24]	23049	1			T21	1		T4	245		T25	3
valid_sources[0x25]	24512	1			T21	1		T22	6		T23	2
valid_sources[0x26]	23039	1			T4	201		T25	6		T60	2
valid_sources[0x27]	23307	1			T4	199		T25	2		T37	1366
valid_sources[0x28]	23249	1			T22	4		T4	237		T25	3
valid_sources[0x29]	23055	1			T4	239		T37	1326		T51	1
valid_sources[0x2a]	24109	1			T23	2		T4	213		T25	4
valid_sources[0x2b]	26284	1			T4	216		T25	3		T14	12
valid_sources[0x2c]	23647	1			T4	221		T25	3		T60	1
valid_sources[0x2d]	24176	1			T4	211		T25	1		T60	1
valid_sources[0x2e]	23758	1			T4	234		T25	2		T60	2
valid_sources[0x2f]	24277	1			T3	13		T4	236		T25	2
valid_sources[0x30]	23894	1			T4	248		T7	3		T60	6
valid_sources[0x31]	24750	1			T4	223		T25	3		T76	2
valid_sources[0x32]	23972	1			T4	243		T25	4		T14	2
valid_sources[0x33]	24907	1			T4	244		T25	1		T37	1279
valid_sources[0x34]	21878	1			T4	244		T25	2		T76	1
valid_sources[0x35]	23665	1			T4	184		T37	1316		T38	234
valid_sources[0x36]	23084	1			T22	1		T4	224		T25	4
valid_sources[0x37]	22295	1			T3	1		T22	3		T4	231
valid_sources[0x38]	23206	1			T2	1		T4	247		T25	3
valid_sources[0x39]	22758	1			T21	1		T4	240		T76	1
valid_sources[0x3a]	24632	1			T4	205		T60	2		T37	1286
valid_sources[0x3b]	23748	1			T4	232		T25	2		T60	2
valid_sources[0x3c]	23059	1			T4	253		T25	2		T60	3
valid_sources[0x3d]	22234	1			T4	235		T25	1		T76	1
valid_sources[0x3e]	24433	1			T4	249		T76	1		T60	1
valid_sources[0x3f]	24706	1			T21	1		T4	257		T25	3
valid_sources[0x40]	22324	1			T4	218		T25	3		T76	2
valid_sources[0x41]	24067	1			T4	247		T25	1		T7	1
valid_sources[0x42]	25904	1			T4	280		T7	2		T60	2
valid_sources[0x43]	23687	1			T21	1		T4	219		T25	1
valid_sources[0x44]	24349	1			T4	213		T25	2		T7	1
valid_sources[0x45]	23799	1			T4	286		T25	2		T7	1
valid_sources[0x46]	24196	1			T22	1		T4	246		T25	1
valid_sources[0x47]	24304	1			T3	4		T4	245		T76	1
valid_sources[0x48]	23561	1			T21	1		T4	283		T25	5
valid_sources[0x49]	22666	1			T4	266		T25	3		T76	1
valid_sources[0x4a]	24068	1			T4	273		T25	3		T8	2
valid_sources[0x4b]	24633	1			T4	259		T76	1		T60	1
valid_sources[0x4c]	23334	1			T4	275		T25	1		T8	3
valid_sources[0x4d]	24932	1			T21	1		T4	246		T25	1
valid_sources[0x4e]	24616	1			T4	241		T25	1		T60	1
valid_sources[0x4f]	24446	1			T4	251		T60	2		T37	1297
valid_sources[0x50]	24606	1			T4	279		T25	2		T60	3
valid_sources[0x51]	24289	1			T4	259		T25	7		T60	2
valid_sources[0x52]	23467	1			T4	247		T25	2		T60	3
valid_sources[0x53]	23837	1			T21	1		T22	2		T23	18
valid_sources[0x54]	24820	1			T4	282		T25	3		T60	1
valid_sources[0x55]	22747	1			T4	259		T25	4		T37	1275
valid_sources[0x56]	24967	1			T4	250		T25	7		T76	1
valid_sources[0x57]	23972	1			T4	199		T37	1296		T38	292
valid_sources[0x58]	26113	1			T22	3		T4	217		T25	2
valid_sources[0x59]	24494	1			T4	216		T25	1		T8	2
valid_sources[0x5a]	22645	1			T4	260		T25	5		T60	1
valid_sources[0x5b]	22935	1			T4	226		T37	1319		T38	271
valid_sources[0x5c]	24228	1			T4	230		T25	3		T60	3
valid_sources[0x5d]	23595	1			T21	1		T4	232		T25	2
valid_sources[0x5e]	25626	1			T4	255		T25	2		T37	1269
valid_sources[0x5f]	25878	1			T4	263		T25	1		T60	1
valid_sources[0x60]	23589	1			T4	286		T25	1		T60	1
valid_sources[0x61]	24119	1			T21	1		T4	218		T25	4
valid_sources[0x62]	23183	1			T4	194		T25	2		T37	1280
valid_sources[0x63]	23345	1			T21	1		T4	261		T60	1
valid_sources[0x64]	22038	1			T4	195		T25	2		T14	3
valid_sources[0x65]	22936	1			T4	237		T25	3		T76	1
valid_sources[0x66]	24273	1			T4	252		T25	2		T60	2
valid_sources[0x67]	24479	1			T21	1		T4	224		T25	2
valid_sources[0x68]	23441	1			T21	2		T23	14		T4	184
valid_sources[0x69]	22907	1			T21	2		T4	229		T25	1
valid_sources[0x6a]	23409	1			T4	284		T25	2		T76	1
valid_sources[0x6b]	25103	1			T4	221		T25	1		T60	1
valid_sources[0x6c]	24260	1			T4	262		T25	9		T37	1290
valid_sources[0x6d]	23278	1			T21	1		T4	187		T25	3
valid_sources[0x6e]	23261	1			T4	260		T25	6		T60	2
valid_sources[0x6f]	24260	1			T4	227		T7	1		T37	1209
valid_sources[0x70]	25625	1			T3	7		T22	2		T4	220
valid_sources[0x71]	23461	1			T4	220		T60	3		T37	1298
valid_sources[0x72]	24664	1			T4	244		T7	1		T8	1
valid_sources[0x73]	24447	1			T4	205		T25	1		T14	2
valid_sources[0x74]	23930	1			T21	1		T4	222		T25	1
valid_sources[0x75]	24019	1			T21	1		T4	260		T25	3
valid_sources[0x76]	25343	1			T4	220		T25	1		T76	1
valid_sources[0x77]	23308	1			T4	258		T25	3		T60	1
valid_sources[0x78]	20669	1			T4	247		T25	3		T37	1326
valid_sources[0x79]	25589	1			T21	1		T4	245		T25	1
valid_sources[0x7a]	22744	1			T21	1		T4	236		T25	1
valid_sources[0x7b]	26759	1			T22	3		T4	265		T60	2
valid_sources[0x7c]	23430	1			T4	244		T25	2		T76	1
valid_sources[0x7d]	23553	1			T4	201		T25	1		T60	1
valid_sources[0x7e]	24914	1			T4	271		T25	1		T76	3
valid_sources[0x7f]	23760	1			T4	267		T25	2		T7	1
valid_sources[0x80]	23107	1			T21	1		T4	238		T60	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1373461

1

T1

17

T2

1

T3

2

values[0x0]

all_enables

biggest_size

2039499

1

T1

25

T2

2

T3

30

values[0x1]

all_enables

biggest_size

2037525

1

T1

24

T2

1

T3

35