Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
62.50	62.50	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	62.50	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	24	28	53.85

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	24	28	53.85	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2696	1			T1	4		T22	2		T23	2
non_zero_bins[1]	2058	1			T1	1		T21	1		T4	34
zero	9554	1			T1	4		T2	3		T3	2

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	547	1			T1	1		T21	1		T4	11
uni	3787	1			T1	3		T21	1		T22	2
gen	4560	1			T1	2		T2	1		T3	1
res	897	1			T22	1		T23	1		T4	9
ins	4517	1			T1	3		T2	2		T3	1

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

9361

1

T1

6

T2

2

T3

2

mubi_true

4947

1

T1

3

T2

1

T21

3

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

12

1

T7

1

T51

1

T92

1

pass

14296

1

T1

9

T2

3

T3

2

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	24	28	53.85	24
Automatically Generated Cross Bins	52	24	28	53.85	24
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	*	[fail]	*	--	--	6

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	142	1			T4	2		T25	1		T37	3
upd	non_zero_bins[0]	pass	mubi_true	112	1			T4	2		T37	1		T71	2
upd	non_zero_bins[1]	pass	mubi_false	86	1			T4	2		T76	1		T60	1
upd	non_zero_bins[1]	pass	mubi_true	98	1			T1	1		T4	1		T178	1
upd	zero	pass	mubi_false	51	1			T4	3		T37	1		T211	1
upd	zero	pass	mubi_true	58	1			T21	1		T4	1		T25	1
uni	zero	pass	mubi_false	2811	1			T1	3		T21	1		T22	2
uni	zero	pass	mubi_true	976	1			T4	26		T25	1		T60	2
gen	non_zero_bins[0]	pass	mubi_false	461	1			T22	1		T4	5		T60	1
gen	non_zero_bins[0]	pass	mubi_true	521	1			T1	1		T4	9		T25	3
gen	non_zero_bins[1]	pass	mubi_false	412	1			T4	4		T25	1		T8	7
gen	non_zero_bins[1]	pass	mubi_true	408	1			T4	5		T37	2		T39	1
gen	zero	fail	mubi_false	11	1			T7	1		T51	1		T92	1
gen	zero	pass	mubi_false	1944	1			T1	1		T3	1		T22	1
gen	zero	pass	mubi_true	803	1			T2	1		T21	1		T4	3
res	non_zero_bins[0]	pass	mubi_false	180	1			T4	1		T37	5		T71	1
res	non_zero_bins[0]	pass	mubi_true	206	1			T23	1		T4	1		T8	2
res	non_zero_bins[1]	pass	mubi_false	152	1			T4	2		T25	1		T60	1
res	non_zero_bins[1]	pass	mubi_true	149	1			T4	4		T37	1		T71	4
res	zero	fail	mubi_false	1	1			T143	1		-	-		-	-
res	zero	pass	mubi_false	108	1			T22	1		T4	1		T38	1
res	zero	pass	mubi_true	101	1			T25	1		T71	3		T9	2
ins	non_zero_bins[0]	pass	mubi_false	556	1			T1	2		T23	1		T4	7
ins	non_zero_bins[0]	pass	mubi_true	518	1			T1	1		T22	1		T4	6
ins	non_zero_bins[1]	pass	mubi_false	369	1			T4	6		T60	1		T37	8
ins	non_zero_bins[1]	pass	mubi_true	384	1			T21	1		T4	10		T25	2
ins	zero	pass	mubi_false	2077	1			T2	2		T3	1		T22	1
ins	zero	pass	mubi_true	613	1			T4	4		T7	1		T11	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded