SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.auto_req_mode | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.boot_req_mode | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.cmd_fifo_rst | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.edn_enable | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 22 | 1 | T87 | 2 | T274 | 2 | T275 | 2 | ||||
others[1] | 10 | 1 | T227 | 2 | T276 | 2 | T277 | 2 | ||||
others[2] | 23 | 1 | T20 | 2 | T92 | 2 | T121 | 2 | ||||
others[3] | 33 | 1 | T7 | 2 | T29 | 2 | T26 | 1 | ||||
false | 3567 | 1 | T1 | 2 | T2 | 2 | T3 | 4 | ||||
true | 816 | 1 | T3 | 5 | T7 | 1 | T8 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 22 | 1 | T153 | 2 | T155 | 2 | T278 | 2 | ||||
others[1] | 20 | 1 | T41 | 2 | T51 | 2 | T228 | 2 | ||||
others[2] | 30 | 1 | T125 | 2 | T82 | 2 | T66 | 2 | ||||
others[3] | 40 | 1 | T166 | 2 | T26 | 1 | T93 | 2 | ||||
false | 3736 | 1 | T1 | 2 | T3 | 9 | T21 | 1 | ||||
true | 623 | 1 | T2 | 2 | T22 | 1 | T23 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 16 | 1 | T101 | 1 | T27 | 1 | T149 | 1 | ||||
others[1] | 11 | 1 | T204 | 1 | T162 | 1 | T279 | 1 | ||||
others[2] | 14 | 1 | T14 | 1 | T61 | 1 | T52 | 1 | ||||
others[3] | 29 | 1 | T280 | 1 | T271 | 1 | T209 | 1 | ||||
false | 3547 | 1 | T1 | 2 | T2 | 2 | T3 | 6 | ||||
true | 854 | 1 | T3 | 3 | T7 | 2 | T8 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 29 | 1 | T83 | 2 | T126 | 2 | T172 | 2 | ||||
others[1] | 21 | 1 | T26 | 1 | T281 | 2 | T282 | 2 | ||||
others[2] | 13 | 1 | T181 | 2 | T283 | 2 | T284 | 2 | ||||
others[3] | 39 | 1 | T84 | 2 | T90 | 2 | T154 | 2 | ||||
false | 2013 | 1 | T3 | 6 | T7 | 5 | T8 | 2 | ||||
true | 2356 | 1 | T1 | 2 | T2 | 2 | T3 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |