Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.06	100.00	94.44		93.24	97.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	97.06	100.00	94.44		93.24	97.62	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.06	100.00	94.44		93.24	97.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.08	100.00	94.44		93.24	97.73	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		108	108	100.00
ALWAYS	42	3	3	100.00
CONT_ASSIGN	44	1	1	100.00
ALWAYS	47	104	104	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	3	3
44	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
78	1	1
79	1	1
80	1	1
83	1	1
84	1	1
85	1	1
			MISSING_ELSE
89	1	1
90	1	1
93	1	1
94	1	1
			MISSING_ELSE
98	1	1
101	1	1
102	1	1
			MISSING_ELSE
106	1	1
107	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
117	1	1
118	1	1
119	1	1
			MISSING_ELSE
123	1	1
124	1	1
125	1	1
			MISSING_ELSE
129	1	1
130	1	1
131	1	1
			MISSING_ELSE
135	1	1
136	1	1
137	1	1
138	1	1
140	1	1
141	1	1
143	1	1
148	1	1
149	1	1
150	1	1
153	1	1
154	1	1
155	1	1
156	1	1
			MISSING_ELSE
160	1	1
161	1	1
162	1	1
165	1	1
166	1	1
167	1	1
168	1	1
			MISSING_ELSE
172	1	1
175	1	1
178	1	1
186	1	1
188	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
211	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T21
1	0	Covered	T2,T24,T11
1	1	Covered	T2,T22,T23

 LINE       66
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T21,T22
1	0	Covered	T3,T19,T47
1	1	Covered	T3,T7,T8

 LINE       186
 EXPRESSION (local_escalate_i || csrng_ack_err_i)
             --------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T14,T29
1	0	Covered	T3,T11,T12

 LINE       188
 EXPRESSION (local_escalate_i ? Error : ((state_q == Error) ? Error : RejectCsrngEntropy))
             --------1-------

-1-	Status	Tests
0	Covered	T7,T14,T29
1	Covered	T3,T11,T12

 LINE       188
 SUB-EXPRESSION ((state_q == Error) ? Error : RejectCsrngEntropy)
                 ---------1--------

-1-	Status	Tests
0	Covered	T7,T14,T29
1	Not Covered

 LINE       188
 SUB-EXPRESSION (state_q == Error)
                ---------1--------

-1-	Status	Tests
0	Covered	T3,T7,T11
1	Covered	T3,T11,T12

 LINE       201
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T24

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	20	100.00	(Not included in score)
Transitions	74	69	93.24
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	156	Covered	T3,T7,T8
AutoCaptGenCnt	143	Covered	T3,T7,T8
AutoCaptReseedCnt	141	Covered	T8,T20,T17
AutoDispatch	125	Covered	T3,T7,T8
AutoFirstAckWait	119	Covered	T3,T7,T8
AutoLoadIns	69	Covered	T3,T7,T8
AutoSendGenCmd	150	Covered	T3,T7,T8
AutoSendReseedCmd	162	Covered	T8,T20,T17
BootDone	98	Covered	T2,T22,T23
BootGenAckWait	90	Covered	T2,T22,T23
BootInsAckWait	80	Covered	T2,T22,T23
BootLoadGen	85	Covered	T2,T22,T23
BootLoadIns	65	Covered	T2,T22,T23
BootLoadUni	102	Covered	T22,T23,T14
BootPulse	94	Covered	T2,T22,T23
BootUniAckWait	107	Covered	T22,T23,T14
Error	188	Covered	T3,T11,T12
Idle	112	Covered	T1,T2,T3
RejectCsrngEntropy	188	Covered	T7,T14,T29
SWPortMode	74	Covered	T1,T21,T22

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	131	Covered	T8,T20,T17
AutoAckWait->Error	188	Covered	T102,T103,T104
AutoAckWait->Idle	211	Covered	T19,T47,T73
AutoAckWait->RejectCsrngEntropy	188	Covered	T7,T51,T61
AutoCaptGenCnt->AutoSendGenCmd	150	Covered	T3,T7,T8
AutoCaptGenCnt->Error	188	Covered	T56,T105
AutoCaptGenCnt->Idle	211	Covered	T19,T106,T107
AutoCaptGenCnt->RejectCsrngEntropy	188	Covered	T82,T108,T109
AutoCaptReseedCnt->AutoSendReseedCmd	162	Covered	T8,T20,T17
AutoCaptReseedCnt->Error	188	Covered	T110,T111
AutoCaptReseedCnt->Idle	211	Covered	T112,T113,T114
AutoCaptReseedCnt->RejectCsrngEntropy	188	Covered	T115,T116,T117
AutoDispatch->AutoCaptGenCnt	143	Covered	T3,T7,T8
AutoDispatch->AutoCaptReseedCnt	141	Covered	T8,T20,T17
AutoDispatch->Error	188	Covered	T118,T119,T120
AutoDispatch->Idle	138	Covered	T8,T17,T9
AutoDispatch->RejectCsrngEntropy	188	Covered	T41,T87,T121
AutoFirstAckWait->AutoDispatch	125	Covered	T3,T7,T8
AutoFirstAckWait->Error	188	Covered	T122,T123
AutoFirstAckWait->Idle	211	Covered	T47,T73,T124
AutoFirstAckWait->RejectCsrngEntropy	188	Covered	T125,T126,T127
AutoLoadIns->AutoFirstAckWait	119	Covered	T3,T7,T8
AutoLoadIns->Error	188	Covered	T54,T128,T129
AutoLoadIns->Idle	211	Covered	T3,T14,T61
AutoLoadIns->RejectCsrngEntropy	188	Covered	T130,T131,T132
AutoSendGenCmd->AutoAckWait	156	Covered	T3,T7,T8
AutoSendGenCmd->Error	188	Covered	T133
AutoSendGenCmd->Idle	211	Covered	T134,T135,T136
AutoSendGenCmd->RejectCsrngEntropy	188	Covered	T52,T101,T90
AutoSendReseedCmd->AutoAckWait	168	Covered	T8,T20,T17
AutoSendReseedCmd->Error	188	Covered	T137,T138,T139
AutoSendReseedCmd->Idle	211	Covered	T140,T141,T142
AutoSendReseedCmd->RejectCsrngEntropy	188	Covered	T143,T144,T145
BootDone->BootLoadUni	102	Covered	T22,T23,T14
BootDone->Error	188	Covered	T11,T146
BootDone->Idle	211	Covered	T95,T91,T147
BootDone->RejectCsrngEntropy	188	Covered	T29,T148,T149
BootGenAckWait->BootPulse	94	Covered	T2,T22,T23
BootGenAckWait->Error	188	Covered	T55,T150
BootGenAckWait->Idle	211	Covered	T78,T151,T152
BootGenAckWait->RejectCsrngEntropy	188	Covered	T83,T98,T153
BootInsAckWait->BootLoadGen	85	Covered	T2,T22,T23
BootInsAckWait->Error	188	Covered	T77,T58,T152
BootInsAckWait->Idle	211	Covered	T24,T11,T77
BootInsAckWait->RejectCsrngEntropy	188	Covered	T93,T154,T155
BootLoadGen->BootGenAckWait	90	Covered	T2,T22,T23
BootLoadGen->Error	188	Not Covered
BootLoadGen->Idle	211	Covered	T2,T156,T94
BootLoadGen->RejectCsrngEntropy	188	Covered	T157,T158,T159
BootLoadIns->BootInsAckWait	80	Covered	T2,T22,T23
BootLoadIns->Error	188	Covered	T53,T59,T160
BootLoadIns->Idle	211	Not Covered
BootLoadIns->RejectCsrngEntropy	188	Covered	T84,T161,T162
BootLoadUni->BootUniAckWait	107	Covered	T22,T23,T14
BootLoadUni->Error	188	Covered	T163,T164,T165
BootLoadUni->Idle	211	Not Covered
BootLoadUni->RejectCsrngEntropy	188	Covered	T166,T167,T168
BootPulse->BootDone	98	Covered	T2,T22,T23
BootPulse->Error	188	Not Covered
BootPulse->Idle	211	Covered	T65,T169,T170
BootPulse->RejectCsrngEntropy	188	Covered	T66,T171,T172
BootUniAckWait->Error	188	Covered	T156,T173,T174
BootUniAckWait->Idle	112	Covered	T22,T23,T29
BootUniAckWait->RejectCsrngEntropy	188	Covered	T14,T81,T88
Idle->AutoLoadIns	69	Covered	T3,T7,T8
Idle->BootLoadIns	65	Covered	T2,T22,T23
Idle->Error	188	Covered	T13,T15,T16
Idle->RejectCsrngEntropy	188	Covered	T14,T29,T166
Idle->SWPortMode	74	Covered	T1,T21,T22
RejectCsrngEntropy->Error	188	Not Covered
RejectCsrngEntropy->Idle	211	Covered	T7,T14,T29
SWPortMode->Error	188	Covered	T12,T13,T175
SWPortMode->Idle	211	Covered	T1,T4,T25
SWPortMode->RejectCsrngEntropy	188	Covered	T7,T41,T51

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		42	41	97.62
IF	42	2	2	100.00
CASE	62	35	35	100.00
IF	186	5	4	80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	42	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	62	case (state_q)
-2-:	64	if ((boot_req_mode_i && edn_enable_i))
-3-:	66	if ((auto_req_mode_i && edn_enable_i))
-4-:	70	if (edn_enable_i)
-5-:	84	if (csrng_cmd_ack_i)
-6-:	93	if (csrng_cmd_ack_i)
-7-:	101	if ((!boot_req_mode_i))
-8-:	110	if (csrng_cmd_ack_i)
-9-:	118	if (sw_cmd_req_load_i)
-10-:	124	if (csrng_cmd_ack_i)
-11-:	130	if (csrng_cmd_ack_i)
-12-:	136	if ((!auto_req_mode_i))
-13-:	140	if (max_reqs_cnt_zero_i)
-14-:	155	if (cmd_sent_i)
-15-:	167	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T22,T23
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T7,T8
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T21,T22
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T22,T23
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T2,T22,T23
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T2,T22,T23
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T22,T23
BootGenAckWait	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T2,T22,T23
BootGenAckWait	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T2,T22,T23
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T22,T23
BootDone	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T22,T23,T14
BootDone	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T2,T24,T11
BootLoadUni	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T22,T23,T14
BootUniAckWait	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T22,T23,T14
BootUniAckWait	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T22,T23,T14
AutoLoadIns	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T3,T7,T8
AutoLoadIns	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T3,T7,T8
AutoFirstAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T3,T7,T8
AutoFirstAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T3,T7,T8
AutoAckWait	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T7,T8,T51
AutoAckWait	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T3,T7,T8
AutoDispatch	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T8,T17,T9
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T8,T20,T17
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T3,T7,T8
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T7,T8
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T3,T7,T8
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T3,T7,T8
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T20,T17
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T8,T20,T17
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T8,T20,T17
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T21,T22
RejectCsrngEntropy	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T14,T29
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T78,T79

	LineNo.	Expression
-1-:	186	if ((local_escalate_i || csrng_ack_err_i))
-2-:	188	(local_escalate_i) ? 
-3-:	188	((state_q == Error)) ? 
-4-:	201	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy})))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T3,T11,T12
1	0	1	-	Not Covered
1	0	0	-	Covered	T7,T14,T29
0	-	-	1	Covered	T2,T3,T24
0	-	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	222204135	151112	0	0
FpvSecCmErrorStEscalate_A	222204135	152287	0	0
u_state_regs_A	222166835	221980085	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	151112	0	0
T3	1260	325	0	0
T4	261769	0	0	0
T5	0	540	0	0
T6	0	594	0	0
T7	2507	0	0	0
T8	4198	0	0	0
T11	0	322	0	0
T12	0	482	0	0
T13	0	7426	0	0
T21	1994	0	0	0
T22	2035	0	0	0
T23	1620	0	0	0
T24	1151	0	0	0
T25	18033	0	0	0
T76	1958	0	0	0
T77	0	1165	0	0
T78	0	288	0	0
T79	0	1054	0	0
T80	0	201	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	152287	0	0
T3	1260	326	0	0
T4	261769	0	0	0
T5	0	541	0	0
T6	0	595	0	0
T7	2507	0	0	0
T8	4198	0	0	0
T11	0	323	0	0
T12	0	483	0	0
T13	0	7556	0	0
T21	1994	0	0	0
T22	2035	0	0	0
T23	1620	0	0	0
T24	1151	0	0	0
T25	18033	0	0	0
T76	1958	0	0	0
T77	0	1166	0	0
T78	0	289	0	0
T79	0	1055	0	0
T80	0	202	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222166835	221980085	0	0
T1	5810	5609	0	0
T2	1104	1015	0	0
T3	1025	874	0	0
T4	261769	261756	0	0
T7	2507	2420	0	0
T21	1994	1934	0	0
T22	2035	1963	0	0
T23	1620	1543	0	0
T24	1151	1062	0	0
T25	18033	17577	0	0