Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T24

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T21,T22,T23
DataWait	75	Covered	T3,T21,T22
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T3,T11,T12
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T169,T170,T183
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T21,T22,T23
DataWait->AckPls	80	Covered	T21,T22,T23
DataWait->Disabled	107	Covered	T24,T184,T185
DataWait->Error	99	Covered	T3,T12,T78
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T13,T15,T16
EndPointClear->Disabled	107	Covered	T75,T186,T187
EndPointClear->Error	99	Covered	T13,T53,T59
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T3,T21,T22
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T3,T11,T12

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T21,T22,T23
Idle	-	1	0	-	Covered	T3,T21,T22
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T21,T22,T23
DataWait	-	-	-	0	Covered	T3,T21,T22
AckPls	-	-	-	-	Covered	T21,T22,T23
Error	-	-	-	-	Covered	T3,T11,T12
default	-	-	-	-	Covered	T77,T13,T156

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T11,T12
0	1	Covered	T2,T3,T24
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	1555428945	1072984	0	0
FpvSecCmErrorStEscalate_A	1555428945	1081209	0	0
u_state_regs_A	1555391645	1554084395	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1555428945	1072984	0	0
T3	8820	2625	0	0
T4	1832383	0	0	0
T5	0	4130	0	0
T6	0	4508	0	0
T7	17549	0	0	0
T8	29386	0	0	0
T11	0	2254	0	0
T12	0	3374	0	0
T13	0	51982	0	0
T21	13958	0	0	0
T22	14245	0	0	0
T23	11340	0	0	0
T24	8057	0	0	0
T25	126231	0	0	0
T76	13706	0	0	0
T77	0	8105	0	0
T78	0	2366	0	0
T79	0	7728	0	0
T80	0	1757	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1555428945	1081209	0	0
T3	8820	2632	0	0
T4	1832383	0	0	0
T5	0	4137	0	0
T6	0	4515	0	0
T7	17549	0	0	0
T8	29386	0	0	0
T11	0	2261	0	0
T12	0	3381	0	0
T13	0	52892	0	0
T21	13958	0	0	0
T22	14245	0	0	0
T23	11340	0	0	0
T24	8057	0	0	0
T25	126231	0	0	0
T76	13706	0	0	0
T77	0	8112	0	0
T78	0	2373	0	0
T79	0	7735	0	0
T80	0	1764	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1555391645	1554084395	0	0
T1	40670	39263	0	0
T2	7728	7105	0	0
T3	8585	7528	0	0
T4	1832383	1832292	0	0
T7	17549	16940	0	0
T21	13958	13538	0	0
T22	14245	13741	0	0
T23	11340	10801	0	0
T24	8057	7434	0	0
T25	126231	123039	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T24

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T7,T39,T40
DataWait	75	Covered	T7,T39,T40
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T3,T11,T12
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T7,T39,T40
DataWait->AckPls	80	Covered	T7,T39,T40
DataWait->Disabled	107	Covered	T185,T107,T188
DataWait->Error	99	Covered	T163,T55,T56
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T13,T15,T16
EndPointClear->Disabled	107	Covered	T75,T186,T187
EndPointClear->Error	99	Covered	T13,T53,T59
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T7,T39,T40
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T3,T11,T12

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T7,T39,T40
Idle	-	1	0	-	Covered	T7,T39,T40
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T7,T39,T40
DataWait	-	-	-	0	Covered	T7,T39,T40
AckPls	-	-	-	-	Covered	T7,T39,T40
Error	-	-	-	-	Covered	T3,T11,T12
default	-	-	-	-	Covered	T13,T15,T16

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T11,T12
0	1	Covered	T2,T3,T24
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	222204135	153612	0	0
FpvSecCmErrorStEscalate_A	222204135	154787	0	0
u_state_regs_A	222204135	222017385	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	153612	0	0
T3	1260	375	0	0
T4	261769	0	0	0
T5	0	590	0	0
T6	0	644	0	0
T7	2507	0	0	0
T8	4198	0	0	0
T11	0	322	0	0
T12	0	482	0	0
T13	0	7426	0	0
T21	1994	0	0	0
T22	2035	0	0	0
T23	1620	0	0	0
T24	1151	0	0	0
T25	18033	0	0	0
T76	1958	0	0	0
T77	0	1165	0	0
T78	0	338	0	0
T79	0	1104	0	0
T80	0	251	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	154787	0	0
T3	1260	376	0	0
T4	261769	0	0	0
T5	0	591	0	0
T6	0	645	0	0
T7	2507	0	0	0
T8	4198	0	0	0
T11	0	323	0	0
T12	0	483	0	0
T13	0	7556	0	0
T21	1994	0	0	0
T22	2035	0	0	0
T23	1620	0	0	0
T24	1151	0	0	0
T25	18033	0	0	0
T76	1958	0	0	0
T77	0	1166	0	0
T78	0	339	0	0
T79	0	1105	0	0
T80	0	252	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	222017385	0	0
T1	5810	5609	0	0
T2	1104	1015	0	0
T3	1260	1109	0	0
T4	261769	261756	0	0
T7	2507	2420	0	0
T21	1994	1934	0	0
T22	2035	1963	0	0
T23	1620	1543	0	0
T24	1151	1062	0	0
T25	18033	17577	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T24

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T23,T8,T20
DataWait	75	Covered	T23,T8,T12
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T3,T11,T12
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T23,T8,T20
DataWait->AckPls	80	Covered	T23,T8,T20
DataWait->Disabled	107	Covered	T184,T189,T190
DataWait->Error	99	Covered	T12,T164,T150
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T13,T15,T16
EndPointClear->Disabled	107	Covered	T75,T186,T187
EndPointClear->Error	99	Covered	T13,T53,T59
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T23,T8,T12
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T3,T11,T77

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T23,T8,T20
Idle	-	1	0	-	Covered	T23,T8,T12
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T23,T8,T20
DataWait	-	-	-	0	Covered	T23,T8,T12
AckPls	-	-	-	-	Covered	T23,T8,T20
Error	-	-	-	-	Covered	T3,T11,T12
default	-	-	-	-	Covered	T13,T15,T16

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T11,T12
0	1	Covered	T2,T3,T24
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	222204135	153612	0	0
FpvSecCmErrorStEscalate_A	222204135	154787	0	0
u_state_regs_A	222204135	222017385	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	153612	0	0
T3	1260	375	0	0
T4	261769	0	0	0
T5	0	590	0	0
T6	0	644	0	0
T7	2507	0	0	0
T8	4198	0	0	0
T11	0	322	0	0
T12	0	482	0	0
T13	0	7426	0	0
T21	1994	0	0	0
T22	2035	0	0	0
T23	1620	0	0	0
T24	1151	0	0	0
T25	18033	0	0	0
T76	1958	0	0	0
T77	0	1165	0	0
T78	0	338	0	0
T79	0	1104	0	0
T80	0	251	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	154787	0	0
T3	1260	376	0	0
T4	261769	0	0	0
T5	0	591	0	0
T6	0	645	0	0
T7	2507	0	0	0
T8	4198	0	0	0
T11	0	323	0	0
T12	0	483	0	0
T13	0	7556	0	0
T21	1994	0	0	0
T22	2035	0	0	0
T23	1620	0	0	0
T24	1151	0	0	0
T25	18033	0	0	0
T76	1958	0	0	0
T77	0	1166	0	0
T78	0	339	0	0
T79	0	1105	0	0
T80	0	252	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	222017385	0	0
T1	5810	5609	0	0
T2	1104	1015	0	0
T3	1260	1109	0	0
T4	261769	261756	0	0
T7	2507	2420	0	0
T21	1994	1934	0	0
T22	2035	1963	0	0
T23	1620	1543	0	0
T24	1151	1062	0	0
T25	18033	17577	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T24

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T2,T41,T51
DataWait	75	Covered	T2,T11,T41
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T3,T11,T12
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T2,T41,T51
DataWait->AckPls	80	Covered	T2,T41,T51
DataWait->Disabled	107	Covered	T2,T19,T134
DataWait->Error	99	Covered	T11,T156,T152
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T13,T15,T16
EndPointClear->Disabled	107	Covered	T75,T186,T187
EndPointClear->Error	99	Covered	T13,T53,T59
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T2,T11,T41
Idle->Disabled	107	Covered	T1,T3,T4
Idle->Error	99	Covered	T3,T12,T77

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T2,T41,T51
Idle	-	1	0	-	Covered	T2,T11,T41
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T2,T41,T51
DataWait	-	-	-	0	Covered	T2,T11,T41
AckPls	-	-	-	-	Covered	T2,T41,T51
Error	-	-	-	-	Covered	T3,T11,T12
default	-	-	-	-	Covered	T13,T15,T16

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T11,T12
0	1	Covered	T2,T3,T24
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	222204135	153612	0	0
FpvSecCmErrorStEscalate_A	222204135	154787	0	0
u_state_regs_A	222204135	222017385	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	153612	0	0
T3	1260	375	0	0
T4	261769	0	0	0
T5	0	590	0	0
T6	0	644	0	0
T7	2507	0	0	0
T8	4198	0	0	0
T11	0	322	0	0
T12	0	482	0	0
T13	0	7426	0	0
T21	1994	0	0	0
T22	2035	0	0	0
T23	1620	0	0	0
T24	1151	0	0	0
T25	18033	0	0	0
T76	1958	0	0	0
T77	0	1165	0	0
T78	0	338	0	0
T79	0	1104	0	0
T80	0	251	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	154787	0	0
T3	1260	376	0	0
T4	261769	0	0	0
T5	0	591	0	0
T6	0	645	0	0
T7	2507	0	0	0
T8	4198	0	0	0
T11	0	323	0	0
T12	0	483	0	0
T13	0	7556	0	0
T21	1994	0	0	0
T22	2035	0	0	0
T23	1620	0	0	0
T24	1151	0	0	0
T25	18033	0	0	0
T76	1958	0	0	0
T77	0	1166	0	0
T78	0	339	0	0
T79	0	1105	0	0
T80	0	252	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	222017385	0	0
T1	5810	5609	0	0
T2	1104	1015	0	0
T3	1260	1109	0	0
T4	261769	261756	0	0
T7	2507	2420	0	0
T21	1994	1934	0	0
T22	2035	1963	0	0
T23	1620	1543	0	0
T24	1151	1062	0	0
T25	18033	17577	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T24

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T21,T22,T23
DataWait	75	Covered	T3,T21,T22
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T3,T11,T12
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T169,T191
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T21,T22,T23
DataWait->AckPls	80	Covered	T21,T22,T23
DataWait->Disabled	107	Covered	T192,T135,T193
DataWait->Error	99	Covered	T3,T78,T6
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T13,T15,T16
EndPointClear->Disabled	107	Covered	T75,T186,T187
EndPointClear->Error	99	Covered	T13,T53,T59
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T3,T21,T22
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T11,T12,T79

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T21,T22,T23
Idle	-	1	0	-	Covered	T3,T21,T22
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T21,T22,T23
DataWait	-	-	-	0	Covered	T3,T21,T22
AckPls	-	-	-	-	Covered	T21,T22,T23
Error	-	-	-	-	Covered	T3,T11,T12
default	-	-	-	-	Covered	T77,T13,T156

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T11,T12
0	1	Covered	T2,T3,T24
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	222204135	151312	0	0
FpvSecCmErrorStEscalate_A	222204135	152487	0	0
u_state_regs_A	222166835	221980085	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	151312	0	0
T3	1260	375	0	0
T4	261769	0	0	0
T5	0	590	0	0
T6	0	644	0	0
T7	2507	0	0	0
T8	4198	0	0	0
T11	0	322	0	0
T12	0	482	0	0
T13	0	7426	0	0
T21	1994	0	0	0
T22	2035	0	0	0
T23	1620	0	0	0
T24	1151	0	0	0
T25	18033	0	0	0
T76	1958	0	0	0
T77	0	1115	0	0
T78	0	338	0	0
T79	0	1104	0	0
T80	0	251	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	152487	0	0
T3	1260	376	0	0
T4	261769	0	0	0
T5	0	591	0	0
T6	0	645	0	0
T7	2507	0	0	0
T8	4198	0	0	0
T11	0	323	0	0
T12	0	483	0	0
T13	0	7556	0	0
T21	1994	0	0	0
T22	2035	0	0	0
T23	1620	0	0	0
T24	1151	0	0	0
T25	18033	0	0	0
T76	1958	0	0	0
T77	0	1116	0	0
T78	0	339	0	0
T79	0	1105	0	0
T80	0	252	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222166835	221980085	0	0
T1	5810	5609	0	0
T2	1104	1015	0	0
T3	1025	874	0	0
T4	261769	261756	0	0
T7	2507	2420	0	0
T21	1994	1934	0	0
T22	2035	1963	0	0
T23	1620	1543	0	0
T24	1151	1062	0	0
T25	18033	17577	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T24

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T23,T8,T40
DataWait	75	Covered	T23,T8,T40
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T3,T11,T12
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T194
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T23,T8,T40
DataWait->AckPls	80	Covered	T23,T8,T40
DataWait->Disabled	107	Covered	T195,T196,T197
DataWait->Error	99	Covered	T198,T199,T120
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T13,T15,T16
EndPointClear->Disabled	107	Covered	T75,T186,T187
EndPointClear->Error	99	Covered	T13,T53,T59
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T23,T8,T40
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T3,T11,T12

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T23,T8,T40
Idle	-	1	0	-	Covered	T23,T8,T40
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T23,T8,T40
DataWait	-	-	-	0	Covered	T23,T8,T40
AckPls	-	-	-	-	Covered	T23,T8,T40
Error	-	-	-	-	Covered	T3,T11,T12
default	-	-	-	-	Covered	T13,T15,T16

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T11,T12
0	1	Covered	T2,T3,T24
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	222204135	153612	0	0
FpvSecCmErrorStEscalate_A	222204135	154787	0	0
u_state_regs_A	222204135	222017385	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	153612	0	0
T3	1260	375	0	0
T4	261769	0	0	0
T5	0	590	0	0
T6	0	644	0	0
T7	2507	0	0	0
T8	4198	0	0	0
T11	0	322	0	0
T12	0	482	0	0
T13	0	7426	0	0
T21	1994	0	0	0
T22	2035	0	0	0
T23	1620	0	0	0
T24	1151	0	0	0
T25	18033	0	0	0
T76	1958	0	0	0
T77	0	1165	0	0
T78	0	338	0	0
T79	0	1104	0	0
T80	0	251	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	154787	0	0
T3	1260	376	0	0
T4	261769	0	0	0
T5	0	591	0	0
T6	0	645	0	0
T7	2507	0	0	0
T8	4198	0	0	0
T11	0	323	0	0
T12	0	483	0	0
T13	0	7556	0	0
T21	1994	0	0	0
T22	2035	0	0	0
T23	1620	0	0	0
T24	1151	0	0	0
T25	18033	0	0	0
T76	1958	0	0	0
T77	0	1166	0	0
T78	0	339	0	0
T79	0	1105	0	0
T80	0	252	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	222017385	0	0
T1	5810	5609	0	0
T2	1104	1015	0	0
T3	1260	1109	0	0
T4	261769	261756	0	0
T7	2507	2420	0	0
T21	1994	1934	0	0
T22	2035	1963	0	0
T23	1620	1543	0	0
T24	1151	1062	0	0
T25	18033	17577	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T24

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T24,T8,T17
DataWait	75	Covered	T24,T8,T17
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T3,T11,T12
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T170,T183
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T24,T8,T17
DataWait->AckPls	80	Covered	T24,T8,T17
DataWait->Disabled	107	Covered	T24,T200,T201
DataWait->Error	99	Covered	T122,T173
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T13,T15,T16
EndPointClear->Disabled	107	Covered	T75,T186,T187
EndPointClear->Error	99	Covered	T13,T53,T59
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T24,T8,T17
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T3,T11,T12

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T24,T8,T17
Idle	-	1	0	-	Covered	T24,T8,T17
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T24,T8,T17
DataWait	-	-	-	0	Covered	T24,T8,T17
AckPls	-	-	-	-	Covered	T24,T8,T17
Error	-	-	-	-	Covered	T3,T11,T12
default	-	-	-	-	Covered	T13,T15,T16

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T11,T12
0	1	Covered	T2,T3,T24
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	222204135	153612	0	0
FpvSecCmErrorStEscalate_A	222204135	154787	0	0
u_state_regs_A	222204135	222017385	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	153612	0	0
T3	1260	375	0	0
T4	261769	0	0	0
T5	0	590	0	0
T6	0	644	0	0
T7	2507	0	0	0
T8	4198	0	0	0
T11	0	322	0	0
T12	0	482	0	0
T13	0	7426	0	0
T21	1994	0	0	0
T22	2035	0	0	0
T23	1620	0	0	0
T24	1151	0	0	0
T25	18033	0	0	0
T76	1958	0	0	0
T77	0	1165	0	0
T78	0	338	0	0
T79	0	1104	0	0
T80	0	251	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	154787	0	0
T3	1260	376	0	0
T4	261769	0	0	0
T5	0	591	0	0
T6	0	645	0	0
T7	2507	0	0	0
T8	4198	0	0	0
T11	0	323	0	0
T12	0	483	0	0
T13	0	7556	0	0
T21	1994	0	0	0
T22	2035	0	0	0
T23	1620	0	0	0
T24	1151	0	0	0
T25	18033	0	0	0
T76	1958	0	0	0
T77	0	1166	0	0
T78	0	339	0	0
T79	0	1105	0	0
T80	0	252	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	222017385	0	0
T1	5810	5609	0	0
T2	1104	1015	0	0
T3	1260	1109	0	0
T4	261769	261756	0	0
T7	2507	2420	0	0
T21	1994	1934	0	0
T22	2035	1963	0	0
T23	1620	1543	0	0
T24	1151	1062	0	0
T25	18033	17577	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T24

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T23,T18,T19
DataWait	75	Covered	T23,T18,T19
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T3,T11,T12
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T202
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T23,T18,T19
DataWait->AckPls	80	Covered	T23,T18,T19
DataWait->Disabled	107	Covered	T94,T203
DataWait->Error	99	Covered	T5,T54,T103
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T13,T15,T16
EndPointClear->Disabled	107	Covered	T75,T186,T187
EndPointClear->Error	99	Covered	T13,T53,T59
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T23,T18,T19
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T3,T11,T12

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T23,T18,T19
Idle	-	1	0	-	Covered	T23,T18,T19
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T23,T18,T19
DataWait	-	-	-	0	Covered	T23,T18,T19
AckPls	-	-	-	-	Covered	T23,T18,T19
Error	-	-	-	-	Covered	T3,T11,T12
default	-	-	-	-	Covered	T13,T15,T16

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T11,T12
0	1	Covered	T2,T3,T24
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	222204135	153612	0	0
FpvSecCmErrorStEscalate_A	222204135	154787	0	0
u_state_regs_A	222204135	222017385	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	153612	0	0
T3	1260	375	0	0
T4	261769	0	0	0
T5	0	590	0	0
T6	0	644	0	0
T7	2507	0	0	0
T8	4198	0	0	0
T11	0	322	0	0
T12	0	482	0	0
T13	0	7426	0	0
T21	1994	0	0	0
T22	2035	0	0	0
T23	1620	0	0	0
T24	1151	0	0	0
T25	18033	0	0	0
T76	1958	0	0	0
T77	0	1165	0	0
T78	0	338	0	0
T79	0	1104	0	0
T80	0	251	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	154787	0	0
T3	1260	376	0	0
T4	261769	0	0	0
T5	0	591	0	0
T6	0	645	0	0
T7	2507	0	0	0
T8	4198	0	0	0
T11	0	323	0	0
T12	0	483	0	0
T13	0	7556	0	0
T21	1994	0	0	0
T22	2035	0	0	0
T23	1620	0	0	0
T24	1151	0	0	0
T25	18033	0	0	0
T76	1958	0	0	0
T77	0	1166	0	0
T78	0	339	0	0
T79	0	1105	0	0
T80	0	252	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	222017385	0	0
T1	5810	5609	0	0
T2	1104	1015	0	0
T3	1260	1109	0	0
T4	261769	261756	0	0
T7	2507	2420	0	0
T21	1994	1934	0	0
T22	2035	1963	0	0
T23	1620	1543	0	0
T24	1151	1062	0	0
T25	18033	17577	0	0