Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T30,T100
1	1	0	Not Covered
1	1	1	Covered	T3,T7,T8

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T34,T35,T36
1	0	1	Covered	T3,T7,T8
1	1	0	Not Covered
1	1	1	Covered	T3,T7,T8

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	443688084	1036594	0	0
DepthKnown_A	444408270	444034770	0	0
RvalidKnown_A	444408270	444034770	0	0
WreadyKnown_A	444408270	444034770	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	444038648	1129813	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443688084	1036594	0	0
T3	660	282	0	0
T4	523538	0	0	0
T7	5014	471	0	0
T8	8396	3288	0	0
T14	0	530	0	0
T20	0	602	0	0
T21	3988	0	0	0
T22	4070	0	0	0
T23	3240	0	0	0
T24	2302	0	0	0
T25	36066	0	0	0
T41	0	654	0	0
T51	0	656	0	0
T52	0	514	0	0
T61	0	1216	0	0
T76	3916	0	0	0
T101	0	1075	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444408270	444034770	0	0
T1	11620	11218	0	0
T2	2208	2030	0	0
T3	2520	2218	0	0
T4	523538	523512	0	0
T7	5014	4840	0	0
T21	3988	3868	0	0
T22	4070	3926	0	0
T23	3240	3086	0	0
T24	2302	2124	0	0
T25	36066	35154	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444408270	444034770	0	0
T1	11620	11218	0	0
T2	2208	2030	0	0
T3	2520	2218	0	0
T4	523538	523512	0	0
T7	5014	4840	0	0
T21	3988	3868	0	0
T22	4070	3926	0	0
T23	3240	3086	0	0
T24	2302	2124	0	0
T25	36066	35154	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444408270	444034770	0	0
T1	11620	11218	0	0
T2	2208	2030	0	0
T3	2520	2218	0	0
T4	523538	523512	0	0
T7	5014	4840	0	0
T21	3988	3868	0	0
T22	4070	3926	0	0
T23	3240	3086	0	0
T24	2302	2124	0	0
T25	36066	35154	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	444038648	1129813	0	0
T3	2520	1254	0	0
T4	523538	0	0	0
T7	5014	471	0	0
T8	8396	3288	0	0
T11	0	2218	0	0
T12	0	222	0	0
T14	0	530	0	0
T21	3988	0	0	0
T22	4070	0	0	0
T23	3240	0	0	0
T24	2302	0	0	0
T25	36066	0	0	0
T41	0	654	0	0
T51	0	656	0	0
T52	0	514	0	0
T61	0	1216	0	0
T76	3916	0	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T19,T93,T30
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T30
1	1	0	Not Covered
1	1	1	Covered	T3,T7,T8

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T34,T36
1	0	1	Covered	T3,T7,T8
1	1	0	Not Covered
1	1	1	Covered	T8,T20,T17

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	221844042	512091	0	0
DepthKnown_A	222204135	222017385	0	0
RvalidKnown_A	222204135	222017385	0	0
WreadyKnown_A	222204135	222017385	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	222019324	558086	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221844042	512091	0	0
T3	330	101	0	0
T4	261769	0	0	0
T7	2507	237	0	0
T8	4198	1595	0	0
T14	0	227	0	0
T20	0	303	0	0
T21	1994	0	0	0
T22	2035	0	0	0
T23	1620	0	0	0
T24	1151	0	0	0
T25	18033	0	0	0
T41	0	333	0	0
T51	0	330	0	0
T52	0	315	0	0
T61	0	595	0	0
T76	1958	0	0	0
T101	0	588	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	222017385	0	0
T1	5810	5609	0	0
T2	1104	1015	0	0
T3	1260	1109	0	0
T4	261769	261756	0	0
T7	2507	2420	0	0
T21	1994	1934	0	0
T22	2035	1963	0	0
T23	1620	1543	0	0
T24	1151	1062	0	0
T25	18033	17577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	222017385	0	0
T1	5810	5609	0	0
T2	1104	1015	0	0
T3	1260	1109	0	0
T4	261769	261756	0	0
T7	2507	2420	0	0
T21	1994	1934	0	0
T22	2035	1963	0	0
T23	1620	1543	0	0
T24	1151	1062	0	0
T25	18033	17577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	222017385	0	0
T1	5810	5609	0	0
T2	1104	1015	0	0
T3	1260	1109	0	0
T4	261769	261756	0	0
T7	2507	2420	0	0
T21	1994	1934	0	0
T22	2035	1963	0	0
T23	1620	1543	0	0
T24	1151	1062	0	0
T25	18033	17577	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	222019324	558086	0	0
T3	1260	559	0	0
T4	261769	0	0	0
T7	2507	237	0	0
T8	4198	1595	0	0
T11	0	1110	0	0
T12	0	112	0	0
T14	0	227	0	0
T21	1994	0	0	0
T22	2035	0	0	0
T23	1620	0	0	0
T24	1151	0	0	0
T25	18033	0	0	0
T41	0	333	0	0
T51	0	330	0	0
T52	0	315	0	0
T61	0	595	0	0
T76	1958	0	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T100
1	1	0	Not Covered
1	1	1	Covered	T3,T7,T8

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T35
1	0	1	Covered	T3,T7,T8
1	1	0	Not Covered
1	1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	221844042	524503	0	0
DepthKnown_A	222204135	222017385	0	0
RvalidKnown_A	222204135	222017385	0	0
WreadyKnown_A	222204135	222017385	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	222019324	571727	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221844042	524503	0	0
T3	330	181	0	0
T4	261769	0	0	0
T7	2507	234	0	0
T8	4198	1693	0	0
T14	0	303	0	0
T20	0	299	0	0
T21	1994	0	0	0
T22	2035	0	0	0
T23	1620	0	0	0
T24	1151	0	0	0
T25	18033	0	0	0
T41	0	321	0	0
T51	0	326	0	0
T52	0	199	0	0
T61	0	621	0	0
T76	1958	0	0	0
T101	0	487	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	222017385	0	0
T1	5810	5609	0	0
T2	1104	1015	0	0
T3	1260	1109	0	0
T4	261769	261756	0	0
T7	2507	2420	0	0
T21	1994	1934	0	0
T22	2035	1963	0	0
T23	1620	1543	0	0
T24	1151	1062	0	0
T25	18033	17577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	222017385	0	0
T1	5810	5609	0	0
T2	1104	1015	0	0
T3	1260	1109	0	0
T4	261769	261756	0	0
T7	2507	2420	0	0
T21	1994	1934	0	0
T22	2035	1963	0	0
T23	1620	1543	0	0
T24	1151	1062	0	0
T25	18033	17577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222204135	222017385	0	0
T1	5810	5609	0	0
T2	1104	1015	0	0
T3	1260	1109	0	0
T4	261769	261756	0	0
T7	2507	2420	0	0
T21	1994	1934	0	0
T22	2035	1963	0	0
T23	1620	1543	0	0
T24	1151	1062	0	0
T25	18033	17577	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	222019324	571727	0	0
T3	1260	695	0	0
T4	261769	0	0	0
T7	2507	234	0	0
T8	4198	1693	0	0
T11	0	1108	0	0
T12	0	110	0	0
T14	0	303	0	0
T21	1994	0	0	0
T22	2035	0	0	0
T23	1620	0	0	0
T24	1151	0	0	0
T25	18033	0	0	0
T41	0	321	0	0
T51	0	326	0	0
T52	0	199	0	0
T61	0	621	0	0
T76	1958	0	0	0