Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.65 98.25 93.97 97.02 91.86 96.37 99.77 92.28


Total test records in report: 1130
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html
T284 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.766902261 Jul 06 05:13:11 PM PDT 24 Jul 06 05:13:12 PM PDT 24 133003354 ps
T1018 /workspace/coverage/cover_reg_top/29.edn_intr_test.3649998815 Jul 06 05:13:19 PM PDT 24 Jul 06 05:13:21 PM PDT 24 170086222 ps
T1019 /workspace/coverage/cover_reg_top/6.edn_tl_errors.3422774620 Jul 06 05:13:10 PM PDT 24 Jul 06 05:13:15 PM PDT 24 476327676 ps
T1020 /workspace/coverage/cover_reg_top/39.edn_intr_test.1156884047 Jul 06 05:13:32 PM PDT 24 Jul 06 05:13:33 PM PDT 24 18882061 ps
T1021 /workspace/coverage/cover_reg_top/12.edn_tl_errors.3395875283 Jul 06 05:13:26 PM PDT 24 Jul 06 05:13:31 PM PDT 24 562439875 ps
T1022 /workspace/coverage/cover_reg_top/44.edn_intr_test.100282833 Jul 06 05:13:34 PM PDT 24 Jul 06 05:13:35 PM PDT 24 15262694 ps
T1023 /workspace/coverage/cover_reg_top/15.edn_intr_test.726019324 Jul 06 05:13:26 PM PDT 24 Jul 06 05:13:28 PM PDT 24 12101243 ps
T264 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.3140728146 Jul 06 05:13:08 PM PDT 24 Jul 06 05:13:09 PM PDT 24 189450686 ps
T1024 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.2480622008 Jul 06 05:13:15 PM PDT 24 Jul 06 05:13:17 PM PDT 24 592973229 ps
T304 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.3931279050 Jul 06 05:13:19 PM PDT 24 Jul 06 05:13:22 PM PDT 24 136577804 ps
T1025 /workspace/coverage/cover_reg_top/16.edn_intr_test.4189226617 Jul 06 05:13:13 PM PDT 24 Jul 06 05:13:14 PM PDT 24 13261887 ps
T1026 /workspace/coverage/cover_reg_top/19.edn_tl_errors.138420178 Jul 06 05:13:36 PM PDT 24 Jul 06 05:13:40 PM PDT 24 440816678 ps
T1027 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.3782784667 Jul 06 05:13:18 PM PDT 24 Jul 06 05:13:24 PM PDT 24 28508022 ps
T1028 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.2859643185 Jul 06 05:13:06 PM PDT 24 Jul 06 05:13:08 PM PDT 24 72377637 ps
T307 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.3049345410 Jul 06 05:13:06 PM PDT 24 Jul 06 05:13:09 PM PDT 24 129917545 ps
T308 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.4096247428 Jul 06 05:13:08 PM PDT 24 Jul 06 05:13:10 PM PDT 24 287210272 ps
T1029 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.352529770 Jul 06 05:13:20 PM PDT 24 Jul 06 05:13:22 PM PDT 24 20796479 ps
T1030 /workspace/coverage/cover_reg_top/18.edn_tl_errors.3934189711 Jul 06 05:13:13 PM PDT 24 Jul 06 05:13:16 PM PDT 24 59975510 ps
T1031 /workspace/coverage/cover_reg_top/6.edn_csr_rw.1458763883 Jul 06 05:13:13 PM PDT 24 Jul 06 05:13:14 PM PDT 24 17225439 ps
T1032 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.3185889513 Jul 06 05:13:20 PM PDT 24 Jul 06 05:13:23 PM PDT 24 45023306 ps
T1033 /workspace/coverage/cover_reg_top/48.edn_intr_test.3496412830 Jul 06 05:13:35 PM PDT 24 Jul 06 05:13:36 PM PDT 24 14991854 ps
T1034 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.3536843316 Jul 06 05:13:24 PM PDT 24 Jul 06 05:13:25 PM PDT 24 48117496 ps
T1035 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.794391496 Jul 06 05:13:08 PM PDT 24 Jul 06 05:13:09 PM PDT 24 24159671 ps
T265 /workspace/coverage/cover_reg_top/9.edn_csr_rw.2203062049 Jul 06 05:13:07 PM PDT 24 Jul 06 05:13:09 PM PDT 24 35617452 ps
T1036 /workspace/coverage/cover_reg_top/47.edn_intr_test.107228474 Jul 06 05:13:39 PM PDT 24 Jul 06 05:13:40 PM PDT 24 15271161 ps
T1037 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.1194180852 Jul 06 05:13:11 PM PDT 24 Jul 06 05:13:13 PM PDT 24 31911289 ps
T266 /workspace/coverage/cover_reg_top/15.edn_csr_rw.4024247621 Jul 06 05:13:31 PM PDT 24 Jul 06 05:13:32 PM PDT 24 16172672 ps
T1038 /workspace/coverage/cover_reg_top/34.edn_intr_test.1162342235 Jul 06 05:13:40 PM PDT 24 Jul 06 05:13:42 PM PDT 24 14019803 ps
T267 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.2604746945 Jul 06 05:13:18 PM PDT 24 Jul 06 05:13:20 PM PDT 24 29983418 ps
T305 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.1043820490 Jul 06 05:13:10 PM PDT 24 Jul 06 05:13:14 PM PDT 24 330077980 ps
T1039 /workspace/coverage/cover_reg_top/31.edn_intr_test.2990293393 Jul 06 05:13:31 PM PDT 24 Jul 06 05:13:32 PM PDT 24 42322136 ps
T1040 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2832442012 Jul 06 05:13:10 PM PDT 24 Jul 06 05:13:12 PM PDT 24 25428356 ps
T1041 /workspace/coverage/cover_reg_top/41.edn_intr_test.2229843835 Jul 06 05:13:40 PM PDT 24 Jul 06 05:13:41 PM PDT 24 13851339 ps
T1042 /workspace/coverage/cover_reg_top/27.edn_intr_test.623044913 Jul 06 05:13:20 PM PDT 24 Jul 06 05:13:22 PM PDT 24 12289181 ps
T1043 /workspace/coverage/cover_reg_top/0.edn_intr_test.1366420728 Jul 06 05:13:05 PM PDT 24 Jul 06 05:13:07 PM PDT 24 59652116 ps
T1044 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.1862902972 Jul 06 05:13:18 PM PDT 24 Jul 06 05:13:22 PM PDT 24 137756398 ps
T1045 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.2908876699 Jul 06 05:13:06 PM PDT 24 Jul 06 05:13:08 PM PDT 24 40496904 ps
T1046 /workspace/coverage/cover_reg_top/35.edn_intr_test.1610771994 Jul 06 05:13:45 PM PDT 24 Jul 06 05:13:46 PM PDT 24 15190682 ps
T1047 /workspace/coverage/cover_reg_top/13.edn_tl_errors.3784801754 Jul 06 05:13:27 PM PDT 24 Jul 06 05:13:30 PM PDT 24 73010364 ps
T1048 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.3846326759 Jul 06 05:13:19 PM PDT 24 Jul 06 05:13:23 PM PDT 24 133741931 ps
T1049 /workspace/coverage/cover_reg_top/5.edn_tl_errors.2579519651 Jul 06 05:13:08 PM PDT 24 Jul 06 05:13:10 PM PDT 24 38927351 ps
T1050 /workspace/coverage/cover_reg_top/46.edn_intr_test.1132179164 Jul 06 05:13:36 PM PDT 24 Jul 06 05:13:38 PM PDT 24 13981836 ps
T1051 /workspace/coverage/cover_reg_top/15.edn_tl_errors.494275853 Jul 06 05:13:12 PM PDT 24 Jul 06 05:13:15 PM PDT 24 70498519 ps
T1052 /workspace/coverage/cover_reg_top/23.edn_intr_test.3451069205 Jul 06 05:13:19 PM PDT 24 Jul 06 05:13:21 PM PDT 24 10878300 ps
T1053 /workspace/coverage/cover_reg_top/4.edn_csr_rw.3706868216 Jul 06 05:13:10 PM PDT 24 Jul 06 05:13:11 PM PDT 24 22134951 ps
T1054 /workspace/coverage/cover_reg_top/17.edn_csr_rw.2832261508 Jul 06 05:13:32 PM PDT 24 Jul 06 05:13:33 PM PDT 24 15026342 ps
T1055 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.3565319234 Jul 06 05:13:11 PM PDT 24 Jul 06 05:13:12 PM PDT 24 76132556 ps
T268 /workspace/coverage/cover_reg_top/10.edn_csr_rw.2909318893 Jul 06 05:13:15 PM PDT 24 Jul 06 05:13:16 PM PDT 24 47659450 ps
T1056 /workspace/coverage/cover_reg_top/4.edn_tl_errors.1716410639 Jul 06 05:13:18 PM PDT 24 Jul 06 05:13:22 PM PDT 24 137813284 ps
T1057 /workspace/coverage/cover_reg_top/2.edn_intr_test.158283581 Jul 06 05:13:10 PM PDT 24 Jul 06 05:13:12 PM PDT 24 12715854 ps
T269 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.642633986 Jul 06 05:13:10 PM PDT 24 Jul 06 05:13:12 PM PDT 24 33231783 ps
T1058 /workspace/coverage/cover_reg_top/0.edn_tl_errors.2499212689 Jul 06 05:13:07 PM PDT 24 Jul 06 05:13:11 PM PDT 24 160801699 ps
T1059 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.228786524 Jul 06 05:13:18 PM PDT 24 Jul 06 05:13:22 PM PDT 24 123358045 ps
T1060 /workspace/coverage/cover_reg_top/9.edn_tl_errors.2350382171 Jul 06 05:13:09 PM PDT 24 Jul 06 05:13:12 PM PDT 24 45169561 ps
T1061 /workspace/coverage/cover_reg_top/9.edn_intr_test.797240051 Jul 06 05:13:20 PM PDT 24 Jul 06 05:13:22 PM PDT 24 26485625 ps
T1062 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.768098974 Jul 06 05:13:20 PM PDT 24 Jul 06 05:13:23 PM PDT 24 167068653 ps
T1063 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.1938900160 Jul 06 05:13:06 PM PDT 24 Jul 06 05:13:07 PM PDT 24 64523316 ps
T1064 /workspace/coverage/cover_reg_top/40.edn_intr_test.1292937350 Jul 06 05:13:43 PM PDT 24 Jul 06 05:13:50 PM PDT 24 12628915 ps
T272 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.3530716743 Jul 06 05:13:13 PM PDT 24 Jul 06 05:13:17 PM PDT 24 58732137 ps
T1065 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.1986863814 Jul 06 05:13:30 PM PDT 24 Jul 06 05:13:31 PM PDT 24 39760883 ps
T1066 /workspace/coverage/cover_reg_top/11.edn_tl_errors.3523640893 Jul 06 05:13:12 PM PDT 24 Jul 06 05:13:14 PM PDT 24 25749807 ps
T1067 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3602089471 Jul 06 05:13:09 PM PDT 24 Jul 06 05:13:10 PM PDT 24 73766341 ps
T1068 /workspace/coverage/cover_reg_top/1.edn_csr_rw.1456041509 Jul 06 05:13:18 PM PDT 24 Jul 06 05:13:20 PM PDT 24 33474448 ps
T1069 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.1060509287 Jul 06 05:13:18 PM PDT 24 Jul 06 05:13:20 PM PDT 24 25007526 ps
T270 /workspace/coverage/cover_reg_top/18.edn_csr_rw.2398213223 Jul 06 05:13:37 PM PDT 24 Jul 06 05:13:38 PM PDT 24 164572553 ps
T1070 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.1768268383 Jul 06 05:13:19 PM PDT 24 Jul 06 05:13:21 PM PDT 24 232573457 ps
T1071 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.1206019438 Jul 06 05:13:07 PM PDT 24 Jul 06 05:13:08 PM PDT 24 26195563 ps
T1072 /workspace/coverage/cover_reg_top/10.edn_tl_errors.1466720488 Jul 06 05:13:09 PM PDT 24 Jul 06 05:13:12 PM PDT 24 66148981 ps
T1073 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.2812899793 Jul 06 05:13:18 PM PDT 24 Jul 06 05:13:20 PM PDT 24 47742909 ps
T1074 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.2425748014 Jul 06 05:13:12 PM PDT 24 Jul 06 05:13:14 PM PDT 24 46522482 ps
T1075 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.4113812983 Jul 06 05:13:10 PM PDT 24 Jul 06 05:13:12 PM PDT 24 94578097 ps
T1076 /workspace/coverage/cover_reg_top/19.edn_intr_test.2402286278 Jul 06 05:13:24 PM PDT 24 Jul 06 05:13:25 PM PDT 24 57454746 ps
T1077 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.3954331891 Jul 06 05:13:13 PM PDT 24 Jul 06 05:13:15 PM PDT 24 321256604 ps
T1078 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.1337069597 Jul 06 05:13:22 PM PDT 24 Jul 06 05:13:24 PM PDT 24 177615331 ps
T271 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.2450130381 Jul 06 05:13:04 PM PDT 24 Jul 06 05:13:06 PM PDT 24 61965541 ps
T1079 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.966286459 Jul 06 05:13:38 PM PDT 24 Jul 06 05:13:39 PM PDT 24 109094048 ps
T1080 /workspace/coverage/cover_reg_top/13.edn_intr_test.4146180295 Jul 06 05:13:20 PM PDT 24 Jul 06 05:13:22 PM PDT 24 42542740 ps
T1081 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.1396472955 Jul 06 05:13:14 PM PDT 24 Jul 06 05:13:16 PM PDT 24 22710183 ps
T1082 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.1463864625 Jul 06 05:13:37 PM PDT 24 Jul 06 05:13:38 PM PDT 24 57779855 ps
T1083 /workspace/coverage/cover_reg_top/16.edn_tl_errors.3585307341 Jul 06 05:13:16 PM PDT 24 Jul 06 05:13:18 PM PDT 24 229656270 ps
T1084 /workspace/coverage/cover_reg_top/30.edn_intr_test.2895810387 Jul 06 05:13:21 PM PDT 24 Jul 06 05:13:22 PM PDT 24 110651951 ps
T1085 /workspace/coverage/cover_reg_top/28.edn_intr_test.398855387 Jul 06 05:13:26 PM PDT 24 Jul 06 05:13:27 PM PDT 24 20410206 ps
T1086 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.2628592641 Jul 06 05:13:17 PM PDT 24 Jul 06 05:13:19 PM PDT 24 18636500 ps
T1087 /workspace/coverage/cover_reg_top/2.edn_csr_rw.930484976 Jul 06 05:13:08 PM PDT 24 Jul 06 05:13:09 PM PDT 24 22262037 ps
T1088 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.3112583151 Jul 06 05:13:29 PM PDT 24 Jul 06 05:13:31 PM PDT 24 80935078 ps
T1089 /workspace/coverage/cover_reg_top/8.edn_tl_errors.2783260654 Jul 06 05:13:12 PM PDT 24 Jul 06 05:13:14 PM PDT 24 24963004 ps
T273 /workspace/coverage/cover_reg_top/19.edn_csr_rw.3533637616 Jul 06 05:13:17 PM PDT 24 Jul 06 05:13:19 PM PDT 24 14426449 ps
T1090 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.2804128659 Jul 06 05:13:06 PM PDT 24 Jul 06 05:13:08 PM PDT 24 49697171 ps
T1091 /workspace/coverage/cover_reg_top/36.edn_intr_test.3725457220 Jul 06 05:13:30 PM PDT 24 Jul 06 05:13:31 PM PDT 24 14192806 ps
T1092 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1735299772 Jul 06 05:13:17 PM PDT 24 Jul 06 05:13:19 PM PDT 24 175370769 ps
T1093 /workspace/coverage/cover_reg_top/38.edn_intr_test.1103406948 Jul 06 05:13:38 PM PDT 24 Jul 06 05:13:39 PM PDT 24 19393841 ps
T1094 /workspace/coverage/cover_reg_top/1.edn_intr_test.1391045561 Jul 06 05:13:06 PM PDT 24 Jul 06 05:13:07 PM PDT 24 25098209 ps
T1095 /workspace/coverage/cover_reg_top/42.edn_intr_test.4151294372 Jul 06 05:13:42 PM PDT 24 Jul 06 05:13:43 PM PDT 24 20338868 ps
T1096 /workspace/coverage/cover_reg_top/45.edn_intr_test.3640307291 Jul 06 05:13:40 PM PDT 24 Jul 06 05:13:41 PM PDT 24 14974540 ps
T1097 /workspace/coverage/cover_reg_top/3.edn_intr_test.3133126161 Jul 06 05:13:06 PM PDT 24 Jul 06 05:13:07 PM PDT 24 109436565 ps
T1098 /workspace/coverage/cover_reg_top/22.edn_intr_test.3763656416 Jul 06 05:13:42 PM PDT 24 Jul 06 05:13:43 PM PDT 24 39696737 ps
T1099 /workspace/coverage/cover_reg_top/25.edn_intr_test.4155424261 Jul 06 05:13:35 PM PDT 24 Jul 06 05:13:36 PM PDT 24 29256497 ps
T1100 /workspace/coverage/cover_reg_top/7.edn_tl_errors.2984634354 Jul 06 05:13:12 PM PDT 24 Jul 06 05:13:15 PM PDT 24 91127525 ps
T1101 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.2667371157 Jul 06 05:13:11 PM PDT 24 Jul 06 05:13:12 PM PDT 24 14859977 ps
T1102 /workspace/coverage/cover_reg_top/0.edn_csr_rw.3686337279 Jul 06 05:13:04 PM PDT 24 Jul 06 05:13:05 PM PDT 24 31513508 ps
T1103 /workspace/coverage/cover_reg_top/32.edn_intr_test.1796045359 Jul 06 05:13:37 PM PDT 24 Jul 06 05:13:38 PM PDT 24 13668539 ps
T1104 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.3727407169 Jul 06 05:13:11 PM PDT 24 Jul 06 05:13:13 PM PDT 24 38266066 ps
T1105 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.2991674863 Jul 06 05:13:07 PM PDT 24 Jul 06 05:13:09 PM PDT 24 235419832 ps
T1106 /workspace/coverage/cover_reg_top/6.edn_intr_test.3759539762 Jul 06 05:13:12 PM PDT 24 Jul 06 05:13:19 PM PDT 24 70552284 ps
T1107 /workspace/coverage/cover_reg_top/12.edn_intr_test.1204614216 Jul 06 05:13:17 PM PDT 24 Jul 06 05:13:18 PM PDT 24 16841090 ps
T1108 /workspace/coverage/cover_reg_top/43.edn_intr_test.263953161 Jul 06 05:13:47 PM PDT 24 Jul 06 05:13:48 PM PDT 24 15192332 ps
T1109 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.2888497707 Jul 06 05:13:20 PM PDT 24 Jul 06 05:13:24 PM PDT 24 121481571 ps
T1110 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.4016553762 Jul 06 05:13:21 PM PDT 24 Jul 06 05:13:23 PM PDT 24 302103609 ps
T1111 /workspace/coverage/cover_reg_top/18.edn_intr_test.1072337521 Jul 06 05:13:32 PM PDT 24 Jul 06 05:13:33 PM PDT 24 32958558 ps
T1112 /workspace/coverage/cover_reg_top/49.edn_intr_test.196686816 Jul 06 05:13:40 PM PDT 24 Jul 06 05:13:41 PM PDT 24 88280254 ps
T1113 /workspace/coverage/cover_reg_top/7.edn_intr_test.3292650959 Jul 06 05:13:19 PM PDT 24 Jul 06 05:13:21 PM PDT 24 45992241 ps
T1114 /workspace/coverage/cover_reg_top/12.edn_csr_rw.4132426375 Jul 06 05:13:17 PM PDT 24 Jul 06 05:13:18 PM PDT 24 26772569 ps
T1115 /workspace/coverage/cover_reg_top/17.edn_intr_test.995640301 Jul 06 05:13:14 PM PDT 24 Jul 06 05:13:15 PM PDT 24 24201415 ps
T1116 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.844470313 Jul 06 05:13:31 PM PDT 24 Jul 06 05:13:33 PM PDT 24 90339386 ps
T1117 /workspace/coverage/cover_reg_top/8.edn_intr_test.3019194323 Jul 06 05:13:16 PM PDT 24 Jul 06 05:13:17 PM PDT 24 10914778 ps
T274 /workspace/coverage/cover_reg_top/8.edn_csr_rw.1775677657 Jul 06 05:13:10 PM PDT 24 Jul 06 05:13:11 PM PDT 24 19979657 ps
T1118 /workspace/coverage/cover_reg_top/2.edn_tl_errors.1727014372 Jul 06 05:13:08 PM PDT 24 Jul 06 05:13:10 PM PDT 24 102393820 ps
T1119 /workspace/coverage/cover_reg_top/11.edn_intr_test.927341632 Jul 06 05:13:07 PM PDT 24 Jul 06 05:13:08 PM PDT 24 49241754 ps
T1120 /workspace/coverage/cover_reg_top/5.edn_intr_test.150107926 Jul 06 05:13:05 PM PDT 24 Jul 06 05:13:07 PM PDT 24 15114448 ps
T1121 /workspace/coverage/cover_reg_top/33.edn_intr_test.4115022911 Jul 06 05:13:29 PM PDT 24 Jul 06 05:13:30 PM PDT 24 15252581 ps
T306 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.3153715823 Jul 06 05:13:17 PM PDT 24 Jul 06 05:13:20 PM PDT 24 288093805 ps
T1122 /workspace/coverage/cover_reg_top/37.edn_intr_test.2070188347 Jul 06 05:13:24 PM PDT 24 Jul 06 05:13:25 PM PDT 24 21190479 ps
T1123 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.3121331211 Jul 06 05:13:14 PM PDT 24 Jul 06 05:13:17 PM PDT 24 31918140 ps
T1124 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.3389654426 Jul 06 05:13:26 PM PDT 24 Jul 06 05:13:28 PM PDT 24 19905499 ps
T1125 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.2465621500 Jul 06 05:13:09 PM PDT 24 Jul 06 05:13:11 PM PDT 24 74511577 ps
T1126 /workspace/coverage/cover_reg_top/4.edn_intr_test.2963978358 Jul 06 05:13:06 PM PDT 24 Jul 06 05:13:07 PM PDT 24 22404607 ps
T1127 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.2936531577 Jul 06 05:13:13 PM PDT 24 Jul 06 05:13:15 PM PDT 24 255344610 ps
T1128 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.514979878 Jul 06 05:13:26 PM PDT 24 Jul 06 05:13:28 PM PDT 24 273718310 ps
T1129 /workspace/coverage/cover_reg_top/10.edn_intr_test.1234929401 Jul 06 05:13:19 PM PDT 24 Jul 06 05:13:21 PM PDT 24 19823805 ps
T1130 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1322890586 Jul 06 05:13:18 PM PDT 24 Jul 06 05:13:20 PM PDT 24 29426589 ps

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.2519850954
Short name T3
Test name
Test status
Simulation time 24317487848 ps
CPU time 444.51 seconds
Started Jul 06 06:27:27 PM PDT 24
Finished Jul 06 06:34:53 PM PDT 24
Peak memory 219560 kb
Host smart-ec7f0b85-3b96-43c8-aff6-57f668ad96d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519850954 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.2519850954
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/129.edn_genbits.1764503501
Short name T10
Test name
Test status
Simulation time 87957292 ps
CPU time 1.19 seconds
Started Jul 06 06:28:44 PM PDT 24
Finished Jul 06 06:28:46 PM PDT 24
Peak memory 220356 kb
Host smart-b3db647a-0ad3-46e8-a1e3-e85c903ad23f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764503501 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.1764503501
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_alert.1518716791
Short name T21
Test name
Test status
Simulation time 72849349 ps
CPU time 1.17 seconds
Started Jul 06 06:28:41 PM PDT 24
Finished Jul 06 06:28:42 PM PDT 24
Peak memory 222040 kb
Host smart-3afbfdd7-c383-4aa7-8a7d-c9c5703ac70b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518716791 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_alert.1518716791
Directory /workspace/105.edn_alert/latest

Test location /workspace/coverage/default/3.edn_sec_cm.1244947708
Short name T17
Test name
Test status
Simulation time 508672131 ps
CPU time 4.63 seconds
Started Jul 06 06:27:01 PM PDT 24
Finished Jul 06 06:27:06 PM PDT 24
Peak memory 235876 kb
Host smart-662447e1-799d-421a-9952-adf0512485e1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244947708 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.1244947708
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/81.edn_err.1396359084
Short name T41
Test name
Test status
Simulation time 37452204 ps
CPU time 0.82 seconds
Started Jul 06 06:28:31 PM PDT 24
Finished Jul 06 06:28:32 PM PDT 24
Peak memory 218744 kb
Host smart-99c2c749-748f-494b-aebc-e3decc14e4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396359084 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.1396359084
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/65.edn_alert.895223147
Short name T101
Test name
Test status
Simulation time 55591359 ps
CPU time 1.35 seconds
Started Jul 06 06:28:20 PM PDT 24
Finished Jul 06 06:28:22 PM PDT 24
Peak memory 216052 kb
Host smart-85e7c6c0-3b01-499d-b38c-cfa33d88ae7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895223147 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_alert.895223147
Directory /workspace/65.edn_alert/latest

Test location /workspace/coverage/default/7.edn_disable.525040508
Short name T90
Test name
Test status
Simulation time 51567834 ps
CPU time 0.9 seconds
Started Jul 06 06:27:03 PM PDT 24
Finished Jul 06 06:27:05 PM PDT 24
Peak memory 216620 kb
Host smart-2689a348-49a3-46c0-9615-ba7dae56279b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525040508 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.525040508
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/138.edn_alert.698670465
Short name T52
Test name
Test status
Simulation time 33107793 ps
CPU time 1.43 seconds
Started Jul 06 06:28:46 PM PDT 24
Finished Jul 06 06:28:48 PM PDT 24
Peak memory 216028 kb
Host smart-c4230bbe-27f5-42b6-af22-34e4a75c753c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698670465 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_alert.698670465
Directory /workspace/138.edn_alert/latest

Test location /workspace/coverage/default/196.edn_alert.2483809850
Short name T62
Test name
Test status
Simulation time 254312361 ps
CPU time 1.21 seconds
Started Jul 06 06:29:07 PM PDT 24
Finished Jul 06 06:29:09 PM PDT 24
Peak memory 220108 kb
Host smart-edcd8b13-7dc6-443e-81fc-0e84cdfd5c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483809850 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_alert.2483809850
Directory /workspace/196.edn_alert/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.3881536809
Short name T148
Test name
Test status
Simulation time 33516443 ps
CPU time 1.21 seconds
Started Jul 06 06:28:12 PM PDT 24
Finished Jul 06 06:28:14 PM PDT 24
Peak memory 217072 kb
Host smart-281a3ad7-67a5-4ecd-ad78-d93896644072
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881536809 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.3881536809
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.2205534126
Short name T231
Test name
Test status
Simulation time 34605312606 ps
CPU time 771.24 seconds
Started Jul 06 06:26:51 PM PDT 24
Finished Jul 06 06:39:43 PM PDT 24
Peak memory 218308 kb
Host smart-9946320f-8b7d-4eda-9d3d-9a5193377952
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205534126 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.2205534126
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.edn_alert.217010258
Short name T100
Test name
Test status
Simulation time 51190721 ps
CPU time 1.19 seconds
Started Jul 06 06:28:30 PM PDT 24
Finished Jul 06 06:28:31 PM PDT 24
Peak memory 219852 kb
Host smart-ac8f9ddd-b85e-4e7f-8b50-8eb011fedd47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217010258 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_alert.217010258
Directory /workspace/81.edn_alert/latest

Test location /workspace/coverage/default/1.edn_regwen.1812708190
Short name T248
Test name
Test status
Simulation time 52629751 ps
CPU time 0.88 seconds
Started Jul 06 06:26:50 PM PDT 24
Finished Jul 06 06:26:51 PM PDT 24
Peak memory 207428 kb
Host smart-ab6445f6-179b-4c7f-894f-efcf6a6719d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812708190 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.1812708190
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.3931279050
Short name T304
Test name
Test status
Simulation time 136577804 ps
CPU time 2.43 seconds
Started Jul 06 05:13:19 PM PDT 24
Finished Jul 06 05:13:22 PM PDT 24
Peak memory 215040 kb
Host smart-469c337a-c4fe-420f-b5af-e996f3c8fcfe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931279050 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.3931279050
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/38.edn_disable.3267659780
Short name T54
Test name
Test status
Simulation time 22157509 ps
CPU time 0.85 seconds
Started Jul 06 06:27:53 PM PDT 24
Finished Jul 06 06:27:55 PM PDT 24
Peak memory 216656 kb
Host smart-673d97fd-a540-408f-828b-35d1e74d1345
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267659780 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.3267659780
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/77.edn_alert.3858203782
Short name T294
Test name
Test status
Simulation time 96388260 ps
CPU time 1.24 seconds
Started Jul 06 06:28:27 PM PDT 24
Finished Jul 06 06:28:29 PM PDT 24
Peak memory 220416 kb
Host smart-32e6c667-9e90-447d-9f83-3659468b6616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858203782 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_alert.3858203782
Directory /workspace/77.edn_alert/latest

Test location /workspace/coverage/default/90.edn_err.3328672303
Short name T164
Test name
Test status
Simulation time 173790107 ps
CPU time 1.02 seconds
Started Jul 06 06:28:35 PM PDT 24
Finished Jul 06 06:28:36 PM PDT 24
Peak memory 220064 kb
Host smart-c3bf83eb-0583-4f52-b6f4-20f745a71098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328672303 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.3328672303
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.3538435117
Short name T301
Test name
Test status
Simulation time 173244684 ps
CPU time 2.09 seconds
Started Jul 06 06:27:24 PM PDT 24
Finished Jul 06 06:27:27 PM PDT 24
Peak memory 220436 kb
Host smart-bc1c714a-dbe3-419c-b94f-9746274f2d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538435117 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.3538435117
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_disable.3408500099
Short name T194
Test name
Test status
Simulation time 38413075 ps
CPU time 0.84 seconds
Started Jul 06 06:27:09 PM PDT 24
Finished Jul 06 06:27:11 PM PDT 24
Peak memory 216672 kb
Host smart-78ca9c32-327f-456d-a88e-d4b5239309f8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408500099 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.3408500099
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.3580672865
Short name T204
Test name
Test status
Simulation time 89726214 ps
CPU time 1.18 seconds
Started Jul 06 06:27:22 PM PDT 24
Finished Jul 06 06:27:23 PM PDT 24
Peak memory 217128 kb
Host smart-f40b3136-cafa-4baa-9c5b-392bcb63b38a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580672865 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.3580672865
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.1281439004
Short name T263
Test name
Test status
Simulation time 16516569 ps
CPU time 0.9 seconds
Started Jul 06 05:13:15 PM PDT 24
Finished Jul 06 05:13:16 PM PDT 24
Peak memory 206904 kb
Host smart-f8c4a501-b37d-4897-8ae1-e409bf08e3d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281439004 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.1281439004
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/default/22.edn_alert.3526139568
Short name T299
Test name
Test status
Simulation time 48398120 ps
CPU time 1.2 seconds
Started Jul 06 06:27:27 PM PDT 24
Finished Jul 06 06:27:29 PM PDT 24
Peak memory 219516 kb
Host smart-9a94bf81-fc0a-49d1-9a06-344e72461501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526139568 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.3526139568
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert.647989035
Short name T91
Test name
Test status
Simulation time 65060301 ps
CPU time 1.11 seconds
Started Jul 06 06:27:01 PM PDT 24
Finished Jul 06 06:27:03 PM PDT 24
Peak memory 220056 kb
Host smart-988f22b1-62bf-4338-adea-381216b6e401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647989035 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.647989035
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert.4107382270
Short name T577
Test name
Test status
Simulation time 23193566 ps
CPU time 1.22 seconds
Started Jul 06 06:27:21 PM PDT 24
Finished Jul 06 06:27:23 PM PDT 24
Peak memory 219088 kb
Host smart-da12bf15-a594-41fe-8842-d4dc19264f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107382270 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.4107382270
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/1.edn_intr.1541266725
Short name T43
Test name
Test status
Simulation time 25606984 ps
CPU time 1.15 seconds
Started Jul 06 06:26:48 PM PDT 24
Finished Jul 06 06:26:49 PM PDT 24
Peak memory 216260 kb
Host smart-77d26929-7885-44e0-8c33-044665e531ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541266725 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.1541266725
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.4152541813
Short name T154
Test name
Test status
Simulation time 39706281 ps
CPU time 1.31 seconds
Started Jul 06 06:27:27 PM PDT 24
Finished Jul 06 06:27:29 PM PDT 24
Peak memory 217324 kb
Host smart-be8a4a20-2999-428a-a419-ff3280bdb462
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152541813 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.4152541813
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/146.edn_genbits.3375839749
Short name T320
Test name
Test status
Simulation time 43494704 ps
CPU time 1.19 seconds
Started Jul 06 06:28:56 PM PDT 24
Finished Jul 06 06:28:58 PM PDT 24
Peak memory 218900 kb
Host smart-c57f5c0a-f949-4137-882b-189e3094a7b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375839749 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.3375839749
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_genbits.2328340767
Short name T326
Test name
Test status
Simulation time 276726947 ps
CPU time 4.08 seconds
Started Jul 06 06:28:27 PM PDT 24
Finished Jul 06 06:28:32 PM PDT 24
Peak memory 219728 kb
Host smart-6a76afc3-dad3-4df5-a5eb-75d2409551c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328340767 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.2328340767
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_alert.1746556827
Short name T782
Test name
Test status
Simulation time 240663195 ps
CPU time 1.19 seconds
Started Jul 06 06:29:04 PM PDT 24
Finished Jul 06 06:29:06 PM PDT 24
Peak memory 220060 kb
Host smart-d747f3d9-e645-471b-8842-17f53cef83b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746556827 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_alert.1746556827
Directory /workspace/189.edn_alert/latest

Test location /workspace/coverage/default/160.edn_alert.4204910697
Short name T2
Test name
Test status
Simulation time 84274796 ps
CPU time 1.1 seconds
Started Jul 06 06:28:58 PM PDT 24
Finished Jul 06 06:29:00 PM PDT 24
Peak memory 218768 kb
Host smart-21c5f7e8-645f-4ace-bbde-ca2d3e4b85af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204910697 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_alert.4204910697
Directory /workspace/160.edn_alert/latest

Test location /workspace/coverage/default/180.edn_alert.2328682393
Short name T593
Test name
Test status
Simulation time 39019407 ps
CPU time 1.26 seconds
Started Jul 06 06:29:11 PM PDT 24
Finished Jul 06 06:29:13 PM PDT 24
Peak memory 219864 kb
Host smart-2e46dcb0-1819-4381-b0b4-e2c3b6e4d70b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328682393 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_alert.2328682393
Directory /workspace/180.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert.880404632
Short name T183
Test name
Test status
Simulation time 50905303 ps
CPU time 1.15 seconds
Started Jul 06 06:27:42 PM PDT 24
Finished Jul 06 06:27:44 PM PDT 24
Peak memory 221336 kb
Host smart-be8e86b4-b0e0-4a83-a3ff-a1658445d628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880404632 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.880404632
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.1044897160
Short name T23
Test name
Test status
Simulation time 39518419 ps
CPU time 1.31 seconds
Started Jul 06 06:28:00 PM PDT 24
Finished Jul 06 06:28:02 PM PDT 24
Peak memory 220024 kb
Host smart-dc160cdb-3632-4fe8-9a06-996a72a42886
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044897160 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.1044897160
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.524229293
Short name T65
Test name
Test status
Simulation time 23520566 ps
CPU time 1.06 seconds
Started Jul 06 06:27:12 PM PDT 24
Finished Jul 06 06:27:13 PM PDT 24
Peak memory 229804 kb
Host smart-2458cac5-85fb-4a34-ba3c-94d2a934c8cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524229293 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.524229293
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/93.edn_alert.1072929991
Short name T133
Test name
Test status
Simulation time 84269963 ps
CPU time 1.22 seconds
Started Jul 06 06:28:32 PM PDT 24
Finished Jul 06 06:28:34 PM PDT 24
Peak memory 219792 kb
Host smart-3b22afd2-21b1-4802-9b56-6a24dc469762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072929991 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_alert.1072929991
Directory /workspace/93.edn_alert/latest

Test location /workspace/coverage/default/231.edn_genbits.3484520023
Short name T324
Test name
Test status
Simulation time 62466225 ps
CPU time 1.46 seconds
Started Jul 06 06:29:27 PM PDT 24
Finished Jul 06 06:29:28 PM PDT 24
Peak memory 218776 kb
Host smart-e1d1d372-a0f1-4a1b-ba52-8b7a5711b0a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484520023 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.3484520023
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.2641846348
Short name T35
Test name
Test status
Simulation time 20857601 ps
CPU time 1.11 seconds
Started Jul 06 06:27:53 PM PDT 24
Finished Jul 06 06:27:54 PM PDT 24
Peak memory 216288 kb
Host smart-4d9411ef-4243-4772-a387-4cc2a174c36c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641846348 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.2641846348
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/20.edn_disable.3771558126
Short name T160
Test name
Test status
Simulation time 60914973 ps
CPU time 0.88 seconds
Started Jul 06 06:27:26 PM PDT 24
Finished Jul 06 06:27:27 PM PDT 24
Peak memory 215656 kb
Host smart-cdf64ef4-bc67-4a06-82dc-3116e0dd2d4f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771558126 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.3771558126
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/10.edn_alert_test.2771200056
Short name T83
Test name
Test status
Simulation time 37105347 ps
CPU time 0.88 seconds
Started Jul 06 06:27:13 PM PDT 24
Finished Jul 06 06:27:14 PM PDT 24
Peak memory 215236 kb
Host smart-a2986441-f62e-4b79-8cb1-48be46a370b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771200056 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.2771200056
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_alert.4266814795
Short name T435
Test name
Test status
Simulation time 27134860 ps
CPU time 1.25 seconds
Started Jul 06 06:26:48 PM PDT 24
Finished Jul 06 06:26:50 PM PDT 24
Peak memory 221180 kb
Host smart-9f7d1e27-e76f-42b5-837e-191513cbde00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266814795 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.4266814795
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.643755942
Short name T128
Test name
Test status
Simulation time 210471931 ps
CPU time 1.2 seconds
Started Jul 06 06:27:11 PM PDT 24
Finished Jul 06 06:27:13 PM PDT 24
Peak memory 220212 kb
Host smart-fa8cafb2-540b-4a71-a70a-c660f34c5a8d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643755942 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_di
sable_auto_req_mode.643755942
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_disable.3047206400
Short name T186
Test name
Test status
Simulation time 123620575 ps
CPU time 0.92 seconds
Started Jul 06 06:27:11 PM PDT 24
Finished Jul 06 06:27:13 PM PDT 24
Peak memory 216576 kb
Host smart-31196210-fe33-48f6-bc42-d04a214b51b7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047206400 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.3047206400
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/12.edn_alert.1284798669
Short name T86
Test name
Test status
Simulation time 70064560 ps
CPU time 1.01 seconds
Started Jul 06 06:27:16 PM PDT 24
Finished Jul 06 06:27:17 PM PDT 24
Peak memory 220132 kb
Host smart-89a748db-6e27-4f5c-8b8c-cc52461f0562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284798669 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.1284798669
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.1444295289
Short name T135
Test name
Test status
Simulation time 61149681 ps
CPU time 1.12 seconds
Started Jul 06 06:27:17 PM PDT 24
Finished Jul 06 06:27:19 PM PDT 24
Peak memory 218632 kb
Host smart-74e4c431-8ffb-444d-9ac6-8d4e5377314c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444295289 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.1444295289
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.2898932319
Short name T201
Test name
Test status
Simulation time 99233189 ps
CPU time 1.21 seconds
Started Jul 06 06:27:24 PM PDT 24
Finished Jul 06 06:27:26 PM PDT 24
Peak memory 217236 kb
Host smart-968810a8-ed68-4f0c-bbe3-70f40cfe1eb6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898932319 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.2898932319
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.3281609954
Short name T210
Test name
Test status
Simulation time 61052118 ps
CPU time 1.24 seconds
Started Jul 06 06:27:26 PM PDT 24
Finished Jul 06 06:27:28 PM PDT 24
Peak memory 217084 kb
Host smart-9a24688e-c98f-4c9a-9adc-f9d8d45f684a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281609954 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.3281609954
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_disable.374804852
Short name T187
Test name
Test status
Simulation time 17732414 ps
CPU time 0.84 seconds
Started Jul 06 06:27:30 PM PDT 24
Finished Jul 06 06:27:31 PM PDT 24
Peak memory 216584 kb
Host smart-6394169f-4c80-4073-8a71-15f77d6454d4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374804852 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.374804852
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable.2045630996
Short name T760
Test name
Test status
Simulation time 28666007 ps
CPU time 0.85 seconds
Started Jul 06 06:27:36 PM PDT 24
Finished Jul 06 06:27:37 PM PDT 24
Peak memory 216708 kb
Host smart-01302199-601a-4d7d-95be-d393f147a5a2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045630996 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.2045630996
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/45.edn_err.1657781096
Short name T191
Test name
Test status
Simulation time 23486356 ps
CPU time 0.91 seconds
Started Jul 06 06:28:06 PM PDT 24
Finished Jul 06 06:28:07 PM PDT 24
Peak memory 218808 kb
Host smart-c80749f3-6613-4117-b0c4-1f3ac7a44c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657781096 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.1657781096
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/162.edn_genbits.815598002
Short name T245
Test name
Test status
Simulation time 282416336 ps
CPU time 3.97 seconds
Started Jul 06 06:28:59 PM PDT 24
Finished Jul 06 06:29:04 PM PDT 24
Peak memory 218920 kb
Host smart-400fbe28-9e4c-4c6c-8fd5-160ef86f87d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815598002 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.815598002
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_genbits.875913990
Short name T96
Test name
Test status
Simulation time 38583652 ps
CPU time 1.57 seconds
Started Jul 06 06:29:10 PM PDT 24
Finished Jul 06 06:29:12 PM PDT 24
Peak memory 218944 kb
Host smart-c99aa806-8553-4c06-ae26-57ef2c7fae51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875913990 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.875913990
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_genbits.1121782597
Short name T102
Test name
Test status
Simulation time 105070615 ps
CPU time 1.36 seconds
Started Jul 06 06:29:12 PM PDT 24
Finished Jul 06 06:29:14 PM PDT 24
Peak memory 219412 kb
Host smart-4e010b06-68e0-4ca5-b790-01ece227a0fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121782597 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.1121782597
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.130348334
Short name T107
Test name
Test status
Simulation time 25913170 ps
CPU time 0.96 seconds
Started Jul 06 06:27:14 PM PDT 24
Finished Jul 06 06:27:15 PM PDT 24
Peak memory 216172 kb
Host smart-711f3bfb-8ffa-4a39-befa-baf14fa82814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130348334 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.130348334
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/184.edn_alert.3337361583
Short name T221
Test name
Test status
Simulation time 33880208 ps
CPU time 1.42 seconds
Started Jul 06 06:29:09 PM PDT 24
Finished Jul 06 06:29:11 PM PDT 24
Peak memory 216032 kb
Host smart-5f2592d9-2f48-44da-8203-bc62adb06648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337361583 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_alert.3337361583
Directory /workspace/184.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.2859240720
Short name T282
Test name
Test status
Simulation time 18554653 ps
CPU time 1.1 seconds
Started Jul 06 05:13:18 PM PDT 24
Finished Jul 06 05:13:20 PM PDT 24
Peak memory 206888 kb
Host smart-a300acf2-784c-4380-b87d-021c0a2f5fa8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859240720 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.2859240720
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.edn_sec_cm.2308213772
Short name T72
Test name
Test status
Simulation time 453907253 ps
CPU time 7.53 seconds
Started Jul 06 06:26:48 PM PDT 24
Finished Jul 06 06:26:56 PM PDT 24
Peak memory 236820 kb
Host smart-1d9fc09a-53e7-424d-ac38-23319f850c52
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308213772 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.2308213772
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_regwen.1922574680
Short name T313
Test name
Test status
Simulation time 17352192 ps
CPU time 0.94 seconds
Started Jul 06 06:26:45 PM PDT 24
Finished Jul 06 06:26:46 PM PDT 24
Peak memory 207396 kb
Host smart-df5cca26-edcd-4e7e-93ee-18945698c834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922574680 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.1922574680
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.3742478526
Short name T503
Test name
Test status
Simulation time 114306799371 ps
CPU time 1410.35 seconds
Started Jul 06 06:26:46 PM PDT 24
Finished Jul 06 06:50:17 PM PDT 24
Peak memory 227044 kb
Host smart-88cb9493-d176-44f4-a014-65f5362c4eb7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742478526 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.3742478526
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_stress_all.4101601565
Short name T254
Test name
Test status
Simulation time 402279387 ps
CPU time 2.17 seconds
Started Jul 06 06:26:51 PM PDT 24
Finished Jul 06 06:26:53 PM PDT 24
Peak memory 217604 kb
Host smart-a1022ced-c1e0-4967-81d9-8922a3fb4c83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101601565 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.4101601565
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/130.edn_genbits.752889711
Short name T334
Test name
Test status
Simulation time 215110115 ps
CPU time 1.01 seconds
Started Jul 06 06:28:54 PM PDT 24
Finished Jul 06 06:28:56 PM PDT 24
Peak memory 217804 kb
Host smart-d15c4f40-4d3f-4855-877c-f4cb086cced1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752889711 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.752889711
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_genbits.863331659
Short name T974
Test name
Test status
Simulation time 34894822 ps
CPU time 1.49 seconds
Started Jul 06 06:28:52 PM PDT 24
Finished Jul 06 06:28:54 PM PDT 24
Peak memory 217520 kb
Host smart-17d984b9-4f36-4fe7-ab55-c715d05b3313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863331659 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.863331659
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_genbits.2557563834
Short name T328
Test name
Test status
Simulation time 75035759 ps
CPU time 1.55 seconds
Started Jul 06 06:28:55 PM PDT 24
Finished Jul 06 06:28:57 PM PDT 24
Peak memory 219132 kb
Host smart-e1c113d8-4073-4b81-b2e5-7c97b2e44356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557563834 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.2557563834
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_genbits.451032967
Short name T340
Test name
Test status
Simulation time 70838235 ps
CPU time 2.71 seconds
Started Jul 06 06:28:56 PM PDT 24
Finished Jul 06 06:29:00 PM PDT 24
Peak memory 220512 kb
Host smart-25ce9612-b5da-4d10-8b45-61c3bfa99227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451032967 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.451032967
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.3628173946
Short name T860
Test name
Test status
Simulation time 76790938663 ps
CPU time 450.2 seconds
Started Jul 06 06:27:17 PM PDT 24
Finished Jul 06 06:34:48 PM PDT 24
Peak memory 222452 kb
Host smart-87d94be7-134b-44ec-bb4c-3b1d4551d524
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628173946 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.3628173946
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_genbits.4076185702
Short name T992
Test name
Test status
Simulation time 45397787 ps
CPU time 1.44 seconds
Started Jul 06 06:28:59 PM PDT 24
Finished Jul 06 06:29:01 PM PDT 24
Peak memory 219228 kb
Host smart-2caa3e97-75e5-417b-adb7-bee7bcd21b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076185702 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.4076185702
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_genbits.1634222137
Short name T572
Test name
Test status
Simulation time 57409218 ps
CPU time 1.29 seconds
Started Jul 06 06:28:59 PM PDT 24
Finished Jul 06 06:29:01 PM PDT 24
Peak memory 219032 kb
Host smart-41d6c7cd-09c1-40d9-af86-3572125dc79e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634222137 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.1634222137
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_genbits.617001276
Short name T349
Test name
Test status
Simulation time 87337081 ps
CPU time 1.58 seconds
Started Jul 06 06:29:08 PM PDT 24
Finished Jul 06 06:29:10 PM PDT 24
Peak memory 219184 kb
Host smart-dce3cc06-355a-4330-98eb-ed602f7bd139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617001276 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.617001276
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.3250110577
Short name T300
Test name
Test status
Simulation time 110702719 ps
CPU time 1.15 seconds
Started Jul 06 06:27:51 PM PDT 24
Finished Jul 06 06:27:52 PM PDT 24
Peak memory 219964 kb
Host smart-da3a54a6-3521-43f0-aecc-8cdc39c53b54
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250110577 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.3250110577
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/76.edn_genbits.3484498933
Short name T333
Test name
Test status
Simulation time 58901707 ps
CPU time 1.64 seconds
Started Jul 06 06:28:26 PM PDT 24
Finished Jul 06 06:28:28 PM PDT 24
Peak memory 220280 kb
Host smart-e3fc8ec5-7583-4d30-b48d-cd46d1d6fc59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484498933 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.3484498933
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.3988819534
Short name T740
Test name
Test status
Simulation time 28925152 ps
CPU time 0.88 seconds
Started Jul 06 06:27:15 PM PDT 24
Finished Jul 06 06:27:16 PM PDT 24
Peak memory 216044 kb
Host smart-9abf5b3d-350b-41d8-b6bc-b6a39cecd7b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988819534 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.3988819534
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/23.edn_err.2330834491
Short name T7
Test name
Test status
Simulation time 63539700 ps
CPU time 0.9 seconds
Started Jul 06 06:27:27 PM PDT 24
Finished Jul 06 06:27:29 PM PDT 24
Peak memory 220216 kb
Host smart-305a8314-f5f9-4dee-97b5-ea8475007d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330834491 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.2330834491
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/125.edn_genbits.2010476539
Short name T632
Test name
Test status
Simulation time 60855309 ps
CPU time 1.88 seconds
Started Jul 06 06:28:51 PM PDT 24
Finished Jul 06 06:28:54 PM PDT 24
Peak memory 220324 kb
Host smart-49dce99f-753e-4130-b35f-7d008ddd3e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010476539 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.2010476539
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_alert.836621444
Short name T118
Test name
Test status
Simulation time 27256416 ps
CPU time 1.19 seconds
Started Jul 06 06:28:44 PM PDT 24
Finished Jul 06 06:28:46 PM PDT 24
Peak memory 220228 kb
Host smart-39a7c58b-b82f-43c2-b0a1-429beab2f984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836621444 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_alert.836621444
Directory /workspace/115.edn_alert/latest

Test location /workspace/coverage/default/15.edn_genbits.2754929658
Short name T616
Test name
Test status
Simulation time 49881758 ps
CPU time 1.62 seconds
Started Jul 06 06:27:17 PM PDT 24
Finished Jul 06 06:27:19 PM PDT 24
Peak memory 220336 kb
Host smart-30c143c5-a7e2-4216-828b-3af4ed32aaf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754929658 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.2754929658
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.3211557708
Short name T262
Test name
Test status
Simulation time 156257921 ps
CPU time 1.51 seconds
Started Jul 06 05:13:18 PM PDT 24
Finished Jul 06 05:13:20 PM PDT 24
Peak memory 206848 kb
Host smart-5a5536e0-9a65-4fec-be4c-503d5487452b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211557708 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.3211557708
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.2888497707
Short name T1109
Test name
Test status
Simulation time 121481571 ps
CPU time 3.28 seconds
Started Jul 06 05:13:20 PM PDT 24
Finished Jul 06 05:13:24 PM PDT 24
Peak memory 206972 kb
Host smart-daa90390-f415-4ab8-8bad-166a69eba76e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888497707 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.2888497707
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.2812899793
Short name T1073
Test name
Test status
Simulation time 47742909 ps
CPU time 0.96 seconds
Started Jul 06 05:13:18 PM PDT 24
Finished Jul 06 05:13:20 PM PDT 24
Peak memory 206948 kb
Host smart-55f5b2a1-268a-4b8f-9b8f-ebae95605e8f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812899793 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.2812899793
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.2804128659
Short name T1090
Test name
Test status
Simulation time 49697171 ps
CPU time 1.4 seconds
Started Jul 06 05:13:06 PM PDT 24
Finished Jul 06 05:13:08 PM PDT 24
Peak memory 215232 kb
Host smart-7e3d3a64-a4ab-4484-9942-91f7f3a19df4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804128659 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.2804128659
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.3686337279
Short name T1102
Test name
Test status
Simulation time 31513508 ps
CPU time 0.85 seconds
Started Jul 06 05:13:04 PM PDT 24
Finished Jul 06 05:13:05 PM PDT 24
Peak memory 206940 kb
Host smart-4fcfeffb-c55f-436a-b779-69b572abc6c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686337279 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.3686337279
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.1366420728
Short name T1043
Test name
Test status
Simulation time 59652116 ps
CPU time 0.94 seconds
Started Jul 06 05:13:05 PM PDT 24
Finished Jul 06 05:13:07 PM PDT 24
Peak memory 206868 kb
Host smart-7100bf53-d789-41dd-9262-92444fcfd7ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366420728 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.1366420728
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.794391496
Short name T1035
Test name
Test status
Simulation time 24159671 ps
CPU time 0.94 seconds
Started Jul 06 05:13:08 PM PDT 24
Finished Jul 06 05:13:09 PM PDT 24
Peak memory 206944 kb
Host smart-73b3a86c-b837-4f59-9f84-6bd7080ca1b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794391496 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_out
standing.794391496
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.2499212689
Short name T1058
Test name
Test status
Simulation time 160801699 ps
CPU time 3 seconds
Started Jul 06 05:13:07 PM PDT 24
Finished Jul 06 05:13:11 PM PDT 24
Peak memory 215176 kb
Host smart-09ee3cf6-1553-4a97-9fdd-12c10ed52233
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499212689 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.2499212689
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.1886174329
Short name T291
Test name
Test status
Simulation time 70039269 ps
CPU time 1.6 seconds
Started Jul 06 05:13:10 PM PDT 24
Finished Jul 06 05:13:12 PM PDT 24
Peak memory 207016 kb
Host smart-b3627b75-d083-4565-b1d7-a5bba3b9bdd9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886174329 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.1886174329
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.2450130381
Short name T271
Test name
Test status
Simulation time 61965541 ps
CPU time 1.22 seconds
Started Jul 06 05:13:04 PM PDT 24
Finished Jul 06 05:13:06 PM PDT 24
Peak memory 207008 kb
Host smart-88be95ca-f330-4d6a-b7b2-ca3c8e9beaba
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450130381 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.2450130381
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.3530716743
Short name T272
Test name
Test status
Simulation time 58732137 ps
CPU time 3.24 seconds
Started Jul 06 05:13:13 PM PDT 24
Finished Jul 06 05:13:17 PM PDT 24
Peak memory 207044 kb
Host smart-3cafe285-8147-49b0-a353-fd87ad5d3081
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530716743 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.3530716743
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.3536843316
Short name T1034
Test name
Test status
Simulation time 48117496 ps
CPU time 0.88 seconds
Started Jul 06 05:13:24 PM PDT 24
Finished Jul 06 05:13:25 PM PDT 24
Peak memory 206912 kb
Host smart-59e7cdac-f422-46d6-88c5-0347aadec2e6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536843316 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.3536843316
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.2991674863
Short name T1105
Test name
Test status
Simulation time 235419832 ps
CPU time 1.43 seconds
Started Jul 06 05:13:07 PM PDT 24
Finished Jul 06 05:13:09 PM PDT 24
Peak memory 215260 kb
Host smart-bf37b684-3c21-46d7-9032-57210b15c286
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991674863 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.2991674863
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.1456041509
Short name T1068
Test name
Test status
Simulation time 33474448 ps
CPU time 0.86 seconds
Started Jul 06 05:13:18 PM PDT 24
Finished Jul 06 05:13:20 PM PDT 24
Peak memory 206972 kb
Host smart-ffbb7031-f282-4c81-b78d-b7c93f3f8ee6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456041509 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.1456041509
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.1391045561
Short name T1094
Test name
Test status
Simulation time 25098209 ps
CPU time 0.87 seconds
Started Jul 06 05:13:06 PM PDT 24
Finished Jul 06 05:13:07 PM PDT 24
Peak memory 206856 kb
Host smart-a2b53353-1fa1-4b1e-9f93-db5ebbdb4dfe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391045561 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.1391045561
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.1439901197
Short name T1015
Test name
Test status
Simulation time 39906374 ps
CPU time 2.59 seconds
Started Jul 06 05:13:01 PM PDT 24
Finished Jul 06 05:13:04 PM PDT 24
Peak memory 215212 kb
Host smart-02e8defd-e60b-493c-a1d4-5c2ddf3bd5f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439901197 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.1439901197
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.228786524
Short name T1059
Test name
Test status
Simulation time 123358045 ps
CPU time 3.11 seconds
Started Jul 06 05:13:18 PM PDT 24
Finished Jul 06 05:13:22 PM PDT 24
Peak memory 207200 kb
Host smart-3ac9aa42-4d40-492f-9dcf-27c2eb7b00ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228786524 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.228786524
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.2465621500
Short name T1125
Test name
Test status
Simulation time 74511577 ps
CPU time 1.11 seconds
Started Jul 06 05:13:09 PM PDT 24
Finished Jul 06 05:13:11 PM PDT 24
Peak memory 215228 kb
Host smart-f6f70020-d64b-489f-9dfc-76ee15890832
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465621500 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.2465621500
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.2909318893
Short name T268
Test name
Test status
Simulation time 47659450 ps
CPU time 0.9 seconds
Started Jul 06 05:13:15 PM PDT 24
Finished Jul 06 05:13:16 PM PDT 24
Peak memory 206884 kb
Host smart-62b4594d-1528-469b-bc8e-968efb16fc59
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909318893 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.2909318893
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.1234929401
Short name T1129
Test name
Test status
Simulation time 19823805 ps
CPU time 0.78 seconds
Started Jul 06 05:13:19 PM PDT 24
Finished Jul 06 05:13:21 PM PDT 24
Peak memory 206600 kb
Host smart-1e431b01-5845-4c8f-ab3f-f688a6b9ece8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234929401 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.1234929401
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.766902261
Short name T284
Test name
Test status
Simulation time 133003354 ps
CPU time 1.02 seconds
Started Jul 06 05:13:11 PM PDT 24
Finished Jul 06 05:13:12 PM PDT 24
Peak memory 206844 kb
Host smart-53c7ba2b-b58e-457a-9eec-74d9259695c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766902261 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_ou
tstanding.766902261
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.1466720488
Short name T1072
Test name
Test status
Simulation time 66148981 ps
CPU time 2.22 seconds
Started Jul 06 05:13:09 PM PDT 24
Finished Jul 06 05:13:12 PM PDT 24
Peak memory 215228 kb
Host smart-8c12abe6-fe79-47a4-b358-459e32d00038
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466720488 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.1466720488
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.3153715823
Short name T306
Test name
Test status
Simulation time 288093805 ps
CPU time 1.46 seconds
Started Jul 06 05:13:17 PM PDT 24
Finished Jul 06 05:13:20 PM PDT 24
Peak memory 206912 kb
Host smart-f4744eb8-20fe-4a1f-af46-24a163139934
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153715823 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.3153715823
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3602089471
Short name T1067
Test name
Test status
Simulation time 73766341 ps
CPU time 1.15 seconds
Started Jul 06 05:13:09 PM PDT 24
Finished Jul 06 05:13:10 PM PDT 24
Peak memory 215220 kb
Host smart-6fdee7e3-808b-4382-a10e-7be9654834f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602089471 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.3602089471
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.2307641660
Short name T280
Test name
Test status
Simulation time 14437115 ps
CPU time 0.89 seconds
Started Jul 06 05:13:09 PM PDT 24
Finished Jul 06 05:13:10 PM PDT 24
Peak memory 206876 kb
Host smart-1a182f3c-d16f-4032-89ee-0a20a23c2b00
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307641660 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.2307641660
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.927341632
Short name T1119
Test name
Test status
Simulation time 49241754 ps
CPU time 0.82 seconds
Started Jul 06 05:13:07 PM PDT 24
Finished Jul 06 05:13:08 PM PDT 24
Peak memory 206684 kb
Host smart-9b23e3e2-8b53-4bc1-9d74-64de0b87b1c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927341632 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.927341632
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.2908876699
Short name T1045
Test name
Test status
Simulation time 40496904 ps
CPU time 0.93 seconds
Started Jul 06 05:13:06 PM PDT 24
Finished Jul 06 05:13:08 PM PDT 24
Peak memory 206932 kb
Host smart-2306639c-1211-41c7-b34d-c2dfcc5a249a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908876699 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.2908876699
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.3523640893
Short name T1066
Test name
Test status
Simulation time 25749807 ps
CPU time 1.78 seconds
Started Jul 06 05:13:12 PM PDT 24
Finished Jul 06 05:13:14 PM PDT 24
Peak memory 215136 kb
Host smart-713983cb-850c-4f67-96f7-17ceeeebb2a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523640893 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.3523640893
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.3193215245
Short name T293
Test name
Test status
Simulation time 62719943 ps
CPU time 1.77 seconds
Started Jul 06 05:13:18 PM PDT 24
Finished Jul 06 05:13:21 PM PDT 24
Peak memory 206904 kb
Host smart-0381c88d-5f5c-42e5-8686-ded0a88ac0a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193215245 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.3193215245
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1322890586
Short name T1130
Test name
Test status
Simulation time 29426589 ps
CPU time 1.11 seconds
Started Jul 06 05:13:18 PM PDT 24
Finished Jul 06 05:13:20 PM PDT 24
Peak memory 217356 kb
Host smart-a0a9c92b-67ae-401f-a1c9-2819c39cb4ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322890586 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.1322890586
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.4132426375
Short name T1114
Test name
Test status
Simulation time 26772569 ps
CPU time 0.89 seconds
Started Jul 06 05:13:17 PM PDT 24
Finished Jul 06 05:13:18 PM PDT 24
Peak memory 206828 kb
Host smart-f2ecc857-02b4-40cb-acf6-5b3b575a10f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132426375 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.4132426375
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.1204614216
Short name T1107
Test name
Test status
Simulation time 16841090 ps
CPU time 0.76 seconds
Started Jul 06 05:13:17 PM PDT 24
Finished Jul 06 05:13:18 PM PDT 24
Peak memory 206728 kb
Host smart-8f10d1b7-0945-4f2c-a26a-c64ac4e8dbb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204614216 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.1204614216
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.1478357101
Short name T278
Test name
Test status
Simulation time 113412511 ps
CPU time 1.36 seconds
Started Jul 06 05:13:20 PM PDT 24
Finished Jul 06 05:13:22 PM PDT 24
Peak memory 206952 kb
Host smart-59ff9ed7-4d18-4af5-88c0-973af13458ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478357101 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.1478357101
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.3395875283
Short name T1021
Test name
Test status
Simulation time 562439875 ps
CPU time 4.72 seconds
Started Jul 06 05:13:26 PM PDT 24
Finished Jul 06 05:13:31 PM PDT 24
Peak memory 215252 kb
Host smart-3561d5f6-7887-4af9-bb00-59e233b473c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395875283 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.3395875283
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.1986863814
Short name T1065
Test name
Test status
Simulation time 39760883 ps
CPU time 1.38 seconds
Started Jul 06 05:13:30 PM PDT 24
Finished Jul 06 05:13:31 PM PDT 24
Peak memory 206964 kb
Host smart-0c8bec2f-b556-4c7f-8e67-82a6faa6bc27
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986863814 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.1986863814
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.3389654426
Short name T1124
Test name
Test status
Simulation time 19905499 ps
CPU time 1.16 seconds
Started Jul 06 05:13:26 PM PDT 24
Finished Jul 06 05:13:28 PM PDT 24
Peak memory 217784 kb
Host smart-37c868bb-e1ac-4a5d-91fb-50e613dff192
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389654426 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.3389654426
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.4146180295
Short name T1080
Test name
Test status
Simulation time 42542740 ps
CPU time 0.84 seconds
Started Jul 06 05:13:20 PM PDT 24
Finished Jul 06 05:13:22 PM PDT 24
Peak memory 206848 kb
Host smart-f7be57ba-5e15-40d1-89ce-52e005a843ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146180295 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.4146180295
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.1060509287
Short name T1069
Test name
Test status
Simulation time 25007526 ps
CPU time 0.96 seconds
Started Jul 06 05:13:18 PM PDT 24
Finished Jul 06 05:13:20 PM PDT 24
Peak memory 206892 kb
Host smart-7aab912a-91b6-41c0-a576-41ca74c1ced2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060509287 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.1060509287
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.3784801754
Short name T1047
Test name
Test status
Simulation time 73010364 ps
CPU time 2.63 seconds
Started Jul 06 05:13:27 PM PDT 24
Finished Jul 06 05:13:30 PM PDT 24
Peak memory 215192 kb
Host smart-0a5970a9-8284-4c94-8d1d-0235cb7c9c86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784801754 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.3784801754
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.2480622008
Short name T1024
Test name
Test status
Simulation time 592973229 ps
CPU time 2.34 seconds
Started Jul 06 05:13:15 PM PDT 24
Finished Jul 06 05:13:17 PM PDT 24
Peak memory 207120 kb
Host smart-a9bf36e2-ae05-469d-99b3-1e7e36eee7b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480622008 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.2480622008
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.3121331211
Short name T1123
Test name
Test status
Simulation time 31918140 ps
CPU time 1.93 seconds
Started Jul 06 05:13:14 PM PDT 24
Finished Jul 06 05:13:17 PM PDT 24
Peak memory 215232 kb
Host smart-661ff10c-c677-449e-a85b-96cf15a5d78b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121331211 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.3121331211
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.1439875815
Short name T279
Test name
Test status
Simulation time 13811565 ps
CPU time 0.91 seconds
Started Jul 06 05:13:19 PM PDT 24
Finished Jul 06 05:13:22 PM PDT 24
Peak memory 206940 kb
Host smart-34fc2424-1e5a-4268-a080-2c6a093d6f71
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439875815 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.1439875815
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.3125251464
Short name T1012
Test name
Test status
Simulation time 21559970 ps
CPU time 0.83 seconds
Started Jul 06 05:13:17 PM PDT 24
Finished Jul 06 05:13:19 PM PDT 24
Peak memory 206904 kb
Host smart-57f0f059-6402-4bd4-b69a-cb3bb3abfeca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125251464 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.3125251464
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.514979878
Short name T1128
Test name
Test status
Simulation time 273718310 ps
CPU time 1.49 seconds
Started Jul 06 05:13:26 PM PDT 24
Finished Jul 06 05:13:28 PM PDT 24
Peak memory 206940 kb
Host smart-93f55696-eb25-44ab-a9bf-c463f4ac4ca9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514979878 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_ou
tstanding.514979878
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.3615119709
Short name T1000
Test name
Test status
Simulation time 377265267 ps
CPU time 3.26 seconds
Started Jul 06 05:13:33 PM PDT 24
Finished Jul 06 05:13:37 PM PDT 24
Peak memory 215148 kb
Host smart-13675c92-95c2-4820-9bc1-593481d75e7e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615119709 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.3615119709
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.1337069597
Short name T1078
Test name
Test status
Simulation time 177615331 ps
CPU time 1.6 seconds
Started Jul 06 05:13:22 PM PDT 24
Finished Jul 06 05:13:24 PM PDT 24
Peak memory 215120 kb
Host smart-47c2ddef-1c3b-4384-b2d8-cbebc2814bf7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337069597 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.1337069597
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1735299772
Short name T1092
Test name
Test status
Simulation time 175370769 ps
CPU time 1.36 seconds
Started Jul 06 05:13:17 PM PDT 24
Finished Jul 06 05:13:19 PM PDT 24
Peak memory 215136 kb
Host smart-11f93d5f-2a80-4526-81c4-a8c9b67e8549
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735299772 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.1735299772
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.4024247621
Short name T266
Test name
Test status
Simulation time 16172672 ps
CPU time 0.81 seconds
Started Jul 06 05:13:31 PM PDT 24
Finished Jul 06 05:13:32 PM PDT 24
Peak memory 206752 kb
Host smart-d258435e-19aa-4d17-9d0f-d82a84cb27a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024247621 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.4024247621
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.726019324
Short name T1023
Test name
Test status
Simulation time 12101243 ps
CPU time 0.87 seconds
Started Jul 06 05:13:26 PM PDT 24
Finished Jul 06 05:13:28 PM PDT 24
Peak memory 206864 kb
Host smart-112daa12-7e49-406c-a3ec-480794f910e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726019324 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.726019324
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.966286459
Short name T1079
Test name
Test status
Simulation time 109094048 ps
CPU time 0.93 seconds
Started Jul 06 05:13:38 PM PDT 24
Finished Jul 06 05:13:39 PM PDT 24
Peak memory 206996 kb
Host smart-c9134608-8eff-479c-b24a-02998355e158
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966286459 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_ou
tstanding.966286459
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.494275853
Short name T1051
Test name
Test status
Simulation time 70498519 ps
CPU time 2.23 seconds
Started Jul 06 05:13:12 PM PDT 24
Finished Jul 06 05:13:15 PM PDT 24
Peak memory 219064 kb
Host smart-925e5d85-ea7e-4c32-bbc5-0d1d06a1a432
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494275853 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.494275853
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.2936531577
Short name T1127
Test name
Test status
Simulation time 255344610 ps
CPU time 1.56 seconds
Started Jul 06 05:13:13 PM PDT 24
Finished Jul 06 05:13:15 PM PDT 24
Peak memory 207328 kb
Host smart-c18430fd-9a15-436f-892d-ad9d400ceed0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936531577 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.2936531577
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.1396472955
Short name T1081
Test name
Test status
Simulation time 22710183 ps
CPU time 1.19 seconds
Started Jul 06 05:13:14 PM PDT 24
Finished Jul 06 05:13:16 PM PDT 24
Peak memory 215200 kb
Host smart-a7d8f368-e729-460c-b15e-d931d51bb896
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396472955 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.1396472955
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.1644344242
Short name T1011
Test name
Test status
Simulation time 73969808 ps
CPU time 0.82 seconds
Started Jul 06 05:13:22 PM PDT 24
Finished Jul 06 05:13:23 PM PDT 24
Peak memory 206748 kb
Host smart-af4fd50b-6736-449d-a541-b025ae2d8065
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644344242 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.1644344242
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.4189226617
Short name T1025
Test name
Test status
Simulation time 13261887 ps
CPU time 0.85 seconds
Started Jul 06 05:13:13 PM PDT 24
Finished Jul 06 05:13:14 PM PDT 24
Peak memory 206900 kb
Host smart-a998be53-613b-4048-a6aa-992a7f78121f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189226617 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.4189226617
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.2401756088
Short name T281
Test name
Test status
Simulation time 46124396 ps
CPU time 1.01 seconds
Started Jul 06 05:13:17 PM PDT 24
Finished Jul 06 05:13:19 PM PDT 24
Peak memory 206992 kb
Host smart-0b41d1e9-508f-4dd5-92fa-fd48a08f5a29
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401756088 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.2401756088
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.3585307341
Short name T1083
Test name
Test status
Simulation time 229656270 ps
CPU time 1.59 seconds
Started Jul 06 05:13:16 PM PDT 24
Finished Jul 06 05:13:18 PM PDT 24
Peak memory 215216 kb
Host smart-f0ba682e-0926-4ed2-a32f-6ea2e4cf2b60
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585307341 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.3585307341
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.1862902972
Short name T1044
Test name
Test status
Simulation time 137756398 ps
CPU time 2.19 seconds
Started Jul 06 05:13:18 PM PDT 24
Finished Jul 06 05:13:22 PM PDT 24
Peak memory 207012 kb
Host smart-24cdb90b-ab94-44ed-bd7e-7d93174f1f31
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862902972 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.1862902972
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3658384615
Short name T998
Test name
Test status
Simulation time 243641466 ps
CPU time 1.21 seconds
Started Jul 06 05:13:19 PM PDT 24
Finished Jul 06 05:13:22 PM PDT 24
Peak memory 217432 kb
Host smart-54ef7de4-5d54-449a-81fc-2e6fa07fc311
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658384615 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.3658384615
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.2832261508
Short name T1054
Test name
Test status
Simulation time 15026342 ps
CPU time 0.95 seconds
Started Jul 06 05:13:32 PM PDT 24
Finished Jul 06 05:13:33 PM PDT 24
Peak memory 206916 kb
Host smart-e804c1ce-1ddc-4e7d-94b5-a98e61c47eee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832261508 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.2832261508
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.995640301
Short name T1115
Test name
Test status
Simulation time 24201415 ps
CPU time 0.9 seconds
Started Jul 06 05:13:14 PM PDT 24
Finished Jul 06 05:13:15 PM PDT 24
Peak memory 206856 kb
Host smart-f78074f1-7329-4d02-9448-17d250086d8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995640301 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.995640301
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.352529770
Short name T1029
Test name
Test status
Simulation time 20796479 ps
CPU time 1.09 seconds
Started Jul 06 05:13:20 PM PDT 24
Finished Jul 06 05:13:22 PM PDT 24
Peak memory 206820 kb
Host smart-b606961b-9c16-4f22-aca1-7abb27b7c03d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352529770 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_ou
tstanding.352529770
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.4062905389
Short name T1003
Test name
Test status
Simulation time 135147179 ps
CPU time 2.48 seconds
Started Jul 06 05:13:13 PM PDT 24
Finished Jul 06 05:13:16 PM PDT 24
Peak memory 215164 kb
Host smart-1d15173f-f754-4e02-9560-06521ce658df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062905389 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.4062905389
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.3846326759
Short name T1048
Test name
Test status
Simulation time 133741931 ps
CPU time 3.09 seconds
Started Jul 06 05:13:19 PM PDT 24
Finished Jul 06 05:13:23 PM PDT 24
Peak memory 206932 kb
Host smart-659f3d34-7521-4945-a47f-d8217fc7ecb6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846326759 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.3846326759
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.834689819
Short name T1014
Test name
Test status
Simulation time 42113866 ps
CPU time 1.24 seconds
Started Jul 06 05:13:30 PM PDT 24
Finished Jul 06 05:13:32 PM PDT 24
Peak memory 215236 kb
Host smart-743247a3-9682-4e82-a934-9118c2abace3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834689819 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.834689819
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.2398213223
Short name T270
Test name
Test status
Simulation time 164572553 ps
CPU time 0.83 seconds
Started Jul 06 05:13:37 PM PDT 24
Finished Jul 06 05:13:38 PM PDT 24
Peak memory 206780 kb
Host smart-33a8d7c1-ee8b-4151-94ca-3b8eada84343
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398213223 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.2398213223
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.1072337521
Short name T1111
Test name
Test status
Simulation time 32958558 ps
CPU time 0.81 seconds
Started Jul 06 05:13:32 PM PDT 24
Finished Jul 06 05:13:33 PM PDT 24
Peak memory 206640 kb
Host smart-c9049412-93c9-41bf-95bc-10bb082cd2af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072337521 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.1072337521
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.1463864625
Short name T1082
Test name
Test status
Simulation time 57779855 ps
CPU time 1.32 seconds
Started Jul 06 05:13:37 PM PDT 24
Finished Jul 06 05:13:38 PM PDT 24
Peak memory 206944 kb
Host smart-2aadd768-ff69-4c26-aad8-5d96e3968b4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463864625 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.1463864625
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.3934189711
Short name T1030
Test name
Test status
Simulation time 59975510 ps
CPU time 2.2 seconds
Started Jul 06 05:13:13 PM PDT 24
Finished Jul 06 05:13:16 PM PDT 24
Peak memory 215240 kb
Host smart-7052b486-e932-45f9-b873-39157595c5fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934189711 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.3934189711
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.4016553762
Short name T1110
Test name
Test status
Simulation time 302103609 ps
CPU time 2.1 seconds
Started Jul 06 05:13:21 PM PDT 24
Finished Jul 06 05:13:23 PM PDT 24
Peak memory 215232 kb
Host smart-8278ea14-2452-4798-9a74-0ef9c0ae6aeb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016553762 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.4016553762
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3870470010
Short name T1017
Test name
Test status
Simulation time 29597441 ps
CPU time 1.81 seconds
Started Jul 06 05:13:26 PM PDT 24
Finished Jul 06 05:13:28 PM PDT 24
Peak memory 215156 kb
Host smart-9157c5c2-c2bd-4ce7-aa17-90533004d675
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870470010 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.3870470010
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.3533637616
Short name T273
Test name
Test status
Simulation time 14426449 ps
CPU time 0.88 seconds
Started Jul 06 05:13:17 PM PDT 24
Finished Jul 06 05:13:19 PM PDT 24
Peak memory 206880 kb
Host smart-3cf7edfa-474a-4c6a-8af0-9130dd54aebe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533637616 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.3533637616
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.2402286278
Short name T1076
Test name
Test status
Simulation time 57454746 ps
CPU time 0.84 seconds
Started Jul 06 05:13:24 PM PDT 24
Finished Jul 06 05:13:25 PM PDT 24
Peak memory 206892 kb
Host smart-6b4f10b2-7466-47dc-acc8-ba63a84e95c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402286278 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.2402286278
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.844470313
Short name T1116
Test name
Test status
Simulation time 90339386 ps
CPU time 1.13 seconds
Started Jul 06 05:13:31 PM PDT 24
Finished Jul 06 05:13:33 PM PDT 24
Peak memory 206948 kb
Host smart-c968df26-2d14-4fba-b876-ce1a996ab3b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844470313 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_ou
tstanding.844470313
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.138420178
Short name T1026
Test name
Test status
Simulation time 440816678 ps
CPU time 3.89 seconds
Started Jul 06 05:13:36 PM PDT 24
Finished Jul 06 05:13:40 PM PDT 24
Peak memory 215224 kb
Host smart-d849fb4f-0abd-4ae7-8988-3c575d8201af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138420178 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.138420178
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.3112583151
Short name T1088
Test name
Test status
Simulation time 80935078 ps
CPU time 2.16 seconds
Started Jul 06 05:13:29 PM PDT 24
Finished Jul 06 05:13:31 PM PDT 24
Peak memory 207024 kb
Host smart-73f9f6b7-3976-475c-a3e2-1698e4a04ca2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112583151 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.3112583151
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.1361410039
Short name T1009
Test name
Test status
Simulation time 95062698 ps
CPU time 1.23 seconds
Started Jul 06 05:13:10 PM PDT 24
Finished Jul 06 05:13:12 PM PDT 24
Peak memory 206944 kb
Host smart-6e551a3a-030d-4aa1-8e06-ba900dc28196
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361410039 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.1361410039
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.3601437174
Short name T1013
Test name
Test status
Simulation time 697782493 ps
CPU time 5.09 seconds
Started Jul 06 05:13:05 PM PDT 24
Finished Jul 06 05:13:11 PM PDT 24
Peak memory 206948 kb
Host smart-e62ff284-7566-4448-a5ba-4527a040b92a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601437174 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.3601437174
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.3140728146
Short name T264
Test name
Test status
Simulation time 189450686 ps
CPU time 0.95 seconds
Started Jul 06 05:13:08 PM PDT 24
Finished Jul 06 05:13:09 PM PDT 24
Peak memory 206876 kb
Host smart-b3e2ee81-e814-44ed-a52a-bf956edcf41b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140728146 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.3140728146
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.3727407169
Short name T1104
Test name
Test status
Simulation time 38266066 ps
CPU time 1.29 seconds
Started Jul 06 05:13:11 PM PDT 24
Finished Jul 06 05:13:13 PM PDT 24
Peak memory 223384 kb
Host smart-9eef076c-0ec1-411b-845f-06eaa0c05a5d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727407169 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.3727407169
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.930484976
Short name T1087
Test name
Test status
Simulation time 22262037 ps
CPU time 0.9 seconds
Started Jul 06 05:13:08 PM PDT 24
Finished Jul 06 05:13:09 PM PDT 24
Peak memory 206932 kb
Host smart-ece55869-c396-432f-8174-9c541cf23ce0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930484976 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.930484976
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.158283581
Short name T1057
Test name
Test status
Simulation time 12715854 ps
CPU time 0.88 seconds
Started Jul 06 05:13:10 PM PDT 24
Finished Jul 06 05:13:12 PM PDT 24
Peak memory 206860 kb
Host smart-d41cc427-e7f8-4763-a8de-373b6b4893ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158283581 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.158283581
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.1206019438
Short name T1071
Test name
Test status
Simulation time 26195563 ps
CPU time 0.93 seconds
Started Jul 06 05:13:07 PM PDT 24
Finished Jul 06 05:13:08 PM PDT 24
Peak memory 206976 kb
Host smart-6c904a79-c2b2-4e22-afd8-86a08f762332
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206019438 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.1206019438
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.1727014372
Short name T1118
Test name
Test status
Simulation time 102393820 ps
CPU time 2.2 seconds
Started Jul 06 05:13:08 PM PDT 24
Finished Jul 06 05:13:10 PM PDT 24
Peak memory 215096 kb
Host smart-aef7a6e9-23c5-48b1-a014-0a9fede6e3d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727014372 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.1727014372
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.2425748014
Short name T1074
Test name
Test status
Simulation time 46522482 ps
CPU time 1.6 seconds
Started Jul 06 05:13:12 PM PDT 24
Finished Jul 06 05:13:14 PM PDT 24
Peak memory 207008 kb
Host smart-3783d7a9-4774-4295-9089-b95ce2e869df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425748014 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.2425748014
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.3744327330
Short name T1006
Test name
Test status
Simulation time 39397324 ps
CPU time 0.83 seconds
Started Jul 06 05:13:31 PM PDT 24
Finished Jul 06 05:13:32 PM PDT 24
Peak memory 206708 kb
Host smart-c667fa86-3c61-45e5-96a9-0aecf559880d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744327330 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.3744327330
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.1255697107
Short name T1001
Test name
Test status
Simulation time 14004199 ps
CPU time 0.85 seconds
Started Jul 06 05:13:19 PM PDT 24
Finished Jul 06 05:13:21 PM PDT 24
Peak memory 206884 kb
Host smart-49df6f82-3384-41a2-86c1-1f209c8198ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255697107 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.1255697107
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.3763656416
Short name T1098
Test name
Test status
Simulation time 39696737 ps
CPU time 0.79 seconds
Started Jul 06 05:13:42 PM PDT 24
Finished Jul 06 05:13:43 PM PDT 24
Peak memory 206720 kb
Host smart-2a969ef2-c00d-4d37-9c03-c6953a4baa0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763656416 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.3763656416
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.3451069205
Short name T1052
Test name
Test status
Simulation time 10878300 ps
CPU time 0.82 seconds
Started Jul 06 05:13:19 PM PDT 24
Finished Jul 06 05:13:21 PM PDT 24
Peak memory 206844 kb
Host smart-c0216b98-ddf9-4119-af41-f5c80c55405a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451069205 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.3451069205
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.3689408059
Short name T1016
Test name
Test status
Simulation time 13264049 ps
CPU time 0.9 seconds
Started Jul 06 05:13:35 PM PDT 24
Finished Jul 06 05:13:36 PM PDT 24
Peak memory 206888 kb
Host smart-cb6bbaf9-5bad-4604-aa3b-5970904970bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689408059 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.3689408059
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.4155424261
Short name T1099
Test name
Test status
Simulation time 29256497 ps
CPU time 0.86 seconds
Started Jul 06 05:13:35 PM PDT 24
Finished Jul 06 05:13:36 PM PDT 24
Peak memory 206892 kb
Host smart-ac2e856f-201c-4c9e-a07e-03a4b0b68767
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155424261 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.4155424261
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.1079576285
Short name T1010
Test name
Test status
Simulation time 16214665 ps
CPU time 0.91 seconds
Started Jul 06 05:13:26 PM PDT 24
Finished Jul 06 05:13:28 PM PDT 24
Peak memory 206860 kb
Host smart-ac2b05b3-bb9f-4342-bf9c-859d7a9674c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079576285 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.1079576285
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.623044913
Short name T1042
Test name
Test status
Simulation time 12289181 ps
CPU time 0.8 seconds
Started Jul 06 05:13:20 PM PDT 24
Finished Jul 06 05:13:22 PM PDT 24
Peak memory 206712 kb
Host smart-b35f8643-205d-417d-9083-8b86213b720e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623044913 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.623044913
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.398855387
Short name T1085
Test name
Test status
Simulation time 20410206 ps
CPU time 0.81 seconds
Started Jul 06 05:13:26 PM PDT 24
Finished Jul 06 05:13:27 PM PDT 24
Peak memory 206668 kb
Host smart-bebd92a8-e465-49ba-8f2f-9f4fa5a90c93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398855387 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.398855387
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.3649998815
Short name T1018
Test name
Test status
Simulation time 170086222 ps
CPU time 0.88 seconds
Started Jul 06 05:13:19 PM PDT 24
Finished Jul 06 05:13:21 PM PDT 24
Peak memory 206880 kb
Host smart-959d8f17-c07f-48cb-aaa8-f2eb8b0905d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649998815 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.3649998815
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.2604746945
Short name T267
Test name
Test status
Simulation time 29983418 ps
CPU time 1.25 seconds
Started Jul 06 05:13:18 PM PDT 24
Finished Jul 06 05:13:20 PM PDT 24
Peak memory 207032 kb
Host smart-375ec8b1-1e07-4a33-b8f3-25afe665edef
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604746945 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.2604746945
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.4199523172
Short name T1008
Test name
Test status
Simulation time 61323884 ps
CPU time 3.24 seconds
Started Jul 06 05:13:18 PM PDT 24
Finished Jul 06 05:13:23 PM PDT 24
Peak memory 207044 kb
Host smart-24864a90-3539-4518-b063-60e1c30eaf25
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199523172 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.4199523172
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.642633986
Short name T269
Test name
Test status
Simulation time 33231783 ps
CPU time 0.87 seconds
Started Jul 06 05:13:10 PM PDT 24
Finished Jul 06 05:13:12 PM PDT 24
Peak memory 206900 kb
Host smart-c9189a7a-0940-469c-a7b7-8d7980659149
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642633986 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.642633986
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.2859643185
Short name T1028
Test name
Test status
Simulation time 72377637 ps
CPU time 1.14 seconds
Started Jul 06 05:13:06 PM PDT 24
Finished Jul 06 05:13:08 PM PDT 24
Peak memory 215212 kb
Host smart-cf9bf67d-82ec-45c6-a4f7-680356cd858c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859643185 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.2859643185
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.1884688199
Short name T276
Test name
Test status
Simulation time 33186134 ps
CPU time 0.86 seconds
Started Jul 06 05:13:06 PM PDT 24
Finished Jul 06 05:13:08 PM PDT 24
Peak memory 206948 kb
Host smart-91f04e0c-2c02-4be0-8e1c-fedb7032577b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884688199 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.1884688199
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.3133126161
Short name T1097
Test name
Test status
Simulation time 109436565 ps
CPU time 0.9 seconds
Started Jul 06 05:13:06 PM PDT 24
Finished Jul 06 05:13:07 PM PDT 24
Peak memory 206892 kb
Host smart-69c90d1f-6081-433b-8ff2-0d3d9c363ccb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133126161 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.3133126161
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.1938900160
Short name T1063
Test name
Test status
Simulation time 64523316 ps
CPU time 1.16 seconds
Started Jul 06 05:13:06 PM PDT 24
Finished Jul 06 05:13:07 PM PDT 24
Peak memory 206964 kb
Host smart-2c480e12-5ae3-4dc2-aa28-bce4afb2239e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938900160 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.1938900160
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.1919172656
Short name T999
Test name
Test status
Simulation time 260370337 ps
CPU time 2.58 seconds
Started Jul 06 05:13:06 PM PDT 24
Finished Jul 06 05:13:09 PM PDT 24
Peak memory 215164 kb
Host smart-6500aedd-d59b-4ffb-b045-1eccfc980824
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919172656 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.1919172656
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.768098974
Short name T1062
Test name
Test status
Simulation time 167068653 ps
CPU time 1.58 seconds
Started Jul 06 05:13:20 PM PDT 24
Finished Jul 06 05:13:23 PM PDT 24
Peak memory 207012 kb
Host smart-8804eec6-5997-4120-8e0f-4f83a5de3d40
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768098974 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.768098974
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.2895810387
Short name T1084
Test name
Test status
Simulation time 110651951 ps
CPU time 0.8 seconds
Started Jul 06 05:13:21 PM PDT 24
Finished Jul 06 05:13:22 PM PDT 24
Peak memory 206728 kb
Host smart-9ffe9799-ca76-4f9d-9788-f4233251d0d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895810387 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.2895810387
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.2990293393
Short name T1039
Test name
Test status
Simulation time 42322136 ps
CPU time 0.83 seconds
Started Jul 06 05:13:31 PM PDT 24
Finished Jul 06 05:13:32 PM PDT 24
Peak memory 206852 kb
Host smart-aec2e467-7eee-4af6-a151-b629be1f9c7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990293393 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.2990293393
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.1796045359
Short name T1103
Test name
Test status
Simulation time 13668539 ps
CPU time 0.84 seconds
Started Jul 06 05:13:37 PM PDT 24
Finished Jul 06 05:13:38 PM PDT 24
Peak memory 206904 kb
Host smart-648d2c70-1c18-4e80-8390-45e851f36004
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796045359 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.1796045359
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.4115022911
Short name T1121
Test name
Test status
Simulation time 15252581 ps
CPU time 0.88 seconds
Started Jul 06 05:13:29 PM PDT 24
Finished Jul 06 05:13:30 PM PDT 24
Peak memory 206872 kb
Host smart-33b7040a-ec7f-41e3-88ce-4536c57e6585
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115022911 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.4115022911
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.1162342235
Short name T1038
Test name
Test status
Simulation time 14019803 ps
CPU time 0.93 seconds
Started Jul 06 05:13:40 PM PDT 24
Finished Jul 06 05:13:42 PM PDT 24
Peak memory 206920 kb
Host smart-517b6367-af49-42cb-8717-3472d3f2d2a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162342235 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.1162342235
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.1610771994
Short name T1046
Test name
Test status
Simulation time 15190682 ps
CPU time 0.86 seconds
Started Jul 06 05:13:45 PM PDT 24
Finished Jul 06 05:13:46 PM PDT 24
Peak memory 206808 kb
Host smart-a3b44634-2bb3-4da6-9449-73b074cc8a03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610771994 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.1610771994
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.3725457220
Short name T1091
Test name
Test status
Simulation time 14192806 ps
CPU time 0.88 seconds
Started Jul 06 05:13:30 PM PDT 24
Finished Jul 06 05:13:31 PM PDT 24
Peak memory 206868 kb
Host smart-30f883f4-e857-4a29-bb7f-6684ede41d8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725457220 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.3725457220
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.2070188347
Short name T1122
Test name
Test status
Simulation time 21190479 ps
CPU time 0.83 seconds
Started Jul 06 05:13:24 PM PDT 24
Finished Jul 06 05:13:25 PM PDT 24
Peak memory 206720 kb
Host smart-e023a0fa-cedf-4499-85c3-2c984224e02f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070188347 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.2070188347
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.1103406948
Short name T1093
Test name
Test status
Simulation time 19393841 ps
CPU time 0.89 seconds
Started Jul 06 05:13:38 PM PDT 24
Finished Jul 06 05:13:39 PM PDT 24
Peak memory 206796 kb
Host smart-003aeb83-dbe9-4829-b510-04e25538e5d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103406948 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.1103406948
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.1156884047
Short name T1020
Test name
Test status
Simulation time 18882061 ps
CPU time 0.99 seconds
Started Jul 06 05:13:32 PM PDT 24
Finished Jul 06 05:13:33 PM PDT 24
Peak memory 206852 kb
Host smart-1017fc33-3af6-4643-9ef6-472ba44c0fe0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156884047 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.1156884047
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.1768268383
Short name T1070
Test name
Test status
Simulation time 232573457 ps
CPU time 1.17 seconds
Started Jul 06 05:13:19 PM PDT 24
Finished Jul 06 05:13:21 PM PDT 24
Peak memory 206844 kb
Host smart-3fc8120c-c177-4172-9040-33ac9ed54453
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768268383 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.1768268383
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.3224293094
Short name T1002
Test name
Test status
Simulation time 37510909 ps
CPU time 2.04 seconds
Started Jul 06 05:13:20 PM PDT 24
Finished Jul 06 05:13:23 PM PDT 24
Peak memory 206920 kb
Host smart-69713862-85eb-4407-bff0-65fcb4fbc66b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224293094 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.3224293094
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.2127895490
Short name T1004
Test name
Test status
Simulation time 25686879 ps
CPU time 0.86 seconds
Started Jul 06 05:13:18 PM PDT 24
Finished Jul 06 05:13:20 PM PDT 24
Peak memory 206844 kb
Host smart-f358f0be-4c4f-47b1-89da-79fead8434c0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127895490 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.2127895490
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.3782784667
Short name T1027
Test name
Test status
Simulation time 28508022 ps
CPU time 1.3 seconds
Started Jul 06 05:13:18 PM PDT 24
Finished Jul 06 05:13:24 PM PDT 24
Peak memory 215240 kb
Host smart-7bc638ef-e575-4109-a825-59fce1594e69
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782784667 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.3782784667
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.3706868216
Short name T1053
Test name
Test status
Simulation time 22134951 ps
CPU time 0.86 seconds
Started Jul 06 05:13:10 PM PDT 24
Finished Jul 06 05:13:11 PM PDT 24
Peak memory 206976 kb
Host smart-8e89fb3e-05af-4b69-a5b0-bc89993342e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706868216 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.3706868216
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.2963978358
Short name T1126
Test name
Test status
Simulation time 22404607 ps
CPU time 0.84 seconds
Started Jul 06 05:13:06 PM PDT 24
Finished Jul 06 05:13:07 PM PDT 24
Peak memory 206848 kb
Host smart-f8499330-eee9-4e55-aa7a-732919fcc952
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963978358 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.2963978358
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.3161254717
Short name T275
Test name
Test status
Simulation time 35618690 ps
CPU time 1.07 seconds
Started Jul 06 05:13:18 PM PDT 24
Finished Jul 06 05:13:20 PM PDT 24
Peak memory 206884 kb
Host smart-2c3ec778-1dbd-46c2-ad24-666802369162
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161254717 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.3161254717
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.1716410639
Short name T1056
Test name
Test status
Simulation time 137813284 ps
CPU time 2.54 seconds
Started Jul 06 05:13:18 PM PDT 24
Finished Jul 06 05:13:22 PM PDT 24
Peak memory 215160 kb
Host smart-7268537c-07ce-46fa-81d3-616ff2dcadb7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716410639 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.1716410639
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.3049345410
Short name T307
Test name
Test status
Simulation time 129917545 ps
CPU time 2.6 seconds
Started Jul 06 05:13:06 PM PDT 24
Finished Jul 06 05:13:09 PM PDT 24
Peak memory 207104 kb
Host smart-d9fe6dd6-4974-4535-942c-c9341f7fd353
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049345410 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.3049345410
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.1292937350
Short name T1064
Test name
Test status
Simulation time 12628915 ps
CPU time 0.89 seconds
Started Jul 06 05:13:43 PM PDT 24
Finished Jul 06 05:13:50 PM PDT 24
Peak memory 206868 kb
Host smart-4fd4ee86-a5ce-43df-a9e0-9e66d8bf5626
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292937350 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.1292937350
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.2229843835
Short name T1041
Test name
Test status
Simulation time 13851339 ps
CPU time 0.78 seconds
Started Jul 06 05:13:40 PM PDT 24
Finished Jul 06 05:13:41 PM PDT 24
Peak memory 206696 kb
Host smart-90a33f7a-0e54-4991-a193-20ac344de882
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229843835 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.2229843835
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.4151294372
Short name T1095
Test name
Test status
Simulation time 20338868 ps
CPU time 0.82 seconds
Started Jul 06 05:13:42 PM PDT 24
Finished Jul 06 05:13:43 PM PDT 24
Peak memory 206600 kb
Host smart-52edd72d-3d0d-4d2b-98ee-0b211da9e975
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151294372 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.4151294372
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.263953161
Short name T1108
Test name
Test status
Simulation time 15192332 ps
CPU time 0.87 seconds
Started Jul 06 05:13:47 PM PDT 24
Finished Jul 06 05:13:48 PM PDT 24
Peak memory 206848 kb
Host smart-8ca27f98-79b0-477c-acbc-19a59b3f1859
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263953161 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.263953161
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.100282833
Short name T1022
Test name
Test status
Simulation time 15262694 ps
CPU time 0.88 seconds
Started Jul 06 05:13:34 PM PDT 24
Finished Jul 06 05:13:35 PM PDT 24
Peak memory 206856 kb
Host smart-644d008f-abfa-4707-9384-593d520975ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100282833 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.100282833
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.3640307291
Short name T1096
Test name
Test status
Simulation time 14974540 ps
CPU time 0.88 seconds
Started Jul 06 05:13:40 PM PDT 24
Finished Jul 06 05:13:41 PM PDT 24
Peak memory 206872 kb
Host smart-e8e4285e-2fc1-4d9d-afdc-c510235b8fb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640307291 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.3640307291
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.1132179164
Short name T1050
Test name
Test status
Simulation time 13981836 ps
CPU time 0.91 seconds
Started Jul 06 05:13:36 PM PDT 24
Finished Jul 06 05:13:38 PM PDT 24
Peak memory 206912 kb
Host smart-349638cc-8147-43a9-9f94-7299e7b4b077
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132179164 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.1132179164
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.107228474
Short name T1036
Test name
Test status
Simulation time 15271161 ps
CPU time 0.98 seconds
Started Jul 06 05:13:39 PM PDT 24
Finished Jul 06 05:13:40 PM PDT 24
Peak memory 206900 kb
Host smart-a090d33b-f6ef-45ce-a307-d689615a3f45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107228474 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.107228474
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.3496412830
Short name T1033
Test name
Test status
Simulation time 14991854 ps
CPU time 0.87 seconds
Started Jul 06 05:13:35 PM PDT 24
Finished Jul 06 05:13:36 PM PDT 24
Peak memory 206904 kb
Host smart-8ce974be-2221-4122-9d74-f125d8d31424
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496412830 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.3496412830
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.196686816
Short name T1112
Test name
Test status
Simulation time 88280254 ps
CPU time 0.81 seconds
Started Jul 06 05:13:40 PM PDT 24
Finished Jul 06 05:13:41 PM PDT 24
Peak memory 206904 kb
Host smart-0be79d25-d359-465c-a67c-3ed96eb204fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196686816 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.196686816
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.1194180852
Short name T1037
Test name
Test status
Simulation time 31911289 ps
CPU time 1.29 seconds
Started Jul 06 05:13:11 PM PDT 24
Finished Jul 06 05:13:13 PM PDT 24
Peak memory 215332 kb
Host smart-465369de-91e4-4a32-98d6-68eb71c8de1b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194180852 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.1194180852
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.1691294550
Short name T1005
Test name
Test status
Simulation time 82420505 ps
CPU time 0.86 seconds
Started Jul 06 05:13:07 PM PDT 24
Finished Jul 06 05:13:09 PM PDT 24
Peak memory 206876 kb
Host smart-b4c657ba-a03b-417f-af57-0092ed2606a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691294550 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.1691294550
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.150107926
Short name T1120
Test name
Test status
Simulation time 15114448 ps
CPU time 0.96 seconds
Started Jul 06 05:13:05 PM PDT 24
Finished Jul 06 05:13:07 PM PDT 24
Peak memory 206868 kb
Host smart-8a25ad03-7a1e-4433-bab8-fa7a846d16d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150107926 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.150107926
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.241948178
Short name T283
Test name
Test status
Simulation time 46809270 ps
CPU time 1.15 seconds
Started Jul 06 05:13:13 PM PDT 24
Finished Jul 06 05:13:15 PM PDT 24
Peak memory 206980 kb
Host smart-a1de6b6b-f4c5-47bd-a1cd-d32d5ecf52fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241948178 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_out
standing.241948178
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.2579519651
Short name T1049
Test name
Test status
Simulation time 38927351 ps
CPU time 1.69 seconds
Started Jul 06 05:13:08 PM PDT 24
Finished Jul 06 05:13:10 PM PDT 24
Peak memory 215272 kb
Host smart-a4034833-fee6-4862-9c24-a54ec367110f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579519651 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.2579519651
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.4096247428
Short name T308
Test name
Test status
Simulation time 287210272 ps
CPU time 2.17 seconds
Started Jul 06 05:13:08 PM PDT 24
Finished Jul 06 05:13:10 PM PDT 24
Peak memory 207016 kb
Host smart-3515e595-fb0d-4239-b910-a9895169d20a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096247428 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.4096247428
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.4113812983
Short name T1075
Test name
Test status
Simulation time 94578097 ps
CPU time 1.19 seconds
Started Jul 06 05:13:10 PM PDT 24
Finished Jul 06 05:13:12 PM PDT 24
Peak memory 215208 kb
Host smart-ff64cfb7-4810-4930-97ad-7045439cdcb4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113812983 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.4113812983
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.1458763883
Short name T1031
Test name
Test status
Simulation time 17225439 ps
CPU time 0.82 seconds
Started Jul 06 05:13:13 PM PDT 24
Finished Jul 06 05:13:14 PM PDT 24
Peak memory 206740 kb
Host smart-aa835981-e15f-4f9b-819e-e5c350aeee68
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458763883 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.1458763883
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.3759539762
Short name T1106
Test name
Test status
Simulation time 70552284 ps
CPU time 0.86 seconds
Started Jul 06 05:13:12 PM PDT 24
Finished Jul 06 05:13:19 PM PDT 24
Peak memory 206856 kb
Host smart-dca3f4d4-089f-4ec7-bfa7-dea73d8912ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759539762 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.3759539762
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.3329397324
Short name T277
Test name
Test status
Simulation time 23248220 ps
CPU time 1.16 seconds
Started Jul 06 05:13:18 PM PDT 24
Finished Jul 06 05:13:20 PM PDT 24
Peak memory 206884 kb
Host smart-ccb57879-8dec-4db8-bed9-f27778d4a10c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329397324 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.3329397324
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.3422774620
Short name T1019
Test name
Test status
Simulation time 476327676 ps
CPU time 3.88 seconds
Started Jul 06 05:13:10 PM PDT 24
Finished Jul 06 05:13:15 PM PDT 24
Peak memory 215168 kb
Host smart-ffd27ff8-8ff1-4faf-857b-05cae7224b09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422774620 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.3422774620
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.243629671
Short name T292
Test name
Test status
Simulation time 40834426 ps
CPU time 1.47 seconds
Started Jul 06 05:13:17 PM PDT 24
Finished Jul 06 05:13:19 PM PDT 24
Peak memory 207036 kb
Host smart-8f5e4cce-8dc1-45fe-999f-5c21985937b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243629671 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.243629671
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2832442012
Short name T1040
Test name
Test status
Simulation time 25428356 ps
CPU time 1.24 seconds
Started Jul 06 05:13:10 PM PDT 24
Finished Jul 06 05:13:12 PM PDT 24
Peak memory 217152 kb
Host smart-ae5b5b92-099f-43d2-a0f0-30ca851bcb34
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832442012 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.2832442012
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.2531597871
Short name T261
Test name
Test status
Simulation time 22793521 ps
CPU time 0.84 seconds
Started Jul 06 05:13:18 PM PDT 24
Finished Jul 06 05:13:20 PM PDT 24
Peak memory 206924 kb
Host smart-d01b1222-64bd-4233-91bf-cfc53aa896c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531597871 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.2531597871
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.3292650959
Short name T1113
Test name
Test status
Simulation time 45992241 ps
CPU time 0.81 seconds
Started Jul 06 05:13:19 PM PDT 24
Finished Jul 06 05:13:21 PM PDT 24
Peak memory 206872 kb
Host smart-a17719ab-706d-4854-bb17-1c85e4650b1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292650959 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.3292650959
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.3565319234
Short name T1055
Test name
Test status
Simulation time 76132556 ps
CPU time 0.94 seconds
Started Jul 06 05:13:11 PM PDT 24
Finished Jul 06 05:13:12 PM PDT 24
Peak memory 206948 kb
Host smart-7cd21829-774b-4c75-8554-5a0dc75a2b86
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565319234 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.3565319234
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.2984634354
Short name T1100
Test name
Test status
Simulation time 91127525 ps
CPU time 2.5 seconds
Started Jul 06 05:13:12 PM PDT 24
Finished Jul 06 05:13:15 PM PDT 24
Peak memory 215176 kb
Host smart-55afc128-013c-4b3b-8fe8-8e014cad5d17
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984634354 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.2984634354
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.3954331891
Short name T1077
Test name
Test status
Simulation time 321256604 ps
CPU time 2.42 seconds
Started Jul 06 05:13:13 PM PDT 24
Finished Jul 06 05:13:15 PM PDT 24
Peak memory 215164 kb
Host smart-43cad20d-1837-4df6-8216-917557c3d93b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954331891 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.3954331891
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.4076987544
Short name T1007
Test name
Test status
Simulation time 55455154 ps
CPU time 1.49 seconds
Started Jul 06 05:13:11 PM PDT 24
Finished Jul 06 05:13:13 PM PDT 24
Peak memory 215220 kb
Host smart-18378f97-4c14-4526-b946-0f5ed88fb15e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076987544 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.4076987544
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.1775677657
Short name T274
Test name
Test status
Simulation time 19979657 ps
CPU time 0.83 seconds
Started Jul 06 05:13:10 PM PDT 24
Finished Jul 06 05:13:11 PM PDT 24
Peak memory 206744 kb
Host smart-ff859b5c-2bcf-41b5-ae35-05d16e22a184
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775677657 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.1775677657
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.3019194323
Short name T1117
Test name
Test status
Simulation time 10914778 ps
CPU time 0.83 seconds
Started Jul 06 05:13:16 PM PDT 24
Finished Jul 06 05:13:17 PM PDT 24
Peak memory 206864 kb
Host smart-25b02a7b-547f-45ac-9efc-9ed1ba268162
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019194323 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.3019194323
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.2667371157
Short name T1101
Test name
Test status
Simulation time 14859977 ps
CPU time 1 seconds
Started Jul 06 05:13:11 PM PDT 24
Finished Jul 06 05:13:12 PM PDT 24
Peak memory 206908 kb
Host smart-4c42b632-7cbb-4e7e-a4ae-5aa4ff67b184
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667371157 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.2667371157
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.2783260654
Short name T1089
Test name
Test status
Simulation time 24963004 ps
CPU time 1.64 seconds
Started Jul 06 05:13:12 PM PDT 24
Finished Jul 06 05:13:14 PM PDT 24
Peak memory 215236 kb
Host smart-745d38eb-5281-41f2-b11f-333e52f4b393
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783260654 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.2783260654
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.1043820490
Short name T305
Test name
Test status
Simulation time 330077980 ps
CPU time 2.49 seconds
Started Jul 06 05:13:10 PM PDT 24
Finished Jul 06 05:13:14 PM PDT 24
Peak memory 206984 kb
Host smart-72ab9c96-9785-492f-9edf-b3c458377a57
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043820490 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.1043820490
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.3185889513
Short name T1032
Test name
Test status
Simulation time 45023306 ps
CPU time 1.44 seconds
Started Jul 06 05:13:20 PM PDT 24
Finished Jul 06 05:13:23 PM PDT 24
Peak memory 215228 kb
Host smart-af6c4791-dd66-4858-b43e-99ecd0ad9222
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185889513 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.3185889513
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.2203062049
Short name T265
Test name
Test status
Simulation time 35617452 ps
CPU time 0.84 seconds
Started Jul 06 05:13:07 PM PDT 24
Finished Jul 06 05:13:09 PM PDT 24
Peak memory 206948 kb
Host smart-51c51da7-29e0-4176-8915-003f01b671d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203062049 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.2203062049
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.797240051
Short name T1061
Test name
Test status
Simulation time 26485625 ps
CPU time 0.85 seconds
Started Jul 06 05:13:20 PM PDT 24
Finished Jul 06 05:13:22 PM PDT 24
Peak memory 206836 kb
Host smart-6cfc9c27-8d3e-42ad-9109-113c42c7c91f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797240051 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.797240051
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.2628592641
Short name T1086
Test name
Test status
Simulation time 18636500 ps
CPU time 1.16 seconds
Started Jul 06 05:13:17 PM PDT 24
Finished Jul 06 05:13:19 PM PDT 24
Peak memory 206972 kb
Host smart-3be5c6f4-badc-4618-b320-c3878ee82e0d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628592641 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.2628592641
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.2350382171
Short name T1060
Test name
Test status
Simulation time 45169561 ps
CPU time 2.62 seconds
Started Jul 06 05:13:09 PM PDT 24
Finished Jul 06 05:13:12 PM PDT 24
Peak memory 223440 kb
Host smart-190e185e-bf99-499a-a7bd-a587e9b10b02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350382171 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.2350382171
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/default/0.edn_alert.3259981137
Short name T808
Test name
Test status
Simulation time 36773746 ps
CPU time 1.21 seconds
Started Jul 06 06:26:48 PM PDT 24
Finished Jul 06 06:26:50 PM PDT 24
Peak memory 220032 kb
Host smart-3de5f55c-5c0c-414a-9523-c6755f2f9197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259981137 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.3259981137
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.3994035178
Short name T933
Test name
Test status
Simulation time 22211833 ps
CPU time 1.04 seconds
Started Jul 06 06:26:51 PM PDT 24
Finished Jul 06 06:26:53 PM PDT 24
Peak memory 207104 kb
Host smart-149cb214-2690-48bc-b137-fc1233e95bbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994035178 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.3994035178
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.1500328779
Short name T835
Test name
Test status
Simulation time 31046899 ps
CPU time 0.85 seconds
Started Jul 06 06:26:50 PM PDT 24
Finished Jul 06 06:26:51 PM PDT 24
Peak memory 216560 kb
Host smart-29c7d6c2-dddb-46db-a55b-fb95a2617530
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500328779 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.1500328779
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.3238986834
Short name T122
Test name
Test status
Simulation time 47295431 ps
CPU time 1.13 seconds
Started Jul 06 06:26:49 PM PDT 24
Finished Jul 06 06:26:50 PM PDT 24
Peak memory 217192 kb
Host smart-dc78dfbc-523b-4c91-97d7-7aab294ff813
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238986834 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.3238986834
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.1418414634
Short name T14
Test name
Test status
Simulation time 31596790 ps
CPU time 1.09 seconds
Started Jul 06 06:26:46 PM PDT 24
Finished Jul 06 06:26:48 PM PDT 24
Peak memory 224160 kb
Host smart-28ddf248-f3ca-455e-bef9-f93ae3c4d862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418414634 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.1418414634
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.262995121
Short name T689
Test name
Test status
Simulation time 60275897 ps
CPU time 1.75 seconds
Started Jul 06 06:26:46 PM PDT 24
Finished Jul 06 06:26:48 PM PDT 24
Peak memory 218792 kb
Host smart-3f65e31e-87f4-44c9-8b5d-60065e78e2fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262995121 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.262995121
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.105966913
Short name T565
Test name
Test status
Simulation time 38487721 ps
CPU time 0.9 seconds
Started Jul 06 06:26:46 PM PDT 24
Finished Jul 06 06:26:47 PM PDT 24
Peak memory 215996 kb
Host smart-1c59ee16-1418-4b57-8cfe-4f099fd25fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105966913 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.105966913
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_smoke.1211249714
Short name T871
Test name
Test status
Simulation time 19292896 ps
CPU time 0.99 seconds
Started Jul 06 06:26:46 PM PDT 24
Finished Jul 06 06:26:47 PM PDT 24
Peak memory 215624 kb
Host smart-3243fe2c-d6e9-4816-9a20-820b97fbb2b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211249714 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.1211249714
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.2556318679
Short name T538
Test name
Test status
Simulation time 153203509 ps
CPU time 1.19 seconds
Started Jul 06 06:26:44 PM PDT 24
Finished Jul 06 06:26:45 PM PDT 24
Peak memory 215596 kb
Host smart-595ed60e-7e43-4404-a3b3-e56d344a05e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556318679 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.2556318679
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_alert_test.644543775
Short name T433
Test name
Test status
Simulation time 18857052 ps
CPU time 0.93 seconds
Started Jul 06 06:26:49 PM PDT 24
Finished Jul 06 06:26:51 PM PDT 24
Peak memory 207084 kb
Host smart-6d07f630-ea28-400d-9de5-62d80ccfaa68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644543775 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.644543775
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.120710471
Short name T827
Test name
Test status
Simulation time 16720654 ps
CPU time 0.85 seconds
Started Jul 06 06:26:52 PM PDT 24
Finished Jul 06 06:26:53 PM PDT 24
Peak memory 215784 kb
Host smart-f2c29e84-3a1a-4d27-8c8d-196f689c29e7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120710471 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.120710471
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.90736356
Short name T20
Test name
Test status
Simulation time 43579168 ps
CPU time 1.02 seconds
Started Jul 06 06:26:50 PM PDT 24
Finished Jul 06 06:26:51 PM PDT 24
Peak memory 217040 kb
Host smart-95d284be-fc35-41d8-ba14-0e49ddf3e082
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90736356 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disa
ble_auto_req_mode.90736356
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.4180641180
Short name T66
Test name
Test status
Simulation time 22283897 ps
CPU time 1.22 seconds
Started Jul 06 06:26:49 PM PDT 24
Finished Jul 06 06:26:51 PM PDT 24
Peak memory 224316 kb
Host smart-a44f9d40-4ee4-4146-b60b-d95f6bd80cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180641180 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.4180641180
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.4047707490
Short name T667
Test name
Test status
Simulation time 115199663 ps
CPU time 1.29 seconds
Started Jul 06 06:26:49 PM PDT 24
Finished Jul 06 06:26:51 PM PDT 24
Peak memory 217808 kb
Host smart-ece0d9cb-d4d4-42ab-8ad8-7939f2e02297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047707490 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.4047707490
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_sec_cm.3731155053
Short name T73
Test name
Test status
Simulation time 463597343 ps
CPU time 7.83 seconds
Started Jul 06 06:26:50 PM PDT 24
Finished Jul 06 06:26:58 PM PDT 24
Peak memory 237764 kb
Host smart-2d87dd2d-efc6-44e8-9932-d676dae95a89
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731155053 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.3731155053
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.109450738
Short name T520
Test name
Test status
Simulation time 20107041 ps
CPU time 0.96 seconds
Started Jul 06 06:26:49 PM PDT 24
Finished Jul 06 06:26:51 PM PDT 24
Peak memory 215664 kb
Host smart-539261a6-fb99-481a-82f8-d786df63714b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109450738 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.109450738
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.3640476136
Short name T832
Test name
Test status
Simulation time 73742271965 ps
CPU time 870.97 seconds
Started Jul 06 06:26:48 PM PDT 24
Finished Jul 06 06:41:20 PM PDT 24
Peak memory 224092 kb
Host smart-cb8638ff-3d06-4464-92c8-fb458fa6268d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640476136 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.3640476136
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.3386379487
Short name T157
Test name
Test status
Simulation time 107201370 ps
CPU time 1.25 seconds
Started Jul 06 06:27:08 PM PDT 24
Finished Jul 06 06:27:10 PM PDT 24
Peak memory 218852 kb
Host smart-5964bd49-2783-4209-ad40-a6d433bd1471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386379487 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.3386379487
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_err.1443017059
Short name T116
Test name
Test status
Simulation time 89245894 ps
CPU time 1.04 seconds
Started Jul 06 06:27:22 PM PDT 24
Finished Jul 06 06:27:23 PM PDT 24
Peak memory 220048 kb
Host smart-07b274d8-9d92-4da4-bc43-9185f67e46c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443017059 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.1443017059
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.3814393763
Short name T723
Test name
Test status
Simulation time 221624977 ps
CPU time 2.77 seconds
Started Jul 06 06:27:06 PM PDT 24
Finished Jul 06 06:27:10 PM PDT 24
Peak memory 215672 kb
Host smart-7467dcf6-d62c-4776-a29a-187dfc9cd13a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814393763 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.3814393763
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.1267935460
Short name T859
Test name
Test status
Simulation time 70868042 ps
CPU time 0.9 seconds
Started Jul 06 06:27:08 PM PDT 24
Finished Jul 06 06:27:10 PM PDT 24
Peak memory 215680 kb
Host smart-cca17e8e-5e3e-43be-b214-5f7e785e30f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267935460 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.1267935460
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.1003992625
Short name T432
Test name
Test status
Simulation time 24321826 ps
CPU time 1.03 seconds
Started Jul 06 06:27:05 PM PDT 24
Finished Jul 06 06:27:07 PM PDT 24
Peak memory 215568 kb
Host smart-56b651dd-141f-44d6-b489-c5b59c4f3a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003992625 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.1003992625
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.909494665
Short name T856
Test name
Test status
Simulation time 113091372 ps
CPU time 2.57 seconds
Started Jul 06 06:27:07 PM PDT 24
Finished Jul 06 06:27:10 PM PDT 24
Peak memory 220604 kb
Host smart-944c713e-1e46-4076-afe5-de16dfd7574f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909494665 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.909494665
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.3013490215
Short name T234
Test name
Test status
Simulation time 165020430163 ps
CPU time 371.86 seconds
Started Jul 06 06:27:08 PM PDT 24
Finished Jul 06 06:33:20 PM PDT 24
Peak memory 220040 kb
Host smart-2e35abab-14fe-409b-ba20-8811eb823c78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013490215 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.3013490215
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_alert.3963809312
Short name T242
Test name
Test status
Simulation time 71495485 ps
CPU time 1.07 seconds
Started Jul 06 06:28:34 PM PDT 24
Finished Jul 06 06:28:36 PM PDT 24
Peak memory 218960 kb
Host smart-8087bfb2-11fd-4110-ba8a-53786f04d172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963809312 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_alert.3963809312
Directory /workspace/100.edn_alert/latest

Test location /workspace/coverage/default/100.edn_genbits.3415623449
Short name T570
Test name
Test status
Simulation time 222068898 ps
CPU time 2.43 seconds
Started Jul 06 06:28:35 PM PDT 24
Finished Jul 06 06:28:38 PM PDT 24
Peak memory 219612 kb
Host smart-63f86bc6-3bea-454b-b40a-6bd4d8263a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415623449 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.3415623449
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_alert.3397981207
Short name T104
Test name
Test status
Simulation time 42820072 ps
CPU time 1.14 seconds
Started Jul 06 06:28:38 PM PDT 24
Finished Jul 06 06:28:39 PM PDT 24
Peak memory 220420 kb
Host smart-f15f31bb-ea26-4bd1-8890-d46343bc9083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397981207 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_alert.3397981207
Directory /workspace/101.edn_alert/latest

Test location /workspace/coverage/default/101.edn_genbits.4222846417
Short name T76
Test name
Test status
Simulation time 44462777 ps
CPU time 1.73 seconds
Started Jul 06 06:28:37 PM PDT 24
Finished Jul 06 06:28:39 PM PDT 24
Peak memory 219000 kb
Host smart-75ca18ac-7a8f-427b-a7e2-1141ae0999d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222846417 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.4222846417
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_alert.4004278544
Short name T500
Test name
Test status
Simulation time 27346385 ps
CPU time 1.21 seconds
Started Jul 06 06:28:35 PM PDT 24
Finished Jul 06 06:28:36 PM PDT 24
Peak memory 219712 kb
Host smart-7e4e70c8-5646-4a36-9499-08c152f0a06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004278544 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_alert.4004278544
Directory /workspace/102.edn_alert/latest

Test location /workspace/coverage/default/102.edn_genbits.3025284518
Short name T686
Test name
Test status
Simulation time 37793585 ps
CPU time 1.41 seconds
Started Jul 06 06:28:34 PM PDT 24
Finished Jul 06 06:28:36 PM PDT 24
Peak memory 218676 kb
Host smart-a0e0f378-6bac-4149-bb10-b9a2ada860b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025284518 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.3025284518
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_alert.3551485173
Short name T786
Test name
Test status
Simulation time 37519727 ps
CPU time 1.34 seconds
Started Jul 06 06:28:38 PM PDT 24
Finished Jul 06 06:28:39 PM PDT 24
Peak memory 220100 kb
Host smart-82e1a334-d418-43fe-b6f4-ad08eb423aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551485173 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_alert.3551485173
Directory /workspace/103.edn_alert/latest

Test location /workspace/coverage/default/103.edn_genbits.939413912
Short name T384
Test name
Test status
Simulation time 28189293 ps
CPU time 1.26 seconds
Started Jul 06 06:28:37 PM PDT 24
Finished Jul 06 06:28:38 PM PDT 24
Peak memory 218756 kb
Host smart-98467d41-1294-4307-b27d-ecc5ad8feef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939413912 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.939413912
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_alert.2053404225
Short name T507
Test name
Test status
Simulation time 50829820 ps
CPU time 1.17 seconds
Started Jul 06 06:28:39 PM PDT 24
Finished Jul 06 06:28:40 PM PDT 24
Peak memory 220060 kb
Host smart-4272e72a-48d4-4226-9eff-e70d6877714a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053404225 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_alert.2053404225
Directory /workspace/104.edn_alert/latest

Test location /workspace/coverage/default/104.edn_genbits.2539976613
Short name T445
Test name
Test status
Simulation time 118229836 ps
CPU time 1.37 seconds
Started Jul 06 06:28:37 PM PDT 24
Finished Jul 06 06:28:39 PM PDT 24
Peak memory 219480 kb
Host smart-e788c6b3-0f6f-4bf9-9305-3e5e1ecfda8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539976613 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.2539976613
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_genbits.2882809357
Short name T25
Test name
Test status
Simulation time 86627906 ps
CPU time 2.79 seconds
Started Jul 06 06:28:43 PM PDT 24
Finished Jul 06 06:28:47 PM PDT 24
Peak memory 220112 kb
Host smart-6899f176-b3dd-40f0-b1d8-cc29cd7cca41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882809357 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.2882809357
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_alert.3535983638
Short name T464
Test name
Test status
Simulation time 22949872 ps
CPU time 1.23 seconds
Started Jul 06 06:28:40 PM PDT 24
Finished Jul 06 06:28:41 PM PDT 24
Peak memory 220064 kb
Host smart-f366bdf1-0707-4cf2-b6bb-1961c2d8aa9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535983638 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_alert.3535983638
Directory /workspace/106.edn_alert/latest

Test location /workspace/coverage/default/106.edn_genbits.1773684861
Short name T903
Test name
Test status
Simulation time 70749298 ps
CPU time 1.73 seconds
Started Jul 06 06:28:36 PM PDT 24
Finished Jul 06 06:28:38 PM PDT 24
Peak memory 218012 kb
Host smart-b0f989f4-b8d4-4135-90d6-a305a6f9d35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773684861 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.1773684861
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_alert.1032253522
Short name T489
Test name
Test status
Simulation time 40441925 ps
CPU time 1.2 seconds
Started Jul 06 06:28:42 PM PDT 24
Finished Jul 06 06:28:43 PM PDT 24
Peak memory 218840 kb
Host smart-93bda6df-c5b4-443b-a15d-1057853f2b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032253522 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_alert.1032253522
Directory /workspace/107.edn_alert/latest

Test location /workspace/coverage/default/107.edn_genbits.3450728896
Short name T302
Test name
Test status
Simulation time 38295266 ps
CPU time 1.09 seconds
Started Jul 06 06:28:41 PM PDT 24
Finished Jul 06 06:28:42 PM PDT 24
Peak memory 217712 kb
Host smart-893de8b5-d796-4977-80dc-ff65cad5d189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450728896 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.3450728896
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_alert.2277495817
Short name T28
Test name
Test status
Simulation time 24235919 ps
CPU time 1.17 seconds
Started Jul 06 06:28:39 PM PDT 24
Finished Jul 06 06:28:41 PM PDT 24
Peak memory 220048 kb
Host smart-00d85154-104d-4cb2-b92b-e55f02f4ff06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277495817 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_alert.2277495817
Directory /workspace/108.edn_alert/latest

Test location /workspace/coverage/default/108.edn_genbits.1334932092
Short name T443
Test name
Test status
Simulation time 51829369 ps
CPU time 1.26 seconds
Started Jul 06 06:28:41 PM PDT 24
Finished Jul 06 06:28:43 PM PDT 24
Peak memory 217484 kb
Host smart-25b8b0dc-cd30-4689-812e-57e85a67d455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334932092 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.1334932092
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_alert.3614988444
Short name T125
Test name
Test status
Simulation time 92744540 ps
CPU time 1.28 seconds
Started Jul 06 06:28:43 PM PDT 24
Finished Jul 06 06:28:44 PM PDT 24
Peak memory 216008 kb
Host smart-7622c942-c47c-421c-861a-ec48448e479d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614988444 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_alert.3614988444
Directory /workspace/109.edn_alert/latest

Test location /workspace/coverage/default/109.edn_genbits.2275855500
Short name T338
Test name
Test status
Simulation time 37615135 ps
CPU time 1.09 seconds
Started Jul 06 06:28:38 PM PDT 24
Finished Jul 06 06:28:40 PM PDT 24
Peak memory 218912 kb
Host smart-93dfca37-a10a-4754-9994-2527701292b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275855500 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.2275855500
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.3387900299
Short name T758
Test name
Test status
Simulation time 45217224 ps
CPU time 1.2 seconds
Started Jul 06 06:27:09 PM PDT 24
Finished Jul 06 06:27:11 PM PDT 24
Peak memory 219524 kb
Host smart-2c0c00ba-41ca-494e-9e44-77a0b1d3a610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387900299 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.3387900299
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.745595375
Short name T950
Test name
Test status
Simulation time 15296876 ps
CPU time 0.91 seconds
Started Jul 06 06:27:12 PM PDT 24
Finished Jul 06 06:27:13 PM PDT 24
Peak memory 215512 kb
Host smart-95fd892b-f074-4425-9e74-0d9d652ef19d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745595375 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.745595375
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_err.202706457
Short name T121
Test name
Test status
Simulation time 21553732 ps
CPU time 1.05 seconds
Started Jul 06 06:27:11 PM PDT 24
Finished Jul 06 06:27:12 PM PDT 24
Peak memory 220068 kb
Host smart-fa751648-0910-45fc-a053-cac9de9fdbcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202706457 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.202706457
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.189779302
Short name T747
Test name
Test status
Simulation time 52599494 ps
CPU time 1.65 seconds
Started Jul 06 06:27:11 PM PDT 24
Finished Jul 06 06:27:13 PM PDT 24
Peak memory 220360 kb
Host smart-a3c3d876-b99d-4ab0-b794-88c64cd56e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189779302 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.189779302
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.316659939
Short name T955
Test name
Test status
Simulation time 29336316 ps
CPU time 0.88 seconds
Started Jul 06 06:27:10 PM PDT 24
Finished Jul 06 06:27:11 PM PDT 24
Peak memory 216220 kb
Host smart-cb04084a-0901-444a-909e-45a467ab0a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316659939 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.316659939
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.1956915738
Short name T543
Test name
Test status
Simulation time 17176692 ps
CPU time 1.05 seconds
Started Jul 06 06:27:10 PM PDT 24
Finished Jul 06 06:27:11 PM PDT 24
Peak memory 215672 kb
Host smart-1856e3a6-b42f-4ec4-8231-98abcd2710fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956915738 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.1956915738
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.2582507356
Short name T592
Test name
Test status
Simulation time 188560642 ps
CPU time 3.78 seconds
Started Jul 06 06:27:09 PM PDT 24
Finished Jul 06 06:27:13 PM PDT 24
Peak memory 218736 kb
Host smart-c0e98ceb-6401-465b-802a-807c0d71579d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582507356 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.2582507356
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.2038919851
Short name T237
Test name
Test status
Simulation time 64077876101 ps
CPU time 680.41 seconds
Started Jul 06 06:27:13 PM PDT 24
Finished Jul 06 06:38:34 PM PDT 24
Peak memory 219992 kb
Host smart-bef7b6f1-e1d0-4cf6-917d-34c8e9d7168c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038919851 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.2038919851
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_alert.3828049491
Short name T317
Test name
Test status
Simulation time 118851481 ps
CPU time 1.1 seconds
Started Jul 06 06:28:39 PM PDT 24
Finished Jul 06 06:28:40 PM PDT 24
Peak memory 221120 kb
Host smart-83269d97-78f2-4dc9-ba46-a34b7bfdbc46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828049491 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_alert.3828049491
Directory /workspace/110.edn_alert/latest

Test location /workspace/coverage/default/110.edn_genbits.1725108698
Short name T846
Test name
Test status
Simulation time 41346950 ps
CPU time 1.91 seconds
Started Jul 06 06:28:41 PM PDT 24
Finished Jul 06 06:28:43 PM PDT 24
Peak memory 218664 kb
Host smart-abdbe180-7541-4875-ae8c-c7c88a6d72f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725108698 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.1725108698
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_alert.2147761998
Short name T482
Test name
Test status
Simulation time 23831453 ps
CPU time 1.21 seconds
Started Jul 06 06:28:42 PM PDT 24
Finished Jul 06 06:28:44 PM PDT 24
Peak memory 219548 kb
Host smart-aa2f79c5-b020-4508-9968-95db58bcb3f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147761998 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_alert.2147761998
Directory /workspace/111.edn_alert/latest

Test location /workspace/coverage/default/111.edn_genbits.3145547970
Short name T455
Test name
Test status
Simulation time 47134832 ps
CPU time 1.54 seconds
Started Jul 06 06:28:38 PM PDT 24
Finished Jul 06 06:28:40 PM PDT 24
Peak memory 219164 kb
Host smart-aae63ff5-b368-4f23-bb68-3205968decb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145547970 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.3145547970
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_alert.186380708
Short name T463
Test name
Test status
Simulation time 169399509 ps
CPU time 1.37 seconds
Started Jul 06 06:28:43 PM PDT 24
Finished Jul 06 06:28:45 PM PDT 24
Peak memory 221084 kb
Host smart-b5abd133-5f31-45e3-b59a-2f6b05e74728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186380708 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_alert.186380708
Directory /workspace/112.edn_alert/latest

Test location /workspace/coverage/default/112.edn_genbits.464575171
Short name T801
Test name
Test status
Simulation time 58574754 ps
CPU time 1.55 seconds
Started Jul 06 06:28:39 PM PDT 24
Finished Jul 06 06:28:41 PM PDT 24
Peak memory 218988 kb
Host smart-217c37fd-9945-4fde-9bd8-c5201e481726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464575171 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.464575171
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_alert.232515070
Short name T705
Test name
Test status
Simulation time 72030099 ps
CPU time 1.17 seconds
Started Jul 06 06:28:40 PM PDT 24
Finished Jul 06 06:28:41 PM PDT 24
Peak memory 220152 kb
Host smart-035a47ab-0c69-4514-ab1d-2b77e152502b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232515070 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_alert.232515070
Directory /workspace/113.edn_alert/latest

Test location /workspace/coverage/default/113.edn_genbits.4216074398
Short name T674
Test name
Test status
Simulation time 40465954 ps
CPU time 1.49 seconds
Started Jul 06 06:28:44 PM PDT 24
Finished Jul 06 06:28:47 PM PDT 24
Peak memory 220024 kb
Host smart-298c4fc0-4df0-4915-af5a-e9e7ae35bafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216074398 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.4216074398
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_alert.4243098685
Short name T890
Test name
Test status
Simulation time 66883619 ps
CPU time 1.18 seconds
Started Jul 06 06:28:43 PM PDT 24
Finished Jul 06 06:28:45 PM PDT 24
Peak memory 219112 kb
Host smart-be2b7629-4611-4033-8103-0518704a09c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243098685 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_alert.4243098685
Directory /workspace/114.edn_alert/latest

Test location /workspace/coverage/default/114.edn_genbits.1176666721
Short name T497
Test name
Test status
Simulation time 39439655 ps
CPU time 1.5 seconds
Started Jul 06 06:28:43 PM PDT 24
Finished Jul 06 06:28:45 PM PDT 24
Peak memory 218964 kb
Host smart-84b9c87f-4ffd-4c2d-93ef-e6ab51c70d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176666721 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.1176666721
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_genbits.1402056186
Short name T591
Test name
Test status
Simulation time 44213483 ps
CPU time 1.16 seconds
Started Jul 06 06:28:39 PM PDT 24
Finished Jul 06 06:28:41 PM PDT 24
Peak memory 220072 kb
Host smart-cb67db85-c84a-4689-a07f-7222823f44f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402056186 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.1402056186
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_alert.1034201055
Short name T719
Test name
Test status
Simulation time 46975839 ps
CPU time 1.27 seconds
Started Jul 06 06:28:45 PM PDT 24
Finished Jul 06 06:28:47 PM PDT 24
Peak memory 219776 kb
Host smart-a5aebeda-7d09-49ee-befc-71a3c41750e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034201055 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_alert.1034201055
Directory /workspace/116.edn_alert/latest

Test location /workspace/coverage/default/116.edn_genbits.3943088332
Short name T724
Test name
Test status
Simulation time 51703029 ps
CPU time 1.66 seconds
Started Jul 06 06:28:44 PM PDT 24
Finished Jul 06 06:28:46 PM PDT 24
Peak memory 218864 kb
Host smart-17552888-56b9-4f0e-8fa9-50c6bc6f475c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943088332 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.3943088332
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_alert.218893572
Short name T496
Test name
Test status
Simulation time 29141525 ps
CPU time 1.27 seconds
Started Jul 06 06:28:42 PM PDT 24
Finished Jul 06 06:28:44 PM PDT 24
Peak memory 221056 kb
Host smart-006f4f9b-7be4-4a9f-9850-b03aac7e6a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218893572 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_alert.218893572
Directory /workspace/117.edn_alert/latest

Test location /workspace/coverage/default/117.edn_genbits.2220815777
Short name T382
Test name
Test status
Simulation time 65605697 ps
CPU time 1.16 seconds
Started Jul 06 06:28:43 PM PDT 24
Finished Jul 06 06:28:45 PM PDT 24
Peak memory 220204 kb
Host smart-10b2344d-3867-45ab-8d9f-5e8947c157f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220815777 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.2220815777
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_alert.15300868
Short name T169
Test name
Test status
Simulation time 38309730 ps
CPU time 1.17 seconds
Started Jul 06 06:28:55 PM PDT 24
Finished Jul 06 06:28:57 PM PDT 24
Peak memory 220020 kb
Host smart-2b2f9ea6-5e84-4b2a-b797-47127ce20cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15300868 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_alert.15300868
Directory /workspace/118.edn_alert/latest

Test location /workspace/coverage/default/118.edn_genbits.4004852146
Short name T483
Test name
Test status
Simulation time 50841337 ps
CPU time 1.4 seconds
Started Jul 06 06:28:54 PM PDT 24
Finished Jul 06 06:28:56 PM PDT 24
Peak memory 217744 kb
Host smart-34ea3dae-074d-407f-8592-4f6300140775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004852146 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.4004852146
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_alert.2264120020
Short name T962
Test name
Test status
Simulation time 65891443 ps
CPU time 1.08 seconds
Started Jul 06 06:28:53 PM PDT 24
Finished Jul 06 06:28:54 PM PDT 24
Peak memory 220196 kb
Host smart-bdecce9b-6f5b-4b9c-a364-ce9d356e0505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264120020 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_alert.2264120020
Directory /workspace/119.edn_alert/latest

Test location /workspace/coverage/default/119.edn_genbits.4131849145
Short name T770
Test name
Test status
Simulation time 87623006 ps
CPU time 2.43 seconds
Started Jul 06 06:28:45 PM PDT 24
Finished Jul 06 06:28:48 PM PDT 24
Peak memory 219420 kb
Host smart-12312f4d-15a2-437b-91e6-3b24e4461237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131849145 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.4131849145
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert_test.2707636720
Short name T636
Test name
Test status
Simulation time 11972207 ps
CPU time 0.91 seconds
Started Jul 06 06:27:14 PM PDT 24
Finished Jul 06 06:27:15 PM PDT 24
Peak memory 207260 kb
Host smart-a71c304f-1b11-4a45-863c-ea7a42f13f00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707636720 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.2707636720
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.3993667607
Short name T838
Test name
Test status
Simulation time 13577833 ps
CPU time 0.9 seconds
Started Jul 06 06:27:20 PM PDT 24
Finished Jul 06 06:27:21 PM PDT 24
Peak memory 215872 kb
Host smart-39c765cf-e535-4ddd-9919-9574b5e27b0f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993667607 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.3993667607
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.3682729779
Short name T49
Test name
Test status
Simulation time 34796666 ps
CPU time 1.08 seconds
Started Jul 06 06:27:14 PM PDT 24
Finished Jul 06 06:27:16 PM PDT 24
Peak memory 217208 kb
Host smart-5a7c1c3e-dd28-4d8a-8f8e-fcbbf16f2384
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682729779 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.3682729779
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.1142208704
Short name T212
Test name
Test status
Simulation time 21447331 ps
CPU time 0.95 seconds
Started Jul 06 06:27:13 PM PDT 24
Finished Jul 06 06:27:14 PM PDT 24
Peak memory 219032 kb
Host smart-a1e7d8c6-6405-4698-b94a-65d04dc73e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142208704 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.1142208704
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.1722088045
Short name T422
Test name
Test status
Simulation time 52218966 ps
CPU time 1.37 seconds
Started Jul 06 06:27:09 PM PDT 24
Finished Jul 06 06:27:10 PM PDT 24
Peak memory 218836 kb
Host smart-ec3461e0-0cb2-4f19-a764-676245da62ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722088045 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.1722088045
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.3855784952
Short name T691
Test name
Test status
Simulation time 34913234 ps
CPU time 0.84 seconds
Started Jul 06 06:27:13 PM PDT 24
Finished Jul 06 06:27:14 PM PDT 24
Peak memory 215564 kb
Host smart-c6875c77-0e16-45be-a535-c2e4aa222161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855784952 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.3855784952
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.2461249090
Short name T806
Test name
Test status
Simulation time 28713932 ps
CPU time 0.94 seconds
Started Jul 06 06:27:21 PM PDT 24
Finished Jul 06 06:27:22 PM PDT 24
Peak memory 207328 kb
Host smart-2e9c17dc-7a33-4dd4-ae81-344bf397536b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461249090 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.2461249090
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.1867341076
Short name T634
Test name
Test status
Simulation time 30420254 ps
CPU time 1.04 seconds
Started Jul 06 06:27:10 PM PDT 24
Finished Jul 06 06:27:11 PM PDT 24
Peak memory 207036 kb
Host smart-f20bae8e-1761-4d75-b6a6-1461d36103eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867341076 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.1867341076
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.2737953712
Short name T45
Test name
Test status
Simulation time 354933010893 ps
CPU time 1828.42 seconds
Started Jul 06 06:27:15 PM PDT 24
Finished Jul 06 06:57:44 PM PDT 24
Peak memory 228728 kb
Host smart-5b4c21ba-66f9-474c-8409-893d35f97707
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737953712 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.2737953712
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_alert.1510080473
Short name T181
Test name
Test status
Simulation time 23493268 ps
CPU time 1.18 seconds
Started Jul 06 06:28:44 PM PDT 24
Finished Jul 06 06:28:46 PM PDT 24
Peak memory 219268 kb
Host smart-48da3863-f803-402b-8fe5-aba73e199056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510080473 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_alert.1510080473
Directory /workspace/120.edn_alert/latest

Test location /workspace/coverage/default/120.edn_genbits.2203898926
Short name T437
Test name
Test status
Simulation time 38020760 ps
CPU time 1.46 seconds
Started Jul 06 06:28:53 PM PDT 24
Finished Jul 06 06:28:55 PM PDT 24
Peak memory 218812 kb
Host smart-4b843e02-9269-4a60-b1bf-13368d7e8521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203898926 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.2203898926
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_alert.286249252
Short name T995
Test name
Test status
Simulation time 89663201 ps
CPU time 1.18 seconds
Started Jul 06 06:28:44 PM PDT 24
Finished Jul 06 06:28:46 PM PDT 24
Peak memory 219872 kb
Host smart-be06cbe0-9614-49b3-8c8c-648528570a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286249252 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_alert.286249252
Directory /workspace/121.edn_alert/latest

Test location /workspace/coverage/default/121.edn_genbits.3792166789
Short name T687
Test name
Test status
Simulation time 32876766 ps
CPU time 1.36 seconds
Started Jul 06 06:28:42 PM PDT 24
Finished Jul 06 06:28:44 PM PDT 24
Peak memory 219844 kb
Host smart-bd470edb-c0b2-4084-ac07-69da4edd06bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792166789 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.3792166789
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_alert.1448260563
Short name T144
Test name
Test status
Simulation time 40381767 ps
CPU time 1.18 seconds
Started Jul 06 06:28:45 PM PDT 24
Finished Jul 06 06:28:47 PM PDT 24
Peak memory 218944 kb
Host smart-795f1649-1dd8-46b0-a621-17a2ac82f9e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448260563 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_alert.1448260563
Directory /workspace/122.edn_alert/latest

Test location /workspace/coverage/default/122.edn_genbits.4204501933
Short name T444
Test name
Test status
Simulation time 107766625 ps
CPU time 1.56 seconds
Started Jul 06 06:28:46 PM PDT 24
Finished Jul 06 06:28:48 PM PDT 24
Peak memory 219356 kb
Host smart-039abb66-dddb-4d0f-aba4-23ab3ad6a5ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204501933 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.4204501933
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_alert.2648559640
Short name T258
Test name
Test status
Simulation time 46580056 ps
CPU time 1.2 seconds
Started Jul 06 06:28:46 PM PDT 24
Finished Jul 06 06:28:48 PM PDT 24
Peak memory 218984 kb
Host smart-6e56ffb3-1b22-4389-8598-aa6414515060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648559640 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_alert.2648559640
Directory /workspace/123.edn_alert/latest

Test location /workspace/coverage/default/123.edn_genbits.2790373239
Short name T329
Test name
Test status
Simulation time 30931167 ps
CPU time 1.32 seconds
Started Jul 06 06:28:52 PM PDT 24
Finished Jul 06 06:28:54 PM PDT 24
Peak memory 219848 kb
Host smart-15d6d1c1-7ffb-4d8c-99f1-f1bb3bcbd025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790373239 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.2790373239
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_alert.652305450
Short name T743
Test name
Test status
Simulation time 28360698 ps
CPU time 1.25 seconds
Started Jul 06 06:29:05 PM PDT 24
Finished Jul 06 06:29:07 PM PDT 24
Peak memory 221256 kb
Host smart-fe507df1-2966-40d2-b38b-6010f1bb410d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652305450 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_alert.652305450
Directory /workspace/124.edn_alert/latest

Test location /workspace/coverage/default/124.edn_genbits.4177357535
Short name T716
Test name
Test status
Simulation time 91493690 ps
CPU time 1.14 seconds
Started Jul 06 06:29:10 PM PDT 24
Finished Jul 06 06:29:12 PM PDT 24
Peak memory 217632 kb
Host smart-0253f86e-5210-42c9-8805-1179e364e4e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177357535 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.4177357535
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_alert.4083690482
Short name T172
Test name
Test status
Simulation time 151603643 ps
CPU time 1.2 seconds
Started Jul 06 06:28:44 PM PDT 24
Finished Jul 06 06:28:45 PM PDT 24
Peak memory 216036 kb
Host smart-2609a503-8fa4-443a-b27c-061b6f7d0064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083690482 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_alert.4083690482
Directory /workspace/125.edn_alert/latest

Test location /workspace/coverage/default/126.edn_alert.2574805472
Short name T312
Test name
Test status
Simulation time 25862106 ps
CPU time 1.23 seconds
Started Jul 06 06:28:47 PM PDT 24
Finished Jul 06 06:28:48 PM PDT 24
Peak memory 219004 kb
Host smart-cc08c415-0a55-430b-9419-e590d2c6c948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574805472 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_alert.2574805472
Directory /workspace/126.edn_alert/latest

Test location /workspace/coverage/default/126.edn_genbits.3145799839
Short name T910
Test name
Test status
Simulation time 75752269 ps
CPU time 1.25 seconds
Started Jul 06 06:28:47 PM PDT 24
Finished Jul 06 06:28:49 PM PDT 24
Peak memory 217496 kb
Host smart-e7d473be-3540-486c-bc60-662bde59baf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145799839 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.3145799839
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_alert.191089715
Short name T531
Test name
Test status
Simulation time 36374919 ps
CPU time 1.08 seconds
Started Jul 06 06:28:47 PM PDT 24
Finished Jul 06 06:28:48 PM PDT 24
Peak memory 219236 kb
Host smart-51f08f01-95e5-4e06-adb8-5a66f816a34e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191089715 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_alert.191089715
Directory /workspace/127.edn_alert/latest

Test location /workspace/coverage/default/127.edn_genbits.705110541
Short name T921
Test name
Test status
Simulation time 48904605 ps
CPU time 1.5 seconds
Started Jul 06 06:28:52 PM PDT 24
Finished Jul 06 06:28:54 PM PDT 24
Peak memory 219088 kb
Host smart-b7e5a812-3f5c-47c6-9cd0-172dec753e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705110541 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.705110541
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_alert.2101355416
Short name T853
Test name
Test status
Simulation time 140158694 ps
CPU time 1.28 seconds
Started Jul 06 06:28:44 PM PDT 24
Finished Jul 06 06:28:46 PM PDT 24
Peak memory 216012 kb
Host smart-8f67a663-852b-4369-be0c-23fb74448ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101355416 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_alert.2101355416
Directory /workspace/128.edn_alert/latest

Test location /workspace/coverage/default/128.edn_genbits.1623589353
Short name T390
Test name
Test status
Simulation time 55841837 ps
CPU time 1.34 seconds
Started Jul 06 06:28:53 PM PDT 24
Finished Jul 06 06:28:55 PM PDT 24
Peak memory 218876 kb
Host smart-3a76e24b-1762-4379-a074-1685d79ac66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623589353 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.1623589353
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_alert.2559027165
Short name T684
Test name
Test status
Simulation time 98082777 ps
CPU time 1.21 seconds
Started Jul 06 06:28:44 PM PDT 24
Finished Jul 06 06:28:46 PM PDT 24
Peak memory 216140 kb
Host smart-3eb4dbf3-ac31-4194-9b14-976c1e07d888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559027165 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_alert.2559027165
Directory /workspace/129.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert.3340150190
Short name T130
Test name
Test status
Simulation time 39034335 ps
CPU time 1.19 seconds
Started Jul 06 06:27:13 PM PDT 24
Finished Jul 06 06:27:15 PM PDT 24
Peak memory 219616 kb
Host smart-49f5a766-2bf7-4ac8-b1aa-55a4c5d3a538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340150190 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.3340150190
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.2727651081
Short name T986
Test name
Test status
Simulation time 23075834 ps
CPU time 0.87 seconds
Started Jul 06 06:27:14 PM PDT 24
Finished Jul 06 06:27:16 PM PDT 24
Peak memory 207048 kb
Host smart-26db1f38-7550-4178-a640-8069a5bbc605
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727651081 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.2727651081
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.858877965
Short name T216
Test name
Test status
Simulation time 41911171 ps
CPU time 0.86 seconds
Started Jul 06 06:27:21 PM PDT 24
Finished Jul 06 06:27:23 PM PDT 24
Peak memory 216608 kb
Host smart-fcc93432-ff70-42b9-9a01-5be813ef7142
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858877965 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.858877965
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.1272133742
Short name T657
Test name
Test status
Simulation time 59157297 ps
CPU time 1.01 seconds
Started Jul 06 06:27:15 PM PDT 24
Finished Jul 06 06:27:17 PM PDT 24
Peak memory 217288 kb
Host smart-0ec33b17-6db0-4cd9-b15a-8265da6befa0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272133742 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.1272133742
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.1965833811
Short name T166
Test name
Test status
Simulation time 20757299 ps
CPU time 1.02 seconds
Started Jul 06 06:27:13 PM PDT 24
Finished Jul 06 06:27:15 PM PDT 24
Peak memory 224272 kb
Host smart-2dfaed71-d0ad-48d6-9bb3-baa274367664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965833811 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.1965833811
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.2410570773
Short name T398
Test name
Test status
Simulation time 61788174 ps
CPU time 1.45 seconds
Started Jul 06 06:27:13 PM PDT 24
Finished Jul 06 06:27:15 PM PDT 24
Peak memory 219048 kb
Host smart-9a083ac3-129a-402f-9e7f-443919023035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410570773 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.2410570773
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_smoke.2189162319
Short name T954
Test name
Test status
Simulation time 20040905 ps
CPU time 1 seconds
Started Jul 06 06:27:15 PM PDT 24
Finished Jul 06 06:27:16 PM PDT 24
Peak memory 215616 kb
Host smart-ed74c479-1eab-4fc4-9ec1-3e9ee5113d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189162319 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.2189162319
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.3369248510
Short name T499
Test name
Test status
Simulation time 218668973 ps
CPU time 1.78 seconds
Started Jul 06 06:27:21 PM PDT 24
Finished Jul 06 06:27:24 PM PDT 24
Peak memory 215592 kb
Host smart-5cb09dc0-726b-4fa3-9720-3ffa1c4ae8f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369248510 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.3369248510
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.1737286776
Short name T778
Test name
Test status
Simulation time 113725199781 ps
CPU time 864.97 seconds
Started Jul 06 06:27:21 PM PDT 24
Finished Jul 06 06:41:47 PM PDT 24
Peak memory 223992 kb
Host smart-eb8b312e-0df8-422f-8f41-42edccfd7e37
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737286776 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.1737286776
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_alert.105938671
Short name T805
Test name
Test status
Simulation time 32500479 ps
CPU time 1.41 seconds
Started Jul 06 06:28:50 PM PDT 24
Finished Jul 06 06:28:51 PM PDT 24
Peak memory 216048 kb
Host smart-eab28d19-a60e-47a3-b211-f4ef5f9a9ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105938671 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_alert.105938671
Directory /workspace/130.edn_alert/latest

Test location /workspace/coverage/default/131.edn_alert.106753134
Short name T224
Test name
Test status
Simulation time 34351590 ps
CPU time 1.29 seconds
Started Jul 06 06:28:47 PM PDT 24
Finished Jul 06 06:28:48 PM PDT 24
Peak memory 220440 kb
Host smart-7bc2d675-ff4f-4b92-a892-a45e92f149f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106753134 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_alert.106753134
Directory /workspace/131.edn_alert/latest

Test location /workspace/coverage/default/132.edn_alert.2585219506
Short name T158
Test name
Test status
Simulation time 55519708 ps
CPU time 1.29 seconds
Started Jul 06 06:28:46 PM PDT 24
Finished Jul 06 06:28:48 PM PDT 24
Peak memory 216008 kb
Host smart-132abbd3-1a8c-4be4-bbd5-e2a7aa08169f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585219506 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_alert.2585219506
Directory /workspace/132.edn_alert/latest

Test location /workspace/coverage/default/132.edn_genbits.3948804133
Short name T678
Test name
Test status
Simulation time 446435123 ps
CPU time 1.58 seconds
Started Jul 06 06:28:47 PM PDT 24
Finished Jul 06 06:28:49 PM PDT 24
Peak memory 217688 kb
Host smart-f867a54b-3f05-40f8-a0d1-309f743faff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948804133 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.3948804133
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_alert.496912476
Short name T589
Test name
Test status
Simulation time 30313340 ps
CPU time 1.47 seconds
Started Jul 06 06:28:56 PM PDT 24
Finished Jul 06 06:28:58 PM PDT 24
Peak memory 215984 kb
Host smart-7161371c-5c88-44da-a2ad-5b16fa85daf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496912476 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_alert.496912476
Directory /workspace/133.edn_alert/latest

Test location /workspace/coverage/default/133.edn_genbits.463375267
Short name T602
Test name
Test status
Simulation time 66057984 ps
CPU time 2.34 seconds
Started Jul 06 06:28:56 PM PDT 24
Finished Jul 06 06:28:59 PM PDT 24
Peak memory 215692 kb
Host smart-be76b6ed-5ddc-44cd-8ad7-514cc7ded160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463375267 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.463375267
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_alert.2785782302
Short name T99
Test name
Test status
Simulation time 47639753 ps
CPU time 1.19 seconds
Started Jul 06 06:28:47 PM PDT 24
Finished Jul 06 06:28:49 PM PDT 24
Peak memory 219172 kb
Host smart-1732791a-7c49-4640-bcbe-8e6c8f0c9106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785782302 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_alert.2785782302
Directory /workspace/134.edn_alert/latest

Test location /workspace/coverage/default/135.edn_alert.3645584657
Short name T642
Test name
Test status
Simulation time 172047460 ps
CPU time 1.24 seconds
Started Jul 06 06:28:52 PM PDT 24
Finished Jul 06 06:28:54 PM PDT 24
Peak memory 220152 kb
Host smart-1cb8a490-f889-4878-bdb0-0aaf22b0ae43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645584657 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_alert.3645584657
Directory /workspace/135.edn_alert/latest

Test location /workspace/coverage/default/135.edn_genbits.4018672387
Short name T659
Test name
Test status
Simulation time 86479238 ps
CPU time 1.41 seconds
Started Jul 06 06:28:50 PM PDT 24
Finished Jul 06 06:28:51 PM PDT 24
Peak memory 220580 kb
Host smart-09cf309b-820c-4f24-8dc8-47a6447493f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018672387 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.4018672387
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_alert.2927375176
Short name T9
Test name
Test status
Simulation time 52976198 ps
CPU time 1.25 seconds
Started Jul 06 06:28:54 PM PDT 24
Finished Jul 06 06:28:56 PM PDT 24
Peak memory 220124 kb
Host smart-ada4ea72-12bf-44c2-ad05-ac5bca2dcab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927375176 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_alert.2927375176
Directory /workspace/136.edn_alert/latest

Test location /workspace/coverage/default/136.edn_genbits.1827089150
Short name T353
Test name
Test status
Simulation time 51064690 ps
CPU time 1.5 seconds
Started Jul 06 06:28:47 PM PDT 24
Finished Jul 06 06:28:49 PM PDT 24
Peak memory 217852 kb
Host smart-0f23e08e-89c7-45e5-aa83-784ff8970c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827089150 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.1827089150
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_alert.2484750763
Short name T51
Test name
Test status
Simulation time 62034833 ps
CPU time 1.24 seconds
Started Jul 06 06:28:47 PM PDT 24
Finished Jul 06 06:28:49 PM PDT 24
Peak memory 220040 kb
Host smart-dd0be482-ae1f-48ca-b8a0-9eedba150069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484750763 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_alert.2484750763
Directory /workspace/137.edn_alert/latest

Test location /workspace/coverage/default/137.edn_genbits.4160846617
Short name T857
Test name
Test status
Simulation time 272070229 ps
CPU time 1.96 seconds
Started Jul 06 06:28:55 PM PDT 24
Finished Jul 06 06:28:58 PM PDT 24
Peak memory 219280 kb
Host smart-0928aebb-1e80-45d2-bff2-b6300b5789cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160846617 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.4160846617
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_genbits.2233468550
Short name T971
Test name
Test status
Simulation time 36560906 ps
CPU time 1.07 seconds
Started Jul 06 06:28:55 PM PDT 24
Finished Jul 06 06:28:56 PM PDT 24
Peak memory 218828 kb
Host smart-d9cf0898-7e05-4944-8ed0-307f2c438316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233468550 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.2233468550
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_alert.1993340215
Short name T757
Test name
Test status
Simulation time 24776760 ps
CPU time 1.22 seconds
Started Jul 06 06:28:53 PM PDT 24
Finished Jul 06 06:28:54 PM PDT 24
Peak memory 220988 kb
Host smart-694cd6cd-7218-42c3-ad6d-31aa18302968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993340215 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_alert.1993340215
Directory /workspace/139.edn_alert/latest

Test location /workspace/coverage/default/139.edn_genbits.2503514024
Short name T608
Test name
Test status
Simulation time 35149224 ps
CPU time 1.15 seconds
Started Jul 06 06:28:47 PM PDT 24
Finished Jul 06 06:28:49 PM PDT 24
Peak memory 218988 kb
Host smart-6719710d-0abb-4320-8bb6-847f2cd50acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503514024 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.2503514024
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.1375505343
Short name T610
Test name
Test status
Simulation time 44224549 ps
CPU time 1.16 seconds
Started Jul 06 06:27:16 PM PDT 24
Finished Jul 06 06:27:17 PM PDT 24
Peak memory 220564 kb
Host smart-118ccb80-9006-4dfc-9982-a50dff995662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375505343 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.1375505343
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.3224479483
Short name T413
Test name
Test status
Simulation time 45369640 ps
CPU time 0.9 seconds
Started Jul 06 06:27:17 PM PDT 24
Finished Jul 06 06:27:19 PM PDT 24
Peak memory 215528 kb
Host smart-7a4b1c9b-4765-4881-bef4-abad37d81d97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224479483 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.3224479483
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.3712163886
Short name T177
Test name
Test status
Simulation time 37582546 ps
CPU time 0.84 seconds
Started Jul 06 06:27:29 PM PDT 24
Finished Jul 06 06:27:31 PM PDT 24
Peak memory 216548 kb
Host smart-6317d37c-ff61-409e-ab1a-0a91caa384fc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712163886 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.3712163886
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.2115968854
Short name T873
Test name
Test status
Simulation time 47869925 ps
CPU time 1.37 seconds
Started Jul 06 06:27:16 PM PDT 24
Finished Jul 06 06:27:17 PM PDT 24
Peak memory 217144 kb
Host smart-aeb7c4b5-8e44-4017-8188-4396dcead325
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115968854 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.2115968854
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.2610627696
Short name T203
Test name
Test status
Simulation time 32746135 ps
CPU time 1 seconds
Started Jul 06 06:27:15 PM PDT 24
Finished Jul 06 06:27:17 PM PDT 24
Peak memory 220128 kb
Host smart-9c67f957-2d97-45ae-8636-617b960fd871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610627696 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.2610627696
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.2172252332
Short name T913
Test name
Test status
Simulation time 43409761 ps
CPU time 1.57 seconds
Started Jul 06 06:27:15 PM PDT 24
Finished Jul 06 06:27:17 PM PDT 24
Peak memory 218984 kb
Host smart-b1368365-2825-47ae-9f63-e9901f149378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172252332 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.2172252332
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_smoke.4023103858
Short name T840
Test name
Test status
Simulation time 57692001 ps
CPU time 0.9 seconds
Started Jul 06 06:27:13 PM PDT 24
Finished Jul 06 06:27:14 PM PDT 24
Peak memory 215612 kb
Host smart-bc68225e-7700-4375-b02c-f36dd045aee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023103858 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.4023103858
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.1107626155
Short name T761
Test name
Test status
Simulation time 308955104 ps
CPU time 6 seconds
Started Jul 06 06:27:14 PM PDT 24
Finished Jul 06 06:27:20 PM PDT 24
Peak memory 217688 kb
Host smart-404a61b5-0b94-4f9c-970b-9d570ce25ced
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107626155 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.1107626155
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.2276691139
Short name T795
Test name
Test status
Simulation time 14612971918 ps
CPU time 341.28 seconds
Started Jul 06 06:27:20 PM PDT 24
Finished Jul 06 06:33:01 PM PDT 24
Peak memory 222252 kb
Host smart-5347e8f2-231d-4c12-860a-dfb183e52519
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276691139 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.2276691139
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_alert.3646483729
Short name T126
Test name
Test status
Simulation time 133026535 ps
CPU time 1.24 seconds
Started Jul 06 06:28:51 PM PDT 24
Finished Jul 06 06:28:53 PM PDT 24
Peak memory 220348 kb
Host smart-b7dc2479-0519-41ef-a591-e376214525a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646483729 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_alert.3646483729
Directory /workspace/140.edn_alert/latest

Test location /workspace/coverage/default/140.edn_genbits.597759358
Short name T421
Test name
Test status
Simulation time 81736854 ps
CPU time 1.88 seconds
Started Jul 06 06:28:49 PM PDT 24
Finished Jul 06 06:28:51 PM PDT 24
Peak memory 220604 kb
Host smart-d286c66b-f003-4966-9f97-64a8af71b8e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597759358 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.597759358
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_alert.3112921769
Short name T830
Test name
Test status
Simulation time 87901782 ps
CPU time 1.22 seconds
Started Jul 06 06:28:47 PM PDT 24
Finished Jul 06 06:28:49 PM PDT 24
Peak memory 221284 kb
Host smart-25bf57c2-0f56-4c59-ba19-5e3c27d29dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112921769 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_alert.3112921769
Directory /workspace/141.edn_alert/latest

Test location /workspace/coverage/default/141.edn_genbits.3690576894
Short name T103
Test name
Test status
Simulation time 264375665 ps
CPU time 3.59 seconds
Started Jul 06 06:28:54 PM PDT 24
Finished Jul 06 06:28:58 PM PDT 24
Peak memory 218880 kb
Host smart-8915a97a-fe2e-44a6-a291-8200540b08f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690576894 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.3690576894
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_alert.2726404469
Short name T298
Test name
Test status
Simulation time 68725910 ps
CPU time 1.24 seconds
Started Jul 06 06:28:56 PM PDT 24
Finished Jul 06 06:28:58 PM PDT 24
Peak memory 219580 kb
Host smart-0c6b2696-c980-45fb-8a0e-5524ebc879fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726404469 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_alert.2726404469
Directory /workspace/142.edn_alert/latest

Test location /workspace/coverage/default/142.edn_genbits.4051091920
Short name T972
Test name
Test status
Simulation time 48036577 ps
CPU time 1.57 seconds
Started Jul 06 06:28:55 PM PDT 24
Finished Jul 06 06:28:57 PM PDT 24
Peak memory 219504 kb
Host smart-1eb59d83-e406-429d-83e9-b0fd8595f697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051091920 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.4051091920
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_alert.2150855362
Short name T527
Test name
Test status
Simulation time 177605100 ps
CPU time 1.08 seconds
Started Jul 06 06:28:54 PM PDT 24
Finished Jul 06 06:28:55 PM PDT 24
Peak memory 218816 kb
Host smart-b2142add-de8a-4424-b2f0-77870dd27d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150855362 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_alert.2150855362
Directory /workspace/143.edn_alert/latest

Test location /workspace/coverage/default/143.edn_genbits.2727054802
Short name T663
Test name
Test status
Simulation time 42576221 ps
CPU time 1.45 seconds
Started Jul 06 06:28:57 PM PDT 24
Finished Jul 06 06:28:59 PM PDT 24
Peak memory 217676 kb
Host smart-091a872b-fbbd-4f8b-aee3-843520f9caf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727054802 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.2727054802
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_alert.4189899652
Short name T150
Test name
Test status
Simulation time 36779860 ps
CPU time 1.23 seconds
Started Jul 06 06:28:57 PM PDT 24
Finished Jul 06 06:28:59 PM PDT 24
Peak memory 220656 kb
Host smart-2454b368-90ac-415c-9966-c5d35cad397f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189899652 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_alert.4189899652
Directory /workspace/144.edn_alert/latest

Test location /workspace/coverage/default/144.edn_genbits.2556242255
Short name T448
Test name
Test status
Simulation time 45987396 ps
CPU time 1.77 seconds
Started Jul 06 06:28:56 PM PDT 24
Finished Jul 06 06:28:58 PM PDT 24
Peak memory 217780 kb
Host smart-5db332c3-b230-496a-b12d-b79d1b8ef76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556242255 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.2556242255
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_alert.2505787670
Short name T820
Test name
Test status
Simulation time 129491741 ps
CPU time 1.31 seconds
Started Jul 06 06:28:55 PM PDT 24
Finished Jul 06 06:28:58 PM PDT 24
Peak memory 220920 kb
Host smart-8d67e882-1cfd-43e3-8cd7-4fa4ba479b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505787670 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_alert.2505787670
Directory /workspace/145.edn_alert/latest

Test location /workspace/coverage/default/145.edn_genbits.1705275139
Short name T98
Test name
Test status
Simulation time 74346755 ps
CPU time 2.69 seconds
Started Jul 06 06:28:57 PM PDT 24
Finished Jul 06 06:29:01 PM PDT 24
Peak memory 220424 kb
Host smart-67c9065c-b568-452a-b06d-eb781100bffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705275139 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.1705275139
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_alert.81892363
Short name T576
Test name
Test status
Simulation time 32456409 ps
CPU time 1.17 seconds
Started Jul 06 06:28:54 PM PDT 24
Finished Jul 06 06:28:56 PM PDT 24
Peak memory 219056 kb
Host smart-516941f4-22a2-4845-9ab9-44934d154f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81892363 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_alert.81892363
Directory /workspace/146.edn_alert/latest

Test location /workspace/coverage/default/147.edn_alert.1589977896
Short name T911
Test name
Test status
Simulation time 38092462 ps
CPU time 1.17 seconds
Started Jul 06 06:28:53 PM PDT 24
Finished Jul 06 06:28:55 PM PDT 24
Peak memory 219028 kb
Host smart-835f290d-5c10-4a6c-b6f8-a8693ebea0ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589977896 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_alert.1589977896
Directory /workspace/147.edn_alert/latest

Test location /workspace/coverage/default/147.edn_genbits.330507852
Short name T297
Test name
Test status
Simulation time 77698163 ps
CPU time 1.07 seconds
Started Jul 06 06:28:57 PM PDT 24
Finished Jul 06 06:28:58 PM PDT 24
Peak memory 217796 kb
Host smart-67f4dc88-4185-4039-926a-3a8b3d5f17fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330507852 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.330507852
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_alert.2034153102
Short name T669
Test name
Test status
Simulation time 75779909 ps
CPU time 1.14 seconds
Started Jul 06 06:28:54 PM PDT 24
Finished Jul 06 06:28:55 PM PDT 24
Peak memory 221052 kb
Host smart-1885b8d3-f772-4527-a374-8b3709c23fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034153102 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_alert.2034153102
Directory /workspace/148.edn_alert/latest

Test location /workspace/coverage/default/148.edn_genbits.2511195647
Short name T385
Test name
Test status
Simulation time 76139646 ps
CPU time 1.26 seconds
Started Jul 06 06:28:54 PM PDT 24
Finished Jul 06 06:28:56 PM PDT 24
Peak memory 219200 kb
Host smart-ff4483c1-38cc-4b99-9197-a8103a255e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511195647 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.2511195647
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_alert.892071892
Short name T842
Test name
Test status
Simulation time 23730216 ps
CPU time 1.23 seconds
Started Jul 06 06:28:58 PM PDT 24
Finished Jul 06 06:29:01 PM PDT 24
Peak memory 220524 kb
Host smart-486948bd-4640-403c-9375-880f013b2ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892071892 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_alert.892071892
Directory /workspace/149.edn_alert/latest

Test location /workspace/coverage/default/149.edn_genbits.2674547717
Short name T350
Test name
Test status
Simulation time 42422470 ps
CPU time 1.45 seconds
Started Jul 06 06:28:53 PM PDT 24
Finished Jul 06 06:28:55 PM PDT 24
Peak memory 218920 kb
Host smart-99715b50-3307-4376-8579-1080e8853b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674547717 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.2674547717
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.379400619
Short name T256
Test name
Test status
Simulation time 26848717 ps
CPU time 1.2 seconds
Started Jul 06 06:27:25 PM PDT 24
Finished Jul 06 06:27:26 PM PDT 24
Peak memory 221232 kb
Host smart-d1a2e6b8-971f-4d0b-a9b4-3e49c169ad5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379400619 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.379400619
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.824041861
Short name T386
Test name
Test status
Simulation time 40893203 ps
CPU time 0.84 seconds
Started Jul 06 06:27:20 PM PDT 24
Finished Jul 06 06:27:21 PM PDT 24
Peak memory 215524 kb
Host smart-df8bc79c-c19a-4b5f-a44f-71787494f041
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824041861 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.824041861
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.1221796276
Short name T185
Test name
Test status
Simulation time 14036248 ps
CPU time 0.89 seconds
Started Jul 06 06:27:18 PM PDT 24
Finished Jul 06 06:27:20 PM PDT 24
Peak memory 215952 kb
Host smart-df3323ef-b2f7-4bb4-889c-7f758ddc82ea
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221796276 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.1221796276
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_err.1587105914
Short name T885
Test name
Test status
Simulation time 30825040 ps
CPU time 0.91 seconds
Started Jul 06 06:27:19 PM PDT 24
Finished Jul 06 06:27:20 PM PDT 24
Peak memory 218888 kb
Host smart-dd65ded6-ba76-4114-83ac-9a9d23fdfaf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587105914 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.1587105914
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_intr.604696198
Short name T16
Test name
Test status
Simulation time 23137185 ps
CPU time 1.25 seconds
Started Jul 06 06:27:23 PM PDT 24
Finished Jul 06 06:27:25 PM PDT 24
Peak memory 224196 kb
Host smart-76b02923-790c-4519-a607-0568c01fccd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604696198 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.604696198
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.433737921
Short name T930
Test name
Test status
Simulation time 29178701 ps
CPU time 0.94 seconds
Started Jul 06 06:27:16 PM PDT 24
Finished Jul 06 06:27:18 PM PDT 24
Peak memory 215648 kb
Host smart-b9abfc1a-0a85-498e-84f3-f00d426c7703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433737921 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.433737921
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.664110672
Short name T552
Test name
Test status
Simulation time 166456271 ps
CPU time 3.74 seconds
Started Jul 06 06:27:23 PM PDT 24
Finished Jul 06 06:27:27 PM PDT 24
Peak memory 215632 kb
Host smart-d61e42bc-0aa7-4916-9468-08e2e081ba8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664110672 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.664110672
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.2450700354
Short name T564
Test name
Test status
Simulation time 309755829148 ps
CPU time 1984.16 seconds
Started Jul 06 06:27:23 PM PDT 24
Finished Jul 06 07:00:28 PM PDT 24
Peak memory 230368 kb
Host smart-8081da90-4d5d-4b75-87f6-1358f93ef2d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450700354 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.2450700354
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_alert.1423791439
Short name T117
Test name
Test status
Simulation time 29101377 ps
CPU time 1.27 seconds
Started Jul 06 06:28:59 PM PDT 24
Finished Jul 06 06:29:01 PM PDT 24
Peak memory 218976 kb
Host smart-1609e34d-261d-4789-91a0-052b088e286e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423791439 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_alert.1423791439
Directory /workspace/150.edn_alert/latest

Test location /workspace/coverage/default/150.edn_genbits.1583299453
Short name T458
Test name
Test status
Simulation time 53260410 ps
CPU time 1.29 seconds
Started Jul 06 06:28:52 PM PDT 24
Finished Jul 06 06:28:53 PM PDT 24
Peak memory 219008 kb
Host smart-7b675972-6fe9-4720-be71-e939719f7183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583299453 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.1583299453
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_alert.1908976571
Short name T440
Test name
Test status
Simulation time 24373466 ps
CPU time 1.18 seconds
Started Jul 06 06:28:53 PM PDT 24
Finished Jul 06 06:28:54 PM PDT 24
Peak memory 218968 kb
Host smart-3c6ec8c4-0d0a-4699-bdfb-4d34c136dce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908976571 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_alert.1908976571
Directory /workspace/151.edn_alert/latest

Test location /workspace/coverage/default/151.edn_genbits.2755008239
Short name T934
Test name
Test status
Simulation time 88601587 ps
CPU time 1.2 seconds
Started Jul 06 06:28:53 PM PDT 24
Finished Jul 06 06:28:55 PM PDT 24
Peak memory 219028 kb
Host smart-826485ad-7970-4a24-94a1-5ff1a9f17546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755008239 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.2755008239
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_alert.325569741
Short name T26
Test name
Test status
Simulation time 24025199 ps
CPU time 1.18 seconds
Started Jul 06 06:28:58 PM PDT 24
Finished Jul 06 06:29:00 PM PDT 24
Peak memory 218908 kb
Host smart-c06ab924-f1a9-4b16-8963-f6d6a10b9775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325569741 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_alert.325569741
Directory /workspace/152.edn_alert/latest

Test location /workspace/coverage/default/152.edn_genbits.298892194
Short name T637
Test name
Test status
Simulation time 30146532 ps
CPU time 1.08 seconds
Started Jul 06 06:28:55 PM PDT 24
Finished Jul 06 06:28:56 PM PDT 24
Peak memory 219732 kb
Host smart-200c4f97-3629-410d-8188-7da3c2661f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298892194 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.298892194
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_alert.3260476459
Short name T518
Test name
Test status
Simulation time 35255854 ps
CPU time 1.19 seconds
Started Jul 06 06:28:56 PM PDT 24
Finished Jul 06 06:28:58 PM PDT 24
Peak memory 221148 kb
Host smart-a232ad9f-a725-42b2-ba10-ed3e45d5c637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260476459 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_alert.3260476459
Directory /workspace/153.edn_alert/latest

Test location /workspace/coverage/default/153.edn_genbits.2174245688
Short name T943
Test name
Test status
Simulation time 133816101 ps
CPU time 2.95 seconds
Started Jul 06 06:28:54 PM PDT 24
Finished Jul 06 06:28:58 PM PDT 24
Peak memory 219396 kb
Host smart-a12bb611-7f96-4878-84f6-95427a7c9b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174245688 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.2174245688
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_alert.3904527532
Short name T590
Test name
Test status
Simulation time 43071635 ps
CPU time 1.19 seconds
Started Jul 06 06:28:55 PM PDT 24
Finished Jul 06 06:28:57 PM PDT 24
Peak memory 218988 kb
Host smart-0dbcc905-e3f3-4b77-a80a-44e27d19c604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904527532 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_alert.3904527532
Directory /workspace/154.edn_alert/latest

Test location /workspace/coverage/default/154.edn_genbits.3401309869
Short name T459
Test name
Test status
Simulation time 30347810 ps
CPU time 1.4 seconds
Started Jul 06 06:28:56 PM PDT 24
Finished Jul 06 06:28:58 PM PDT 24
Peak memory 218852 kb
Host smart-3978087c-d68b-4501-adea-002c9f0e9b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401309869 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.3401309869
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_alert.2815223120
Short name T754
Test name
Test status
Simulation time 96198521 ps
CPU time 1.37 seconds
Started Jul 06 06:28:56 PM PDT 24
Finished Jul 06 06:28:58 PM PDT 24
Peak memory 216060 kb
Host smart-ec2b16a9-60a5-4ece-81d7-c7bb00d7fece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815223120 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_alert.2815223120
Directory /workspace/155.edn_alert/latest

Test location /workspace/coverage/default/155.edn_genbits.1306018470
Short name T106
Test name
Test status
Simulation time 35952809 ps
CPU time 1.36 seconds
Started Jul 06 06:28:54 PM PDT 24
Finished Jul 06 06:28:56 PM PDT 24
Peak memory 217716 kb
Host smart-eeffb72d-c2d7-4a9c-bbcd-7e51394facbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306018470 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.1306018470
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_alert.2028094164
Short name T915
Test name
Test status
Simulation time 138931010 ps
CPU time 1.34 seconds
Started Jul 06 06:28:57 PM PDT 24
Finished Jul 06 06:28:59 PM PDT 24
Peak memory 219912 kb
Host smart-a8044d80-10b9-4506-9c08-5c267b26ccf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028094164 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_alert.2028094164
Directory /workspace/156.edn_alert/latest

Test location /workspace/coverage/default/156.edn_genbits.2189454867
Short name T727
Test name
Test status
Simulation time 43802670 ps
CPU time 1.38 seconds
Started Jul 06 06:28:52 PM PDT 24
Finished Jul 06 06:28:54 PM PDT 24
Peak memory 219776 kb
Host smart-5400c48f-9cb5-47d5-a356-57b0d51664ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189454867 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.2189454867
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_alert.3232742278
Short name T991
Test name
Test status
Simulation time 24521847 ps
CPU time 1.23 seconds
Started Jul 06 06:28:57 PM PDT 24
Finished Jul 06 06:28:59 PM PDT 24
Peak memory 218988 kb
Host smart-91ac2af8-6a3d-44e1-b551-34db495eeffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232742278 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_alert.3232742278
Directory /workspace/157.edn_alert/latest

Test location /workspace/coverage/default/157.edn_genbits.3247414326
Short name T766
Test name
Test status
Simulation time 73019792 ps
CPU time 1.28 seconds
Started Jul 06 06:28:59 PM PDT 24
Finished Jul 06 06:29:01 PM PDT 24
Peak memory 219392 kb
Host smart-96194eef-9200-452f-a127-4b62f434840e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247414326 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.3247414326
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_alert.3825878519
Short name T756
Test name
Test status
Simulation time 122929779 ps
CPU time 1.1 seconds
Started Jul 06 06:28:55 PM PDT 24
Finished Jul 06 06:28:56 PM PDT 24
Peak memory 220620 kb
Host smart-57fa279a-934e-443d-9388-d47c0f8a36aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825878519 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_alert.3825878519
Directory /workspace/158.edn_alert/latest

Test location /workspace/coverage/default/159.edn_alert.346980719
Short name T190
Test name
Test status
Simulation time 25669955 ps
CPU time 1.17 seconds
Started Jul 06 06:28:59 PM PDT 24
Finished Jul 06 06:29:01 PM PDT 24
Peak memory 220236 kb
Host smart-62240595-e6e4-4723-a10b-38759cbe12f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346980719 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_alert.346980719
Directory /workspace/159.edn_alert/latest

Test location /workspace/coverage/default/159.edn_genbits.4028725028
Short name T346
Test name
Test status
Simulation time 360392137 ps
CPU time 1.47 seconds
Started Jul 06 06:28:57 PM PDT 24
Finished Jul 06 06:28:59 PM PDT 24
Peak memory 220388 kb
Host smart-9258da26-ec4b-4a8e-8fc8-38bf2ac5b6d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028725028 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.4028725028
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.4223383430
Short name T792
Test name
Test status
Simulation time 58028610 ps
CPU time 1.26 seconds
Started Jul 06 06:27:24 PM PDT 24
Finished Jul 06 06:27:26 PM PDT 24
Peak memory 216012 kb
Host smart-5422621b-d342-4150-a3f2-5c658c8037b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223383430 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.4223383430
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.520346315
Short name T821
Test name
Test status
Simulation time 14841239 ps
CPU time 0.93 seconds
Started Jul 06 06:27:22 PM PDT 24
Finished Jul 06 06:27:23 PM PDT 24
Peak memory 207060 kb
Host smart-494975ce-b88d-4101-b73c-5d5eb8c0c222
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520346315 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.520346315
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.81731736
Short name T502
Test name
Test status
Simulation time 71871573 ps
CPU time 0.89 seconds
Started Jul 06 06:27:23 PM PDT 24
Finished Jul 06 06:27:25 PM PDT 24
Peak memory 216460 kb
Host smart-08f07c5b-f174-4833-aff3-8153f0000a20
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81731736 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.81731736
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.828285283
Short name T557
Test name
Test status
Simulation time 26613127 ps
CPU time 1 seconds
Started Jul 06 06:27:18 PM PDT 24
Finished Jul 06 06:27:19 PM PDT 24
Peak memory 218572 kb
Host smart-7ce0a569-9794-43ea-bf44-e5597037f16a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828285283 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_di
sable_auto_req_mode.828285283
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.3819064293
Short name T661
Test name
Test status
Simulation time 33716811 ps
CPU time 0.85 seconds
Started Jul 06 06:27:25 PM PDT 24
Finished Jul 06 06:27:27 PM PDT 24
Peak memory 218628 kb
Host smart-67126bce-93d0-4204-ad67-71cc94e42618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819064293 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.3819064293
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.2018198080
Short name T303
Test name
Test status
Simulation time 131455822 ps
CPU time 1.26 seconds
Started Jul 06 06:27:18 PM PDT 24
Finished Jul 06 06:27:19 PM PDT 24
Peak memory 219176 kb
Host smart-aaa52877-dfde-4451-bf3e-8621c3f9ca15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018198080 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.2018198080
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.143661346
Short name T438
Test name
Test status
Simulation time 21065589 ps
CPU time 1.05 seconds
Started Jul 06 06:27:18 PM PDT 24
Finished Jul 06 06:27:19 PM PDT 24
Peak memory 216212 kb
Host smart-5d83f370-8111-4baa-a957-32a149521518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143661346 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.143661346
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.2279615152
Short name T403
Test name
Test status
Simulation time 48043646 ps
CPU time 0.94 seconds
Started Jul 06 06:27:25 PM PDT 24
Finished Jul 06 06:27:27 PM PDT 24
Peak memory 215612 kb
Host smart-ea3d1884-5ed0-4723-9cdc-2985c46296ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279615152 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.2279615152
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.3444081208
Short name T509
Test name
Test status
Simulation time 113101619 ps
CPU time 2.65 seconds
Started Jul 06 06:27:24 PM PDT 24
Finished Jul 06 06:27:27 PM PDT 24
Peak memory 217560 kb
Host smart-1308fc56-1213-46f4-9dda-4e88180daae0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444081208 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.3444081208
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/160.edn_genbits.2920804394
Short name T732
Test name
Test status
Simulation time 66279265 ps
CPU time 1.18 seconds
Started Jul 06 06:28:57 PM PDT 24
Finished Jul 06 06:28:58 PM PDT 24
Peak memory 217920 kb
Host smart-f44a0aae-fcad-403f-b2e8-2db47c34bd1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920804394 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.2920804394
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_alert.1153136816
Short name T318
Test name
Test status
Simulation time 25236870 ps
CPU time 1.14 seconds
Started Jul 06 06:29:03 PM PDT 24
Finished Jul 06 06:29:04 PM PDT 24
Peak memory 219992 kb
Host smart-979b8cb2-b316-419a-a2ee-b619738c026b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153136816 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_alert.1153136816
Directory /workspace/161.edn_alert/latest

Test location /workspace/coverage/default/161.edn_genbits.405226441
Short name T466
Test name
Test status
Simulation time 47380634 ps
CPU time 1.33 seconds
Started Jul 06 06:28:59 PM PDT 24
Finished Jul 06 06:29:01 PM PDT 24
Peak memory 219016 kb
Host smart-4a09a05d-3157-48d4-a15b-e575e86390f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405226441 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.405226441
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_alert.2669065013
Short name T940
Test name
Test status
Simulation time 79517461 ps
CPU time 1.13 seconds
Started Jul 06 06:28:58 PM PDT 24
Finished Jul 06 06:29:00 PM PDT 24
Peak memory 221012 kb
Host smart-110c849d-54ee-4b84-a896-2e2e733a38cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669065013 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_alert.2669065013
Directory /workspace/162.edn_alert/latest

Test location /workspace/coverage/default/163.edn_alert.167571056
Short name T222
Test name
Test status
Simulation time 24817186 ps
CPU time 1.2 seconds
Started Jul 06 06:28:58 PM PDT 24
Finished Jul 06 06:29:01 PM PDT 24
Peak memory 220244 kb
Host smart-aa9acbd4-1336-4b62-98bf-64684862bbd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167571056 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_alert.167571056
Directory /workspace/163.edn_alert/latest

Test location /workspace/coverage/default/163.edn_genbits.3767161626
Short name T57
Test name
Test status
Simulation time 73613031 ps
CPU time 1.62 seconds
Started Jul 06 06:29:02 PM PDT 24
Finished Jul 06 06:29:03 PM PDT 24
Peak memory 218928 kb
Host smart-058ea4a2-d8b9-49da-98f7-5efdaa904f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767161626 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.3767161626
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_alert.301051803
Short name T794
Test name
Test status
Simulation time 42188247 ps
CPU time 1.22 seconds
Started Jul 06 06:28:58 PM PDT 24
Finished Jul 06 06:29:00 PM PDT 24
Peak memory 220244 kb
Host smart-37e6d463-cbe1-473e-8c5b-5b42e2d220f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301051803 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_alert.301051803
Directory /workspace/164.edn_alert/latest

Test location /workspace/coverage/default/164.edn_genbits.2919943477
Short name T522
Test name
Test status
Simulation time 85384376 ps
CPU time 1.62 seconds
Started Jul 06 06:28:57 PM PDT 24
Finished Jul 06 06:28:59 PM PDT 24
Peak memory 219304 kb
Host smart-3352b485-4c0b-4d72-badb-62fe008959b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919943477 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.2919943477
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_alert.2972812144
Short name T951
Test name
Test status
Simulation time 46065045 ps
CPU time 1.27 seconds
Started Jul 06 06:28:58 PM PDT 24
Finished Jul 06 06:29:00 PM PDT 24
Peak memory 218992 kb
Host smart-aebd722b-eda2-4171-bd24-309a8da46123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972812144 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_alert.2972812144
Directory /workspace/165.edn_alert/latest

Test location /workspace/coverage/default/165.edn_genbits.2643875541
Short name T759
Test name
Test status
Simulation time 35060918 ps
CPU time 1.37 seconds
Started Jul 06 06:29:01 PM PDT 24
Finished Jul 06 06:29:02 PM PDT 24
Peak memory 217868 kb
Host smart-48ed0509-29de-4a0e-b52e-a8feb3f26238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643875541 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.2643875541
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_alert.1997680413
Short name T388
Test name
Test status
Simulation time 38511206 ps
CPU time 1.11 seconds
Started Jul 06 06:29:07 PM PDT 24
Finished Jul 06 06:29:09 PM PDT 24
Peak memory 219728 kb
Host smart-c86fb91c-53d2-4fd4-bed3-5672bbb1af1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997680413 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_alert.1997680413
Directory /workspace/166.edn_alert/latest

Test location /workspace/coverage/default/166.edn_genbits.1200460276
Short name T726
Test name
Test status
Simulation time 88350574 ps
CPU time 1.37 seconds
Started Jul 06 06:28:58 PM PDT 24
Finished Jul 06 06:29:00 PM PDT 24
Peak memory 219012 kb
Host smart-44d548cd-ef20-4e8d-8f5d-9efa9b2682f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200460276 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.1200460276
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_alert.2357096925
Short name T55
Test name
Test status
Simulation time 31892354 ps
CPU time 1.07 seconds
Started Jul 06 06:28:58 PM PDT 24
Finished Jul 06 06:29:00 PM PDT 24
Peak memory 220156 kb
Host smart-308ca2a5-5316-4577-aaa6-78d9ec3d69d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357096925 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_alert.2357096925
Directory /workspace/167.edn_alert/latest

Test location /workspace/coverage/default/167.edn_genbits.1541846173
Short name T487
Test name
Test status
Simulation time 67011665 ps
CPU time 1.07 seconds
Started Jul 06 06:29:07 PM PDT 24
Finished Jul 06 06:29:08 PM PDT 24
Peak memory 217620 kb
Host smart-f8479681-ccc7-43c7-96d2-5af96204b8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541846173 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.1541846173
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_alert.1926876588
Short name T226
Test name
Test status
Simulation time 22730594 ps
CPU time 1.18 seconds
Started Jul 06 06:28:57 PM PDT 24
Finished Jul 06 06:28:59 PM PDT 24
Peak memory 219092 kb
Host smart-c4b1b39f-8281-4ed6-85e4-3aeed6757034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926876588 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_alert.1926876588
Directory /workspace/168.edn_alert/latest

Test location /workspace/coverage/default/168.edn_genbits.1331793576
Short name T680
Test name
Test status
Simulation time 40813692 ps
CPU time 1.44 seconds
Started Jul 06 06:29:01 PM PDT 24
Finished Jul 06 06:29:03 PM PDT 24
Peak memory 220388 kb
Host smart-c9df44ed-4889-4678-b952-a37dd0a468a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331793576 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.1331793576
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_alert.1668136105
Short name T914
Test name
Test status
Simulation time 36145482 ps
CPU time 1.08 seconds
Started Jul 06 06:28:57 PM PDT 24
Finished Jul 06 06:28:59 PM PDT 24
Peak memory 221180 kb
Host smart-091c5401-bdf5-4726-86fb-973e09ad41d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668136105 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_alert.1668136105
Directory /workspace/169.edn_alert/latest

Test location /workspace/coverage/default/169.edn_genbits.1387093262
Short name T246
Test name
Test status
Simulation time 27881751 ps
CPU time 1.29 seconds
Started Jul 06 06:29:01 PM PDT 24
Finished Jul 06 06:29:02 PM PDT 24
Peak memory 215624 kb
Host smart-4724c774-7ed8-48d6-add0-5d84f4452aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387093262 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.1387093262
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert_test.3062895171
Short name T559
Test name
Test status
Simulation time 88855070 ps
CPU time 0.92 seconds
Started Jul 06 06:27:23 PM PDT 24
Finished Jul 06 06:27:25 PM PDT 24
Peak memory 207112 kb
Host smart-7c0a29ff-c19b-4b79-8d35-b5ebc98e8b1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062895171 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.3062895171
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.167858228
Short name T714
Test name
Test status
Simulation time 42764299 ps
CPU time 0.87 seconds
Started Jul 06 06:27:24 PM PDT 24
Finished Jul 06 06:27:26 PM PDT 24
Peak memory 216320 kb
Host smart-7dca12a5-185f-4bc8-b6df-935bbcb48ba7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167858228 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.167858228
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_err.4144244138
Short name T617
Test name
Test status
Simulation time 20599879 ps
CPU time 1.02 seconds
Started Jul 06 06:27:24 PM PDT 24
Finished Jul 06 06:27:25 PM PDT 24
Peak memory 218984 kb
Host smart-b56c21f7-c90b-4f62-a086-530d7a71f73e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144244138 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.4144244138
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.3805098059
Short name T749
Test name
Test status
Simulation time 37328621 ps
CPU time 1.4 seconds
Started Jul 06 06:27:21 PM PDT 24
Finished Jul 06 06:27:23 PM PDT 24
Peak memory 218912 kb
Host smart-699b6418-8246-4ece-b540-b956df20f1a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805098059 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.3805098059
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.544924365
Short name T775
Test name
Test status
Simulation time 26496614 ps
CPU time 0.96 seconds
Started Jul 06 06:27:21 PM PDT 24
Finished Jul 06 06:27:22 PM PDT 24
Peak memory 215884 kb
Host smart-c7920c14-8d4d-45d5-ae4f-4626c8768eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544924365 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.544924365
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.628755875
Short name T717
Test name
Test status
Simulation time 22018807 ps
CPU time 0.9 seconds
Started Jul 06 06:27:30 PM PDT 24
Finished Jul 06 06:27:31 PM PDT 24
Peak memory 215608 kb
Host smart-e0e7ab90-e58a-48a3-9634-3d5cd067588b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628755875 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.628755875
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.1114586185
Short name T363
Test name
Test status
Simulation time 62343226 ps
CPU time 1.75 seconds
Started Jul 06 06:27:24 PM PDT 24
Finished Jul 06 06:27:26 PM PDT 24
Peak memory 218680 kb
Host smart-2c427680-cf41-415f-8ba8-4f2de67fd24c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114586185 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.1114586185
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.1458569827
Short name T490
Test name
Test status
Simulation time 114268725974 ps
CPU time 542.56 seconds
Started Jul 06 06:27:30 PM PDT 24
Finished Jul 06 06:36:33 PM PDT 24
Peak memory 220484 kb
Host smart-25c547ae-edea-4ba5-b7e4-c5373c308c07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458569827 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.1458569827
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_alert.2449583503
Short name T530
Test name
Test status
Simulation time 94291141 ps
CPU time 1.21 seconds
Started Jul 06 06:29:07 PM PDT 24
Finished Jul 06 06:29:08 PM PDT 24
Peak memory 218832 kb
Host smart-61af79fc-0ad4-46cf-a5f1-7ba5f3a6902d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449583503 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_alert.2449583503
Directory /workspace/170.edn_alert/latest

Test location /workspace/coverage/default/171.edn_alert.2278562989
Short name T650
Test name
Test status
Simulation time 34845414 ps
CPU time 1.2 seconds
Started Jul 06 06:29:02 PM PDT 24
Finished Jul 06 06:29:03 PM PDT 24
Peak memory 218904 kb
Host smart-822a01b5-367b-4313-9f4b-93ff8a597bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278562989 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_alert.2278562989
Directory /workspace/171.edn_alert/latest

Test location /workspace/coverage/default/172.edn_alert.3662466309
Short name T493
Test name
Test status
Simulation time 28781430 ps
CPU time 1.28 seconds
Started Jul 06 06:29:03 PM PDT 24
Finished Jul 06 06:29:05 PM PDT 24
Peak memory 219896 kb
Host smart-2ee0451e-e235-489e-891c-1f69dfa667cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662466309 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_alert.3662466309
Directory /workspace/172.edn_alert/latest

Test location /workspace/coverage/default/172.edn_genbits.2203481349
Short name T519
Test name
Test status
Simulation time 209816824 ps
CPU time 1.05 seconds
Started Jul 06 06:29:08 PM PDT 24
Finished Jul 06 06:29:09 PM PDT 24
Peak memory 217640 kb
Host smart-bb561368-4cb0-4036-9967-a7c69b417fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203481349 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.2203481349
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_alert.3457061848
Short name T582
Test name
Test status
Simulation time 153869257 ps
CPU time 1.2 seconds
Started Jul 06 06:28:56 PM PDT 24
Finished Jul 06 06:28:58 PM PDT 24
Peak memory 220936 kb
Host smart-9b57f859-a542-4f55-bb04-42164e6eb963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457061848 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_alert.3457061848
Directory /workspace/173.edn_alert/latest

Test location /workspace/coverage/default/173.edn_genbits.1807416181
Short name T368
Test name
Test status
Simulation time 49579613 ps
CPU time 1.13 seconds
Started Jul 06 06:29:07 PM PDT 24
Finished Jul 06 06:29:09 PM PDT 24
Peak memory 217532 kb
Host smart-ecfc6f2a-660f-45bd-ae1e-5a77cd039778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807416181 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.1807416181
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_alert.736021248
Short name T762
Test name
Test status
Simulation time 111086739 ps
CPU time 1.13 seconds
Started Jul 06 06:28:57 PM PDT 24
Finished Jul 06 06:28:59 PM PDT 24
Peak memory 219972 kb
Host smart-93fa92e3-e577-4191-b21a-d0421e288118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736021248 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_alert.736021248
Directory /workspace/174.edn_alert/latest

Test location /workspace/coverage/default/175.edn_alert.2214102196
Short name T973
Test name
Test status
Simulation time 28628533 ps
CPU time 1.14 seconds
Started Jul 06 06:28:57 PM PDT 24
Finished Jul 06 06:28:59 PM PDT 24
Peak memory 218904 kb
Host smart-a4b615a0-4cdb-42f6-a2fb-96af1047e77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214102196 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_alert.2214102196
Directory /workspace/175.edn_alert/latest

Test location /workspace/coverage/default/175.edn_genbits.2219990697
Short name T355
Test name
Test status
Simulation time 31822428 ps
CPU time 1.15 seconds
Started Jul 06 06:28:57 PM PDT 24
Finished Jul 06 06:28:59 PM PDT 24
Peak memory 220312 kb
Host smart-a4465987-c978-43b2-8a7f-92de50c406c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219990697 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.2219990697
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_alert.3319454642
Short name T676
Test name
Test status
Simulation time 23201024 ps
CPU time 1.22 seconds
Started Jul 06 06:28:59 PM PDT 24
Finished Jul 06 06:29:01 PM PDT 24
Peak memory 220236 kb
Host smart-85c91c7d-b110-4eb9-82c3-c3b9727eaf09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319454642 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_alert.3319454642
Directory /workspace/176.edn_alert/latest

Test location /workspace/coverage/default/176.edn_genbits.968203763
Short name T708
Test name
Test status
Simulation time 56359944 ps
CPU time 1.58 seconds
Started Jul 06 06:29:01 PM PDT 24
Finished Jul 06 06:29:03 PM PDT 24
Peak memory 218748 kb
Host smart-4267a620-0e94-4c35-bccf-538f99c31a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968203763 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.968203763
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_alert.2606880066
Short name T713
Test name
Test status
Simulation time 83939077 ps
CPU time 1.17 seconds
Started Jul 06 06:28:59 PM PDT 24
Finished Jul 06 06:29:01 PM PDT 24
Peak memory 218956 kb
Host smart-1fc5adda-6e07-4a0f-acb3-f2c4ca6575e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606880066 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_alert.2606880066
Directory /workspace/177.edn_alert/latest

Test location /workspace/coverage/default/177.edn_genbits.490639756
Short name T344
Test name
Test status
Simulation time 49577442 ps
CPU time 1.76 seconds
Started Jul 06 06:28:59 PM PDT 24
Finished Jul 06 06:29:02 PM PDT 24
Peak memory 218740 kb
Host smart-bcf9a925-e2f9-4fb5-8e38-ff714bcae104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490639756 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.490639756
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_alert.3169112832
Short name T597
Test name
Test status
Simulation time 52994546 ps
CPU time 1.06 seconds
Started Jul 06 06:29:07 PM PDT 24
Finished Jul 06 06:29:08 PM PDT 24
Peak memory 220084 kb
Host smart-06146738-47ff-4b80-bf1f-89a286b2170e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169112832 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_alert.3169112832
Directory /workspace/178.edn_alert/latest

Test location /workspace/coverage/default/178.edn_genbits.2530989489
Short name T889
Test name
Test status
Simulation time 213613912 ps
CPU time 3.21 seconds
Started Jul 06 06:29:03 PM PDT 24
Finished Jul 06 06:29:06 PM PDT 24
Peak memory 220556 kb
Host smart-0b75bed9-4cd7-4edc-9d7f-f466d7c24e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530989489 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.2530989489
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_alert.407438809
Short name T168
Test name
Test status
Simulation time 41650769 ps
CPU time 1.08 seconds
Started Jul 06 06:29:05 PM PDT 24
Finished Jul 06 06:29:06 PM PDT 24
Peak memory 218932 kb
Host smart-c85b1ac2-f70d-47b4-9e45-309d0c7a78b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407438809 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_alert.407438809
Directory /workspace/179.edn_alert/latest

Test location /workspace/coverage/default/179.edn_genbits.296206576
Short name T870
Test name
Test status
Simulation time 50690312 ps
CPU time 1.05 seconds
Started Jul 06 06:29:01 PM PDT 24
Finished Jul 06 06:29:03 PM PDT 24
Peak memory 219332 kb
Host smart-5aa37b4f-a1ba-4af6-9850-f626c58b2e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296206576 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.296206576
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.1400570996
Short name T952
Test name
Test status
Simulation time 72315887 ps
CPU time 1.26 seconds
Started Jul 06 06:27:23 PM PDT 24
Finished Jul 06 06:27:25 PM PDT 24
Peak memory 219096 kb
Host smart-f3b031e6-af58-4ae2-80c8-aabf6ed3cd88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400570996 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.1400570996
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.3396490268
Short name T990
Test name
Test status
Simulation time 39990238 ps
CPU time 0.81 seconds
Started Jul 06 06:27:29 PM PDT 24
Finished Jul 06 06:27:30 PM PDT 24
Peak memory 206808 kb
Host smart-2eef4808-f74d-436a-8006-8a6c3ba2a568
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396490268 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.3396490268
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.1121602843
Short name T178
Test name
Test status
Simulation time 12411229 ps
CPU time 0.88 seconds
Started Jul 06 06:27:30 PM PDT 24
Finished Jul 06 06:27:31 PM PDT 24
Peak memory 216736 kb
Host smart-efd11db4-344f-437a-9ce7-c2d262f514ba
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121602843 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.1121602843
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.281857240
Short name T774
Test name
Test status
Simulation time 72937857 ps
CPU time 1.17 seconds
Started Jul 06 06:27:24 PM PDT 24
Finished Jul 06 06:27:26 PM PDT 24
Peak memory 217052 kb
Host smart-ea536555-e338-404c-9bdc-aabc9e60eb38
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281857240 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_di
sable_auto_req_mode.281857240
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.3998967105
Short name T586
Test name
Test status
Simulation time 28807928 ps
CPU time 0.87 seconds
Started Jul 06 06:27:23 PM PDT 24
Finished Jul 06 06:27:25 PM PDT 24
Peak memory 218656 kb
Host smart-609d0fa4-8c65-4ada-8dc9-c35f92338066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998967105 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.3998967105
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.2130946862
Short name T491
Test name
Test status
Simulation time 117217704 ps
CPU time 1.64 seconds
Started Jul 06 06:27:21 PM PDT 24
Finished Jul 06 06:27:22 PM PDT 24
Peak memory 219368 kb
Host smart-026d7040-1c6e-4df1-9cdb-ab3a2b379547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130946862 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.2130946862
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.490497281
Short name T575
Test name
Test status
Simulation time 69732896 ps
CPU time 0.96 seconds
Started Jul 06 06:27:22 PM PDT 24
Finished Jul 06 06:27:23 PM PDT 24
Peak memory 215852 kb
Host smart-a5b67b92-cab8-469d-a6bb-882ee5acba07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490497281 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.490497281
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.2713154736
Short name T730
Test name
Test status
Simulation time 43302096 ps
CPU time 0.89 seconds
Started Jul 06 06:27:29 PM PDT 24
Finished Jul 06 06:27:30 PM PDT 24
Peak memory 215604 kb
Host smart-f11a9567-fe7c-453a-99e7-837c0b416a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713154736 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.2713154736
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.275705408
Short name T780
Test name
Test status
Simulation time 163418835 ps
CPU time 3.68 seconds
Started Jul 06 06:27:25 PM PDT 24
Finished Jul 06 06:27:29 PM PDT 24
Peak memory 215620 kb
Host smart-65852eb3-d0a5-46d9-917a-6d6f84148e48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275705408 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.275705408
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.281014887
Short name T71
Test name
Test status
Simulation time 160461896468 ps
CPU time 2008.81 seconds
Started Jul 06 06:27:20 PM PDT 24
Finished Jul 06 07:00:49 PM PDT 24
Peak memory 230324 kb
Host smart-b95ada8c-b521-4935-9b0e-791680ae26e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281014887 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.281014887
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_genbits.3034366660
Short name T622
Test name
Test status
Simulation time 65226625 ps
CPU time 1.56 seconds
Started Jul 06 06:29:09 PM PDT 24
Finished Jul 06 06:29:11 PM PDT 24
Peak memory 218068 kb
Host smart-9de3df58-4f47-4d2d-a496-311a817ebe59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034366660 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.3034366660
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_alert.572432258
Short name T546
Test name
Test status
Simulation time 234232655 ps
CPU time 1.23 seconds
Started Jul 06 06:29:04 PM PDT 24
Finished Jul 06 06:29:05 PM PDT 24
Peak memory 219792 kb
Host smart-fabcb811-2bac-4756-87be-d04890815735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572432258 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_alert.572432258
Directory /workspace/181.edn_alert/latest

Test location /workspace/coverage/default/181.edn_genbits.3052977598
Short name T542
Test name
Test status
Simulation time 57401364 ps
CPU time 1.07 seconds
Started Jul 06 06:29:11 PM PDT 24
Finished Jul 06 06:29:13 PM PDT 24
Peak memory 217516 kb
Host smart-3b195c81-4822-4980-998b-ab1adb8d43a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052977598 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.3052977598
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_alert.3636747383
Short name T316
Test name
Test status
Simulation time 60317789 ps
CPU time 1.02 seconds
Started Jul 06 06:29:04 PM PDT 24
Finished Jul 06 06:29:05 PM PDT 24
Peak memory 220068 kb
Host smart-3a2f25ec-d37a-4a82-8f1a-36561e1865f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636747383 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_alert.3636747383
Directory /workspace/182.edn_alert/latest

Test location /workspace/coverage/default/182.edn_genbits.1054450117
Short name T401
Test name
Test status
Simulation time 76020387 ps
CPU time 2.76 seconds
Started Jul 06 06:29:09 PM PDT 24
Finished Jul 06 06:29:12 PM PDT 24
Peak memory 220480 kb
Host smart-416efbef-55d3-4ba9-84b8-7f7bf7fb7654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054450117 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.1054450117
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_alert.1952448629
Short name T946
Test name
Test status
Simulation time 117656160 ps
CPU time 1.11 seconds
Started Jul 06 06:29:04 PM PDT 24
Finished Jul 06 06:29:06 PM PDT 24
Peak memory 220152 kb
Host smart-c27f6b6a-f55f-421a-935c-2a67826a43b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952448629 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_alert.1952448629
Directory /workspace/183.edn_alert/latest

Test location /workspace/coverage/default/183.edn_genbits.4115340597
Short name T696
Test name
Test status
Simulation time 37974091 ps
CPU time 1.55 seconds
Started Jul 06 06:29:03 PM PDT 24
Finished Jul 06 06:29:04 PM PDT 24
Peak memory 218804 kb
Host smart-2fee70a0-1058-4144-a3c0-ec982dc3808b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115340597 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.4115340597
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_genbits.3243455959
Short name T352
Test name
Test status
Simulation time 61393860 ps
CPU time 1.4 seconds
Started Jul 06 06:29:06 PM PDT 24
Finished Jul 06 06:29:07 PM PDT 24
Peak memory 217800 kb
Host smart-41419bc4-2bf4-4b93-8330-d7dfff8ba37b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243455959 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.3243455959
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_alert.2223040028
Short name T944
Test name
Test status
Simulation time 105739960 ps
CPU time 1.11 seconds
Started Jul 06 06:29:06 PM PDT 24
Finished Jul 06 06:29:08 PM PDT 24
Peak memory 220044 kb
Host smart-67967fa7-05ba-40ae-b791-9b292a1da789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223040028 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_alert.2223040028
Directory /workspace/185.edn_alert/latest

Test location /workspace/coverage/default/185.edn_genbits.290408308
Short name T614
Test name
Test status
Simulation time 29554280 ps
CPU time 1.33 seconds
Started Jul 06 06:29:10 PM PDT 24
Finished Jul 06 06:29:12 PM PDT 24
Peak memory 219192 kb
Host smart-ca4ff2ee-7246-474b-ae02-d4dde6b57416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290408308 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.290408308
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_alert.2140685232
Short name T478
Test name
Test status
Simulation time 22176509 ps
CPU time 1.16 seconds
Started Jul 06 06:29:04 PM PDT 24
Finished Jul 06 06:29:06 PM PDT 24
Peak memory 220232 kb
Host smart-6dea55c3-2c88-4585-8626-c085056f86be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140685232 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_alert.2140685232
Directory /workspace/186.edn_alert/latest

Test location /workspace/coverage/default/186.edn_genbits.2172846299
Short name T587
Test name
Test status
Simulation time 550564636 ps
CPU time 3.31 seconds
Started Jul 06 06:29:04 PM PDT 24
Finished Jul 06 06:29:08 PM PDT 24
Peak memory 220200 kb
Host smart-06a02c24-d742-47ef-8476-08b47f30b577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172846299 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.2172846299
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_alert.2265404952
Short name T139
Test name
Test status
Simulation time 37889858 ps
CPU time 1.1 seconds
Started Jul 06 06:29:14 PM PDT 24
Finished Jul 06 06:29:16 PM PDT 24
Peak memory 221040 kb
Host smart-c9d5573d-3cdb-44f6-bece-575546e519b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265404952 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_alert.2265404952
Directory /workspace/187.edn_alert/latest

Test location /workspace/coverage/default/187.edn_genbits.2784880181
Short name T865
Test name
Test status
Simulation time 39338196 ps
CPU time 1.49 seconds
Started Jul 06 06:29:03 PM PDT 24
Finished Jul 06 06:29:05 PM PDT 24
Peak memory 217676 kb
Host smart-6d8c293b-93bb-4afd-aad2-9bba28367882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784880181 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.2784880181
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_alert.3005563193
Short name T579
Test name
Test status
Simulation time 353889171 ps
CPU time 1.2 seconds
Started Jul 06 06:29:12 PM PDT 24
Finished Jul 06 06:29:14 PM PDT 24
Peak memory 220064 kb
Host smart-43020583-dde3-467e-b069-20662036342f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005563193 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_alert.3005563193
Directory /workspace/188.edn_alert/latest

Test location /workspace/coverage/default/188.edn_genbits.1324887409
Short name T767
Test name
Test status
Simulation time 224962436 ps
CPU time 2.93 seconds
Started Jul 06 06:29:06 PM PDT 24
Finished Jul 06 06:29:09 PM PDT 24
Peak memory 219068 kb
Host smart-d336c7dc-228a-4aeb-9d86-489dd7e1c4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324887409 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.1324887409
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_genbits.3213417309
Short name T335
Test name
Test status
Simulation time 210075206 ps
CPU time 1.22 seconds
Started Jul 06 06:29:09 PM PDT 24
Finished Jul 06 06:29:10 PM PDT 24
Peak memory 217636 kb
Host smart-fb55254b-1d63-4a98-a1c0-9a0e74ce9476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213417309 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.3213417309
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.3227216637
Short name T545
Test name
Test status
Simulation time 23248652 ps
CPU time 1.1 seconds
Started Jul 06 06:27:29 PM PDT 24
Finished Jul 06 06:27:30 PM PDT 24
Peak memory 215976 kb
Host smart-98ef3cac-f04b-4c29-9ef0-faf28f53c554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227216637 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.3227216637
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.3195691362
Short name T27
Test name
Test status
Simulation time 22146993 ps
CPU time 1.04 seconds
Started Jul 06 06:27:33 PM PDT 24
Finished Jul 06 06:27:35 PM PDT 24
Peak memory 207076 kb
Host smart-bc791b47-ae10-4d30-ab2f-ea0d4fdfa8b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195691362 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.3195691362
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.2950396883
Short name T793
Test name
Test status
Simulation time 20488468 ps
CPU time 0.82 seconds
Started Jul 06 06:27:28 PM PDT 24
Finished Jul 06 06:27:30 PM PDT 24
Peak memory 215784 kb
Host smart-99b42247-422c-4381-893a-2a5df897eab4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950396883 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.2950396883
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.3803688617
Short name T949
Test name
Test status
Simulation time 95256439 ps
CPU time 1.11 seconds
Started Jul 06 06:27:25 PM PDT 24
Finished Jul 06 06:27:26 PM PDT 24
Peak memory 218900 kb
Host smart-1357cee2-97ef-4ddf-aa32-5f86c47bc474
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803688617 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.3803688617
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.1265937269
Short name T15
Test name
Test status
Simulation time 29455237 ps
CPU time 0.98 seconds
Started Jul 06 06:27:23 PM PDT 24
Finished Jul 06 06:27:25 PM PDT 24
Peak memory 224132 kb
Host smart-74fc1769-e337-4c07-b4ad-272753471e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265937269 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.1265937269
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_intr.647338911
Short name T677
Test name
Test status
Simulation time 21769789 ps
CPU time 1.22 seconds
Started Jul 06 06:27:23 PM PDT 24
Finished Jul 06 06:27:25 PM PDT 24
Peak memory 224280 kb
Host smart-e0644c98-851b-4eb9-af9e-052d7282f1d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647338911 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.647338911
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.3182166900
Short name T80
Test name
Test status
Simulation time 18307989 ps
CPU time 1 seconds
Started Jul 06 06:27:23 PM PDT 24
Finished Jul 06 06:27:25 PM PDT 24
Peak memory 215624 kb
Host smart-d91fe991-4c63-477a-95a8-074a5cded997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182166900 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.3182166900
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.131882133
Short name T442
Test name
Test status
Simulation time 71647693 ps
CPU time 1.29 seconds
Started Jul 06 06:27:22 PM PDT 24
Finished Jul 06 06:27:23 PM PDT 24
Peak memory 217512 kb
Host smart-7b09d371-2473-4cf8-9266-5f7bffd1cd2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131882133 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.131882133
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.2671606286
Short name T238
Test name
Test status
Simulation time 65869020210 ps
CPU time 732.93 seconds
Started Jul 06 06:27:24 PM PDT 24
Finished Jul 06 06:39:38 PM PDT 24
Peak memory 221424 kb
Host smart-efdad876-b573-4e71-89cb-a3ba404146db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671606286 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.2671606286
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_alert.1329883454
Short name T314
Test name
Test status
Simulation time 34078766 ps
CPU time 1.25 seconds
Started Jul 06 06:29:12 PM PDT 24
Finished Jul 06 06:29:15 PM PDT 24
Peak memory 219772 kb
Host smart-608e6b20-49a7-43e0-ae01-21943c86a5ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329883454 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_alert.1329883454
Directory /workspace/190.edn_alert/latest

Test location /workspace/coverage/default/190.edn_genbits.2289661088
Short name T397
Test name
Test status
Simulation time 59182451 ps
CPU time 1.32 seconds
Started Jul 06 06:29:04 PM PDT 24
Finished Jul 06 06:29:06 PM PDT 24
Peak memory 218864 kb
Host smart-c58cea3e-e119-4e31-9427-d2457d3bc6d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289661088 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.2289661088
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_alert.4023396062
Short name T627
Test name
Test status
Simulation time 65439479 ps
CPU time 1.07 seconds
Started Jul 06 06:29:12 PM PDT 24
Finished Jul 06 06:29:14 PM PDT 24
Peak memory 220276 kb
Host smart-398fc984-884f-4b8d-9bef-e3e46ff87065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023396062 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_alert.4023396062
Directory /workspace/191.edn_alert/latest

Test location /workspace/coverage/default/191.edn_genbits.1866902675
Short name T655
Test name
Test status
Simulation time 23484881 ps
CPU time 1.13 seconds
Started Jul 06 06:29:12 PM PDT 24
Finished Jul 06 06:29:14 PM PDT 24
Peak memory 218008 kb
Host smart-d72f823c-9905-4277-9872-d73084385927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866902675 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.1866902675
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_alert.2724111507
Short name T453
Test name
Test status
Simulation time 45276680 ps
CPU time 1.24 seconds
Started Jul 06 06:29:06 PM PDT 24
Finished Jul 06 06:29:08 PM PDT 24
Peak memory 220244 kb
Host smart-9964c032-ac40-4144-b51e-238a1e89e1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724111507 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_alert.2724111507
Directory /workspace/192.edn_alert/latest

Test location /workspace/coverage/default/192.edn_genbits.3681466145
Short name T512
Test name
Test status
Simulation time 152150901 ps
CPU time 2.58 seconds
Started Jul 06 06:29:12 PM PDT 24
Finished Jul 06 06:29:16 PM PDT 24
Peak memory 220584 kb
Host smart-27daa4d4-f481-4bc2-a243-26a5d79965fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681466145 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.3681466145
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_alert.945182389
Short name T517
Test name
Test status
Simulation time 102263706 ps
CPU time 1.29 seconds
Started Jul 06 06:29:09 PM PDT 24
Finished Jul 06 06:29:11 PM PDT 24
Peak memory 220280 kb
Host smart-857cef42-671d-4aa4-bfb8-ab6392ada7e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945182389 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_alert.945182389
Directory /workspace/193.edn_alert/latest

Test location /workspace/coverage/default/193.edn_genbits.2687751705
Short name T926
Test name
Test status
Simulation time 58384958 ps
CPU time 1.02 seconds
Started Jul 06 06:29:06 PM PDT 24
Finished Jul 06 06:29:07 PM PDT 24
Peak memory 217640 kb
Host smart-0ac15754-7ded-4048-8e8c-e75f29046779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687751705 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.2687751705
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_alert.694732231
Short name T712
Test name
Test status
Simulation time 82429252 ps
CPU time 1.15 seconds
Started Jul 06 06:29:05 PM PDT 24
Finished Jul 06 06:29:06 PM PDT 24
Peak memory 218844 kb
Host smart-f59284f1-e917-4985-b1fd-6b878570d588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694732231 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_alert.694732231
Directory /workspace/194.edn_alert/latest

Test location /workspace/coverage/default/195.edn_alert.3563850478
Short name T718
Test name
Test status
Simulation time 52318777 ps
CPU time 1.32 seconds
Started Jul 06 06:29:06 PM PDT 24
Finished Jul 06 06:29:08 PM PDT 24
Peak memory 216064 kb
Host smart-5e200831-0afc-473c-8577-de535c0b9db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563850478 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_alert.3563850478
Directory /workspace/195.edn_alert/latest

Test location /workspace/coverage/default/195.edn_genbits.4261488255
Short name T544
Test name
Test status
Simulation time 28635558 ps
CPU time 1.31 seconds
Started Jul 06 06:29:06 PM PDT 24
Finished Jul 06 06:29:08 PM PDT 24
Peak memory 219060 kb
Host smart-15633b03-b876-4e2b-a1fa-3ae8cfbd21d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261488255 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.4261488255
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_genbits.683653981
Short name T399
Test name
Test status
Simulation time 58341737 ps
CPU time 1.03 seconds
Started Jul 06 06:29:02 PM PDT 24
Finished Jul 06 06:29:04 PM PDT 24
Peak memory 217576 kb
Host smart-baa2c94e-d0cd-4832-bffa-dc8f6c31b461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683653981 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.683653981
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_alert.990916487
Short name T511
Test name
Test status
Simulation time 28500515 ps
CPU time 1.26 seconds
Started Jul 06 06:29:08 PM PDT 24
Finished Jul 06 06:29:10 PM PDT 24
Peak memory 216056 kb
Host smart-8ae2dea9-ace2-4d62-85e8-450b2a397c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990916487 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_alert.990916487
Directory /workspace/197.edn_alert/latest

Test location /workspace/coverage/default/198.edn_alert.1748608486
Short name T69
Test name
Test status
Simulation time 35685452 ps
CPU time 1.09 seconds
Started Jul 06 06:29:05 PM PDT 24
Finished Jul 06 06:29:07 PM PDT 24
Peak memory 220316 kb
Host smart-5b2d8af9-10bc-406a-a022-07672839da31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748608486 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_alert.1748608486
Directory /workspace/198.edn_alert/latest

Test location /workspace/coverage/default/198.edn_genbits.3759596617
Short name T601
Test name
Test status
Simulation time 64186314 ps
CPU time 1.25 seconds
Started Jul 06 06:29:11 PM PDT 24
Finished Jul 06 06:29:14 PM PDT 24
Peak memory 217676 kb
Host smart-732b9da4-c96d-46b7-9a8d-33e6cd1dc9f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759596617 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.3759596617
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_alert.1956571785
Short name T738
Test name
Test status
Simulation time 23528580 ps
CPU time 1.22 seconds
Started Jul 06 06:29:08 PM PDT 24
Finished Jul 06 06:29:10 PM PDT 24
Peak memory 219192 kb
Host smart-36817f78-f557-4c5b-9533-5cd2448eef22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956571785 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_alert.1956571785
Directory /workspace/199.edn_alert/latest

Test location /workspace/coverage/default/199.edn_genbits.1978167275
Short name T765
Test name
Test status
Simulation time 37739611 ps
CPU time 1.38 seconds
Started Jul 06 06:29:06 PM PDT 24
Finished Jul 06 06:29:08 PM PDT 24
Peak memory 217560 kb
Host smart-7a8b7f7d-4157-4015-a7a2-66f2f06ac4cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978167275 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.1978167275
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.1547472319
Short name T219
Test name
Test status
Simulation time 26136038 ps
CPU time 1.25 seconds
Started Jul 06 06:26:49 PM PDT 24
Finished Jul 06 06:26:51 PM PDT 24
Peak memory 220172 kb
Host smart-8d538db0-065a-431d-889b-81276c06c017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547472319 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.1547472319
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.346321742
Short name T920
Test name
Test status
Simulation time 46462356 ps
CPU time 0.98 seconds
Started Jul 06 06:26:54 PM PDT 24
Finished Jul 06 06:26:55 PM PDT 24
Peak memory 215524 kb
Host smart-e8502794-b1e6-46ba-89b7-cc204b565eda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346321742 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.346321742
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.3981821664
Short name T822
Test name
Test status
Simulation time 37535574 ps
CPU time 0.88 seconds
Started Jul 06 06:26:49 PM PDT 24
Finished Jul 06 06:26:51 PM PDT 24
Peak memory 216548 kb
Host smart-39d85841-f946-4855-9818-14d6a2210a4c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981821664 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.3981821664
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.2116954649
Short name T137
Test name
Test status
Simulation time 51496959 ps
CPU time 1.12 seconds
Started Jul 06 06:26:54 PM PDT 24
Finished Jul 06 06:26:56 PM PDT 24
Peak memory 220136 kb
Host smart-acbd7037-ab42-4aea-8084-3ae91880ba1f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116954649 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.2116954649
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.1468097786
Short name T633
Test name
Test status
Simulation time 66972623 ps
CPU time 1 seconds
Started Jul 06 06:26:49 PM PDT 24
Finished Jul 06 06:26:50 PM PDT 24
Peak memory 229508 kb
Host smart-b205d761-c39f-4311-8268-ecb62db5f008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468097786 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.1468097786
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.3191492837
Short name T883
Test name
Test status
Simulation time 57782332 ps
CPU time 1.27 seconds
Started Jul 06 06:26:49 PM PDT 24
Finished Jul 06 06:26:51 PM PDT 24
Peak memory 219784 kb
Host smart-c347f880-270c-4eb1-b8b3-a99a30b2ff85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191492837 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.3191492837
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.1206746475
Short name T108
Test name
Test status
Simulation time 35987643 ps
CPU time 0.87 seconds
Started Jul 06 06:26:50 PM PDT 24
Finished Jul 06 06:26:51 PM PDT 24
Peak memory 215996 kb
Host smart-21a499cd-fddd-439d-8c12-2c3552550a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206746475 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.1206746475
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.4095083867
Short name T595
Test name
Test status
Simulation time 42028940 ps
CPU time 0.88 seconds
Started Jul 06 06:26:51 PM PDT 24
Finished Jul 06 06:26:52 PM PDT 24
Peak memory 207416 kb
Host smart-e132c409-3f0f-4635-bca8-1ac1c9b4a305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095083867 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.4095083867
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_sec_cm.3898992679
Short name T19
Test name
Test status
Simulation time 721138736 ps
CPU time 7.12 seconds
Started Jul 06 06:26:56 PM PDT 24
Finished Jul 06 06:27:03 PM PDT 24
Peak memory 236448 kb
Host smart-03920257-156e-4e3b-9dc3-a86e794fab77
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898992679 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.3898992679
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.2051255388
Short name T668
Test name
Test status
Simulation time 20383481 ps
CPU time 0.95 seconds
Started Jul 06 06:26:48 PM PDT 24
Finished Jul 06 06:26:49 PM PDT 24
Peak memory 215608 kb
Host smart-894cf112-bca7-404d-a8e0-b2fc379a7cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051255388 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.2051255388
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.3843221677
Short name T800
Test name
Test status
Simulation time 60897255 ps
CPU time 1.49 seconds
Started Jul 06 06:26:50 PM PDT 24
Finished Jul 06 06:26:52 PM PDT 24
Peak memory 218812 kb
Host smart-7d45ad10-ad50-4d1b-84d0-0a2d6461aa60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843221677 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.3843221677
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_alert.4086175176
Short name T220
Test name
Test status
Simulation time 55224291 ps
CPU time 1.26 seconds
Started Jul 06 06:27:29 PM PDT 24
Finished Jul 06 06:27:30 PM PDT 24
Peak memory 221788 kb
Host smart-5e3bbdbd-4a5c-4040-8036-85fe06e95456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086175176 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.4086175176
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.3631783273
Short name T619
Test name
Test status
Simulation time 12995860 ps
CPU time 0.87 seconds
Started Jul 06 06:27:26 PM PDT 24
Finished Jul 06 06:27:27 PM PDT 24
Peak memory 207264 kb
Host smart-4d8e03d7-8d07-4c0b-9c0a-af47efa2a005
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631783273 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.3631783273
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_err.3514183132
Short name T374
Test name
Test status
Simulation time 126912991 ps
CPU time 1.09 seconds
Started Jul 06 06:27:31 PM PDT 24
Finished Jul 06 06:27:32 PM PDT 24
Peak memory 220104 kb
Host smart-f7fcd894-f746-4670-aeb4-23e41a16fd61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514183132 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.3514183132
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.3080303410
Short name T12
Test name
Test status
Simulation time 38576702 ps
CPU time 1.48 seconds
Started Jul 06 06:27:27 PM PDT 24
Finished Jul 06 06:27:28 PM PDT 24
Peak memory 220480 kb
Host smart-fecb31a1-b3cf-480b-b745-a9fcb314ef60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080303410 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.3080303410
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.2659371982
Short name T551
Test name
Test status
Simulation time 26836410 ps
CPU time 0.93 seconds
Started Jul 06 06:27:29 PM PDT 24
Finished Jul 06 06:27:31 PM PDT 24
Peak memory 215744 kb
Host smart-b6d88b57-5695-405b-8e16-9375a1cda052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659371982 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.2659371982
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.3542623295
Short name T461
Test name
Test status
Simulation time 26041189 ps
CPU time 0.96 seconds
Started Jul 06 06:27:26 PM PDT 24
Finished Jul 06 06:27:28 PM PDT 24
Peak memory 215672 kb
Host smart-6b2dc1ac-801a-469f-a175-28613b6125f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542623295 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.3542623295
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.320462089
Short name T429
Test name
Test status
Simulation time 988820113 ps
CPU time 4.53 seconds
Started Jul 06 06:27:27 PM PDT 24
Finished Jul 06 06:27:32 PM PDT 24
Peak memory 215668 kb
Host smart-248310f4-e2ed-41f3-8e68-4f8b1badb0e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320462089 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.320462089
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.2429246122
Short name T604
Test name
Test status
Simulation time 68549394840 ps
CPU time 1485.72 seconds
Started Jul 06 06:27:29 PM PDT 24
Finished Jul 06 06:52:15 PM PDT 24
Peak memory 224292 kb
Host smart-fb033e5f-5f39-4446-a2a2-2c995f2a0629
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429246122 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.2429246122
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.653938072
Short name T884
Test name
Test status
Simulation time 47214660 ps
CPU time 1.59 seconds
Started Jul 06 06:29:27 PM PDT 24
Finished Jul 06 06:29:29 PM PDT 24
Peak memory 220072 kb
Host smart-005ca1f2-2961-4074-b7b8-53ff8b02a660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653938072 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.653938072
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.2021133226
Short name T11
Test name
Test status
Simulation time 26123871 ps
CPU time 1.19 seconds
Started Jul 06 06:29:18 PM PDT 24
Finished Jul 06 06:29:19 PM PDT 24
Peak memory 218876 kb
Host smart-b206d4ab-d51b-4a8b-af76-c4f1d4c816b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021133226 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.2021133226
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.2214771561
Short name T380
Test name
Test status
Simulation time 92963312 ps
CPU time 1.12 seconds
Started Jul 06 06:29:06 PM PDT 24
Finished Jul 06 06:29:07 PM PDT 24
Peak memory 217716 kb
Host smart-c9a1c630-1198-44f8-937a-e26516ab9f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214771561 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.2214771561
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.1218456709
Short name T486
Test name
Test status
Simulation time 42750149 ps
CPU time 1.05 seconds
Started Jul 06 06:29:09 PM PDT 24
Finished Jul 06 06:29:11 PM PDT 24
Peak memory 217752 kb
Host smart-e4081bac-7270-4461-a5b6-818fc3118243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218456709 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.1218456709
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.3511031080
Short name T555
Test name
Test status
Simulation time 143196650 ps
CPU time 1.59 seconds
Started Jul 06 06:29:12 PM PDT 24
Finished Jul 06 06:29:14 PM PDT 24
Peak memory 219328 kb
Host smart-41125f78-ab77-4287-bcd3-58dd5246ee26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511031080 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.3511031080
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.4263455625
Short name T908
Test name
Test status
Simulation time 35443517 ps
CPU time 1.03 seconds
Started Jul 06 06:29:10 PM PDT 24
Finished Jul 06 06:29:12 PM PDT 24
Peak memory 217848 kb
Host smart-2c508013-360f-42c7-8bb8-eb9620b9b95e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263455625 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.4263455625
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.1994586930
Short name T477
Test name
Test status
Simulation time 71335536 ps
CPU time 1.18 seconds
Started Jul 06 06:29:09 PM PDT 24
Finished Jul 06 06:29:11 PM PDT 24
Peak memory 217924 kb
Host smart-9465b140-1793-4ff5-a6a2-ea9cbc10ed88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994586930 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.1994586930
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.851119318
Short name T47
Test name
Test status
Simulation time 303633712 ps
CPU time 1.8 seconds
Started Jul 06 06:29:12 PM PDT 24
Finished Jul 06 06:29:15 PM PDT 24
Peak memory 219428 kb
Host smart-044d9166-5a10-4c6c-bf53-7eed0132212e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851119318 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.851119318
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.2995678835
Short name T327
Test name
Test status
Simulation time 33012137 ps
CPU time 1.39 seconds
Started Jul 06 06:29:08 PM PDT 24
Finished Jul 06 06:29:10 PM PDT 24
Peak memory 215612 kb
Host smart-67e90a8c-667e-4e7c-8850-3a62f9ce3ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995678835 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.2995678835
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.3046629545
Short name T537
Test name
Test status
Simulation time 37318280 ps
CPU time 1.26 seconds
Started Jul 06 06:29:24 PM PDT 24
Finished Jul 06 06:29:25 PM PDT 24
Peak memory 218924 kb
Host smart-3fb6926e-5b46-4e70-96d1-572fa453fb2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046629545 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.3046629545
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.3249354832
Short name T188
Test name
Test status
Simulation time 81195034 ps
CPU time 1.23 seconds
Started Jul 06 06:27:36 PM PDT 24
Finished Jul 06 06:27:38 PM PDT 24
Peak memory 219728 kb
Host smart-a61cb47f-4ce4-40db-91eb-930bcce67d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249354832 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.3249354832
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.2651211342
Short name T866
Test name
Test status
Simulation time 49316798 ps
CPU time 0.89 seconds
Started Jul 06 06:27:27 PM PDT 24
Finished Jul 06 06:27:29 PM PDT 24
Peak memory 207100 kb
Host smart-61f68320-44f0-4301-b53c-b4a0836e805b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651211342 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.2651211342
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.1823071541
Short name T206
Test name
Test status
Simulation time 30875841 ps
CPU time 0.87 seconds
Started Jul 06 06:27:36 PM PDT 24
Finished Jul 06 06:27:37 PM PDT 24
Peak memory 216528 kb
Host smart-9c8d8906-b608-4c06-aec8-0946facc8b9b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823071541 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.1823071541
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_err.3224389771
Short name T427
Test name
Test status
Simulation time 29106794 ps
CPU time 0.92 seconds
Started Jul 06 06:27:28 PM PDT 24
Finished Jul 06 06:27:29 PM PDT 24
Peak memory 218692 kb
Host smart-4989465e-95dc-4686-9c7c-150e6a22ced4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224389771 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.3224389771
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.1132765020
Short name T580
Test name
Test status
Simulation time 69375135 ps
CPU time 1.28 seconds
Started Jul 06 06:27:27 PM PDT 24
Finished Jul 06 06:27:29 PM PDT 24
Peak memory 217676 kb
Host smart-c178c6cd-90d1-48b7-9bd5-3c3fc5be6193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132765020 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.1132765020
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.1109973276
Short name T39
Test name
Test status
Simulation time 35120347 ps
CPU time 0.86 seconds
Started Jul 06 06:27:29 PM PDT 24
Finished Jul 06 06:27:31 PM PDT 24
Peak memory 215884 kb
Host smart-017871b9-cc8a-4160-9b07-f1998d56c966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109973276 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.1109973276
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.4039703951
Short name T644
Test name
Test status
Simulation time 17037117 ps
CPU time 0.92 seconds
Started Jul 06 06:27:26 PM PDT 24
Finished Jul 06 06:27:27 PM PDT 24
Peak memory 215596 kb
Host smart-2ac8979b-3e35-4a16-a2d4-0a2459eb3b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039703951 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.4039703951
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.1376245268
Short name T886
Test name
Test status
Simulation time 396456878 ps
CPU time 7.21 seconds
Started Jul 06 06:27:29 PM PDT 24
Finished Jul 06 06:27:37 PM PDT 24
Peak memory 217340 kb
Host smart-d9da3e99-a8a8-49d2-ad96-860bfeff7da0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376245268 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.1376245268
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.4165878607
Short name T847
Test name
Test status
Simulation time 16284830118 ps
CPU time 360.29 seconds
Started Jul 06 06:27:32 PM PDT 24
Finished Jul 06 06:33:32 PM PDT 24
Peak memory 219048 kb
Host smart-d1dc114b-d822-4b2e-b6a0-d97638a3e12c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165878607 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.4165878607
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.2222987932
Short name T412
Test name
Test status
Simulation time 61653889 ps
CPU time 1.07 seconds
Started Jul 06 06:29:12 PM PDT 24
Finished Jul 06 06:29:14 PM PDT 24
Peak memory 217756 kb
Host smart-7a5059cc-da12-4592-a4ba-2832a4fe8604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222987932 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.2222987932
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.2765412794
Short name T623
Test name
Test status
Simulation time 38078701 ps
CPU time 1.33 seconds
Started Jul 06 06:29:09 PM PDT 24
Finished Jul 06 06:29:11 PM PDT 24
Peak memory 218664 kb
Host smart-752ba2ba-73c5-4fb3-ab7c-b9db9f67555f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765412794 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.2765412794
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.864767279
Short name T652
Test name
Test status
Simulation time 50485277 ps
CPU time 1.79 seconds
Started Jul 06 06:29:18 PM PDT 24
Finished Jul 06 06:29:20 PM PDT 24
Peak memory 218780 kb
Host smart-15842bcb-a784-4135-9fd2-10feb2e58183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864767279 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.864767279
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.3288417751
Short name T964
Test name
Test status
Simulation time 45603827 ps
CPU time 1.76 seconds
Started Jul 06 06:29:15 PM PDT 24
Finished Jul 06 06:29:17 PM PDT 24
Peak memory 218984 kb
Host smart-a484244f-0871-4da3-aae0-78f30aa7b63a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288417751 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.3288417751
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.161234250
Short name T404
Test name
Test status
Simulation time 129773891 ps
CPU time 1.06 seconds
Started Jul 06 06:29:28 PM PDT 24
Finished Jul 06 06:29:30 PM PDT 24
Peak memory 217688 kb
Host smart-15747f39-9058-49bc-8dff-87901b0bedb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161234250 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.161234250
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.1227813637
Short name T480
Test name
Test status
Simulation time 121770529 ps
CPU time 2.58 seconds
Started Jul 06 06:29:27 PM PDT 24
Finished Jul 06 06:29:30 PM PDT 24
Peak memory 220260 kb
Host smart-00573f5d-a08b-47da-a476-bb14e0e2ff63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227813637 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.1227813637
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.3768550012
Short name T876
Test name
Test status
Simulation time 49155895 ps
CPU time 1.18 seconds
Started Jul 06 06:29:11 PM PDT 24
Finished Jul 06 06:29:13 PM PDT 24
Peak memory 218940 kb
Host smart-4225f2b5-ecc6-4e40-a759-c3b901fee704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768550012 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.3768550012
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.1307519605
Short name T379
Test name
Test status
Simulation time 100820356 ps
CPU time 1.06 seconds
Started Jul 06 06:29:08 PM PDT 24
Finished Jul 06 06:29:10 PM PDT 24
Peak memory 217640 kb
Host smart-45988997-0ad2-4fc1-90d1-890a0ab24895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307519605 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.1307519605
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.2669916245
Short name T467
Test name
Test status
Simulation time 44922923 ps
CPU time 1.52 seconds
Started Jul 06 06:29:10 PM PDT 24
Finished Jul 06 06:29:12 PM PDT 24
Peak memory 218972 kb
Host smart-3d8cb581-bcd5-4e38-acda-d58a1c2f9f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669916245 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.2669916245
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.1518309195
Short name T524
Test name
Test status
Simulation time 26922148 ps
CPU time 1.14 seconds
Started Jul 06 06:29:12 PM PDT 24
Finished Jul 06 06:29:14 PM PDT 24
Peak memory 217676 kb
Host smart-3fd30b4b-70ad-441a-b2aa-382882746981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518309195 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.1518309195
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert_test.2950665853
Short name T671
Test name
Test status
Simulation time 181029274 ps
CPU time 0.88 seconds
Started Jul 06 06:27:28 PM PDT 24
Finished Jul 06 06:27:29 PM PDT 24
Peak memory 206880 kb
Host smart-aca8d78f-2878-439a-a4b9-08cd18efefbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950665853 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.2950665853
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.4051918046
Short name T288
Test name
Test status
Simulation time 35441799 ps
CPU time 1.19 seconds
Started Jul 06 06:27:27 PM PDT 24
Finished Jul 06 06:27:28 PM PDT 24
Peak memory 218988 kb
Host smart-083418e7-a0f6-4cd4-a109-ce3b2543973a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051918046 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.4051918046
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.2817165261
Short name T68
Test name
Test status
Simulation time 19505386 ps
CPU time 1.11 seconds
Started Jul 06 06:27:27 PM PDT 24
Finished Jul 06 06:27:29 PM PDT 24
Peak memory 219852 kb
Host smart-e75f5bb2-0952-4e9c-b45a-15d59b02d861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817165261 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.2817165261
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.3163231318
Short name T588
Test name
Test status
Simulation time 27939979 ps
CPU time 1.35 seconds
Started Jul 06 06:27:32 PM PDT 24
Finished Jul 06 06:27:34 PM PDT 24
Peak memory 218616 kb
Host smart-cf2701d2-b9b1-493c-a0d6-7206635c68ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163231318 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.3163231318
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.3561716292
Short name T922
Test name
Test status
Simulation time 39206189 ps
CPU time 0.89 seconds
Started Jul 06 06:27:25 PM PDT 24
Finished Jul 06 06:27:26 PM PDT 24
Peak memory 215824 kb
Host smart-8eb71dcf-6d30-4781-b4e3-99dd15a58b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561716292 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.3561716292
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.274843634
Short name T375
Test name
Test status
Simulation time 18038941 ps
CPU time 1.04 seconds
Started Jul 06 06:27:25 PM PDT 24
Finished Jul 06 06:27:26 PM PDT 24
Peak memory 215744 kb
Host smart-a7753b70-b06c-422e-911c-ce4e979986c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274843634 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.274843634
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.2895409058
Short name T395
Test name
Test status
Simulation time 40902058 ps
CPU time 1.38 seconds
Started Jul 06 06:27:28 PM PDT 24
Finished Jul 06 06:27:30 PM PDT 24
Peak memory 217616 kb
Host smart-b87a759c-a521-41a3-8f9c-def870be3af8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895409058 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.2895409058
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.4080843390
Short name T799
Test name
Test status
Simulation time 311865937675 ps
CPU time 1736.72 seconds
Started Jul 06 06:27:32 PM PDT 24
Finished Jul 06 06:56:29 PM PDT 24
Peak memory 226272 kb
Host smart-4c0949bd-1fe4-402c-8e5c-3f967d786e07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080843390 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.4080843390
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.212760816
Short name T864
Test name
Test status
Simulation time 48906011 ps
CPU time 1.87 seconds
Started Jul 06 06:29:10 PM PDT 24
Finished Jul 06 06:29:12 PM PDT 24
Peak memory 219060 kb
Host smart-1b650d00-61fb-4038-af56-46754927635a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212760816 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.212760816
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.2608332327
Short name T947
Test name
Test status
Simulation time 47374270 ps
CPU time 1.3 seconds
Started Jul 06 06:29:09 PM PDT 24
Finished Jul 06 06:29:11 PM PDT 24
Peak memory 220116 kb
Host smart-c4d5e639-9c4b-461d-8bfd-fde18d048d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608332327 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.2608332327
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.2382679916
Short name T558
Test name
Test status
Simulation time 240574509 ps
CPU time 2.17 seconds
Started Jul 06 06:29:10 PM PDT 24
Finished Jul 06 06:29:13 PM PDT 24
Peak memory 220656 kb
Host smart-eb9e2981-195d-4b56-a7b1-59bc9602ee2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382679916 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.2382679916
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.540159564
Short name T887
Test name
Test status
Simulation time 27038674 ps
CPU time 1.15 seconds
Started Jul 06 06:29:27 PM PDT 24
Finished Jul 06 06:29:29 PM PDT 24
Peak memory 220156 kb
Host smart-e1b0ff92-ecf9-498d-9135-5fe54adb242c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540159564 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.540159564
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.380464688
Short name T561
Test name
Test status
Simulation time 38301915 ps
CPU time 1.37 seconds
Started Jul 06 06:29:11 PM PDT 24
Finished Jul 06 06:29:13 PM PDT 24
Peak memory 215664 kb
Host smart-071ffddd-0fbb-47cf-a373-78c69dc348c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380464688 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.380464688
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.1789385340
Short name T618
Test name
Test status
Simulation time 75096465 ps
CPU time 1.45 seconds
Started Jul 06 06:29:11 PM PDT 24
Finished Jul 06 06:29:13 PM PDT 24
Peak memory 219492 kb
Host smart-95d332d8-5f7f-4a56-872c-a239a53b5b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789385340 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.1789385340
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.2327938964
Short name T662
Test name
Test status
Simulation time 163475038 ps
CPU time 1.09 seconds
Started Jul 06 06:29:19 PM PDT 24
Finished Jul 06 06:29:20 PM PDT 24
Peak memory 217484 kb
Host smart-b0ddc4e4-2b83-4345-9bbc-376c34f0488b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327938964 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.2327938964
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.3333384006
Short name T336
Test name
Test status
Simulation time 42706842 ps
CPU time 1.58 seconds
Started Jul 06 06:29:12 PM PDT 24
Finished Jul 06 06:29:15 PM PDT 24
Peak memory 218888 kb
Host smart-fa3e0cd4-41c3-4d0d-9dac-a7e05ee80f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333384006 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.3333384006
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.1647761796
Short name T354
Test name
Test status
Simulation time 74393969 ps
CPU time 1.06 seconds
Started Jul 06 06:29:09 PM PDT 24
Finished Jul 06 06:29:11 PM PDT 24
Peak memory 215644 kb
Host smart-0f93a4bb-c2ad-4941-bae0-93901fa109f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647761796 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.1647761796
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.1464912654
Short name T788
Test name
Test status
Simulation time 37611799 ps
CPU time 1.11 seconds
Started Jul 06 06:29:11 PM PDT 24
Finished Jul 06 06:29:13 PM PDT 24
Peak memory 217592 kb
Host smart-fa487421-8289-4e85-8c8d-fe5567c8e247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464912654 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.1464912654
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.3386203124
Short name T179
Test name
Test status
Simulation time 29792596 ps
CPU time 1.12 seconds
Started Jul 06 06:27:31 PM PDT 24
Finished Jul 06 06:27:32 PM PDT 24
Peak memory 218668 kb
Host smart-ef79496a-90bd-4a9b-87c4-031f027c7bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386203124 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.3386203124
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.1954135021
Short name T984
Test name
Test status
Simulation time 15593017 ps
CPU time 0.91 seconds
Started Jul 06 06:27:26 PM PDT 24
Finished Jul 06 06:27:27 PM PDT 24
Peak memory 207044 kb
Host smart-cc28b8e7-e922-4454-ae25-e4843aa89b38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954135021 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.1954135021
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.2475297310
Short name T879
Test name
Test status
Simulation time 13176855 ps
CPU time 0.89 seconds
Started Jul 06 06:27:30 PM PDT 24
Finished Jul 06 06:27:31 PM PDT 24
Peak memory 216712 kb
Host smart-d5bdb5a0-0088-4887-b117-0b62f09115b1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475297310 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.2475297310
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.1688359473
Short name T773
Test name
Test status
Simulation time 44684547 ps
CPU time 1.3 seconds
Started Jul 06 06:27:50 PM PDT 24
Finished Jul 06 06:27:51 PM PDT 24
Peak memory 218792 kb
Host smart-49c9a3c6-3722-4d7c-a3e1-a7351ad64adb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688359473 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.1688359473
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_genbits.1439564993
Short name T629
Test name
Test status
Simulation time 149771574 ps
CPU time 3.11 seconds
Started Jul 06 06:27:29 PM PDT 24
Finished Jul 06 06:27:33 PM PDT 24
Peak memory 217868 kb
Host smart-69443894-44fd-4d6c-8b22-2bab92bc2cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439564993 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.1439564993
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.4277953933
Short name T863
Test name
Test status
Simulation time 27322745 ps
CPU time 1.03 seconds
Started Jul 06 06:27:36 PM PDT 24
Finished Jul 06 06:27:38 PM PDT 24
Peak memory 215700 kb
Host smart-6ec9f3e7-ba09-45e5-b871-1bcb1380667f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277953933 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.4277953933
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.3218013937
Short name T825
Test name
Test status
Simulation time 20309212 ps
CPU time 0.96 seconds
Started Jul 06 06:27:28 PM PDT 24
Finished Jul 06 06:27:29 PM PDT 24
Peak memory 215624 kb
Host smart-90af5da9-a42a-4d0b-8c66-0ef6fcbaa508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218013937 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.3218013937
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.1130127446
Short name T378
Test name
Test status
Simulation time 758672562 ps
CPU time 5.36 seconds
Started Jul 06 06:27:29 PM PDT 24
Finished Jul 06 06:27:35 PM PDT 24
Peak memory 215624 kb
Host smart-162a5c83-1e7e-4f2c-b959-aad47746da37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130127446 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.1130127446
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.3322570571
Short name T720
Test name
Test status
Simulation time 37838875380 ps
CPU time 913.16 seconds
Started Jul 06 06:27:27 PM PDT 24
Finished Jul 06 06:42:41 PM PDT 24
Peak memory 220856 kb
Host smart-0d31a56f-ff5c-41f1-99e4-0503f035aaa6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322570571 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.3322570571
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.557865162
Short name T244
Test name
Test status
Simulation time 38415997 ps
CPU time 1.45 seconds
Started Jul 06 06:29:12 PM PDT 24
Finished Jul 06 06:29:15 PM PDT 24
Peak memory 218840 kb
Host smart-b43038e6-04f5-4f2d-989b-2dd7e28b1597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557865162 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.557865162
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.2300345022
Short name T957
Test name
Test status
Simulation time 42512338 ps
CPU time 1.06 seconds
Started Jul 06 06:29:36 PM PDT 24
Finished Jul 06 06:29:37 PM PDT 24
Peak memory 217736 kb
Host smart-1600aced-8c13-4f83-bb9b-d82a7f85b64a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300345022 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.2300345022
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.2624138415
Short name T768
Test name
Test status
Simulation time 58094270 ps
CPU time 1.98 seconds
Started Jul 06 06:29:08 PM PDT 24
Finished Jul 06 06:29:11 PM PDT 24
Peak memory 218692 kb
Host smart-d70c6b5c-8948-43cd-9cab-b17cf2d22ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624138415 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.2624138415
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.4027959701
Short name T828
Test name
Test status
Simulation time 74552735 ps
CPU time 2.35 seconds
Started Jul 06 06:29:28 PM PDT 24
Finished Jul 06 06:29:31 PM PDT 24
Peak memory 220096 kb
Host smart-e5a434f4-ca53-4af0-bda0-242300c89bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027959701 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.4027959701
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.4046380753
Short name T802
Test name
Test status
Simulation time 87145899 ps
CPU time 1.26 seconds
Started Jul 06 06:29:11 PM PDT 24
Finished Jul 06 06:29:12 PM PDT 24
Peak memory 217796 kb
Host smart-615434a9-96a8-45a8-9e45-32b912c44b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046380753 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.4046380753
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.2200478762
Short name T899
Test name
Test status
Simulation time 33092911 ps
CPU time 1.23 seconds
Started Jul 06 06:29:11 PM PDT 24
Finished Jul 06 06:29:13 PM PDT 24
Peak memory 217844 kb
Host smart-8db7b703-6ae4-4231-a2bc-67c436d8b6ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200478762 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.2200478762
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.2134305477
Short name T92
Test name
Test status
Simulation time 48262903 ps
CPU time 1.4 seconds
Started Jul 06 06:29:10 PM PDT 24
Finished Jul 06 06:29:12 PM PDT 24
Peak memory 217844 kb
Host smart-fafd00fc-d0a0-4bfd-b9fb-74bd20132720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134305477 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.2134305477
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.449347130
Short name T690
Test name
Test status
Simulation time 71576382 ps
CPU time 1.28 seconds
Started Jul 06 06:29:11 PM PDT 24
Finished Jul 06 06:29:13 PM PDT 24
Peak memory 217620 kb
Host smart-a25951b9-2637-419c-a4aa-da8653c741a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449347130 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.449347130
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.2674425190
Short name T779
Test name
Test status
Simulation time 214274137 ps
CPU time 0.98 seconds
Started Jul 06 06:29:36 PM PDT 24
Finished Jul 06 06:29:37 PM PDT 24
Peak memory 217468 kb
Host smart-76e431f2-ba69-4a17-bec7-f4e0a7b11f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674425190 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.2674425190
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.909379848
Short name T813
Test name
Test status
Simulation time 80158592 ps
CPU time 1.1 seconds
Started Jul 06 06:27:28 PM PDT 24
Finished Jul 06 06:27:29 PM PDT 24
Peak memory 218944 kb
Host smart-fe8998d5-24e2-4412-99de-439786c7d090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909379848 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.909379848
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.922598382
Short name T900
Test name
Test status
Simulation time 19804447 ps
CPU time 1.02 seconds
Started Jul 06 06:27:36 PM PDT 24
Finished Jul 06 06:27:37 PM PDT 24
Peak memory 207072 kb
Host smart-72fffbd2-1d28-4a75-82d6-56c91443b252
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922598382 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.922598382
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.909373834
Short name T818
Test name
Test status
Simulation time 14166431 ps
CPU time 0.93 seconds
Started Jul 06 06:27:29 PM PDT 24
Finished Jul 06 06:27:31 PM PDT 24
Peak memory 216568 kb
Host smart-328ba9e5-3686-4399-8c2d-ba25249de801
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909373834 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.909373834
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.1439238700
Short name T966
Test name
Test status
Simulation time 33248549 ps
CPU time 1.15 seconds
Started Jul 06 06:27:33 PM PDT 24
Finished Jul 06 06:27:35 PM PDT 24
Peak memory 217272 kb
Host smart-3df274d4-57ff-48dc-b01c-f986b7f892c1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439238700 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.1439238700
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.2645198509
Short name T184
Test name
Test status
Simulation time 36408279 ps
CPU time 1.07 seconds
Started Jul 06 06:27:30 PM PDT 24
Finished Jul 06 06:27:32 PM PDT 24
Peak memory 218952 kb
Host smart-3f8eb214-ec21-4365-9684-5cd4a60b4fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645198509 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.2645198509
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.3578881020
Short name T755
Test name
Test status
Simulation time 94558981 ps
CPU time 1.41 seconds
Started Jul 06 06:27:37 PM PDT 24
Finished Jul 06 06:27:38 PM PDT 24
Peak memory 220484 kb
Host smart-3af8f4f0-b20b-42b8-9826-437c808e802e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578881020 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.3578881020
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.2836548303
Short name T110
Test name
Test status
Simulation time 22199172 ps
CPU time 1 seconds
Started Jul 06 06:27:32 PM PDT 24
Finished Jul 06 06:27:33 PM PDT 24
Peak memory 216108 kb
Host smart-70b4c822-1c97-4a78-a74b-8cc90be787be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836548303 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.2836548303
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.3533812224
Short name T848
Test name
Test status
Simulation time 27666465 ps
CPU time 0.89 seconds
Started Jul 06 06:27:44 PM PDT 24
Finished Jul 06 06:27:45 PM PDT 24
Peak memory 215564 kb
Host smart-546e9de2-fde3-4ae0-ad68-0eae088e725e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533812224 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.3533812224
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.2675616668
Short name T484
Test name
Test status
Simulation time 266370726 ps
CPU time 5.43 seconds
Started Jul 06 06:27:32 PM PDT 24
Finished Jul 06 06:27:38 PM PDT 24
Peak memory 220420 kb
Host smart-9ccbf869-a256-411a-8d00-ba927b80f267
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675616668 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.2675616668
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/240.edn_genbits.1244953957
Short name T332
Test name
Test status
Simulation time 70946471 ps
CPU time 1.1 seconds
Started Jul 06 06:29:27 PM PDT 24
Finished Jul 06 06:29:29 PM PDT 24
Peak memory 217488 kb
Host smart-20a46396-a54d-4482-a7e6-3396538f513c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244953957 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.1244953957
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.1798061106
Short name T501
Test name
Test status
Simulation time 90834954 ps
CPU time 1.63 seconds
Started Jul 06 06:29:11 PM PDT 24
Finished Jul 06 06:29:14 PM PDT 24
Peak memory 219212 kb
Host smart-60013bf0-ff83-4f78-85dc-6e91dab92b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798061106 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.1798061106
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.3823846676
Short name T87
Test name
Test status
Simulation time 57816900 ps
CPU time 1.3 seconds
Started Jul 06 06:29:12 PM PDT 24
Finished Jul 06 06:29:14 PM PDT 24
Peak memory 219164 kb
Host smart-bdff8a74-4cc8-4cde-9c5f-87361a2a4b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823846676 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.3823846676
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.1091340930
Short name T362
Test name
Test status
Simulation time 60297256 ps
CPU time 1.21 seconds
Started Jul 06 06:29:27 PM PDT 24
Finished Jul 06 06:29:29 PM PDT 24
Peak memory 217648 kb
Host smart-a9384201-8bd4-4128-b9e5-2b1caba1a1cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091340930 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.1091340930
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.2066225762
Short name T594
Test name
Test status
Simulation time 62120923 ps
CPU time 1.38 seconds
Started Jul 06 06:29:09 PM PDT 24
Finished Jul 06 06:29:11 PM PDT 24
Peak memory 219228 kb
Host smart-e1a910f0-e987-47b4-aefd-341bb631baa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066225762 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.2066225762
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.4263391039
Short name T789
Test name
Test status
Simulation time 72832852 ps
CPU time 1.43 seconds
Started Jul 06 06:29:11 PM PDT 24
Finished Jul 06 06:29:13 PM PDT 24
Peak memory 218752 kb
Host smart-d54e0d06-7bb9-466e-adef-c1bf2d5b7040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263391039 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.4263391039
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.1041241876
Short name T472
Test name
Test status
Simulation time 42777858 ps
CPU time 1.48 seconds
Started Jul 06 06:29:25 PM PDT 24
Finished Jul 06 06:29:27 PM PDT 24
Peak memory 218804 kb
Host smart-04802598-0101-4108-85ad-81673728dceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041241876 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.1041241876
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.1107703644
Short name T485
Test name
Test status
Simulation time 54371113 ps
CPU time 1.21 seconds
Started Jul 06 06:29:12 PM PDT 24
Finished Jul 06 06:29:14 PM PDT 24
Peak memory 217500 kb
Host smart-c60f8d6c-3e72-47cb-91f8-a18b61cc12da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107703644 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.1107703644
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.1557060716
Short name T826
Test name
Test status
Simulation time 112013079 ps
CPU time 1.47 seconds
Started Jul 06 06:29:17 PM PDT 24
Finished Jul 06 06:29:19 PM PDT 24
Peak memory 219480 kb
Host smart-5167d27b-8a46-4cdb-a5aa-009ebf1cfdc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557060716 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.1557060716
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.1685428183
Short name T434
Test name
Test status
Simulation time 27991433 ps
CPU time 1.29 seconds
Started Jul 06 06:29:22 PM PDT 24
Finished Jul 06 06:29:23 PM PDT 24
Peak memory 220348 kb
Host smart-724fed80-4776-4d39-bf87-01098ba9318c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685428183 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.1685428183
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.61475801
Short name T285
Test name
Test status
Simulation time 44832748 ps
CPU time 1.16 seconds
Started Jul 06 06:27:31 PM PDT 24
Finished Jul 06 06:27:33 PM PDT 24
Peak memory 220188 kb
Host smart-6b6649d1-a25c-4e26-b1d6-338961b7f295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61475801 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.61475801
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.446607921
Short name T423
Test name
Test status
Simulation time 13623973 ps
CPU time 0.9 seconds
Started Jul 06 06:27:33 PM PDT 24
Finished Jul 06 06:27:34 PM PDT 24
Peak memory 215252 kb
Host smart-54a03d13-c40b-4e9a-923d-26739c018d8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446607921 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.446607921
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.1386681903
Short name T941
Test name
Test status
Simulation time 13088734 ps
CPU time 0.97 seconds
Started Jul 06 06:27:36 PM PDT 24
Finished Jul 06 06:27:37 PM PDT 24
Peak memory 216888 kb
Host smart-99a4bb2e-3da9-4ad7-b245-51271c62fc60
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386681903 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.1386681903
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.3219905498
Short name T123
Test name
Test status
Simulation time 117596012 ps
CPU time 1.24 seconds
Started Jul 06 06:27:30 PM PDT 24
Finished Jul 06 06:27:31 PM PDT 24
Peak memory 217316 kb
Host smart-6dd3d5de-1614-44bb-aa1c-5dc70bbbba73
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219905498 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.3219905498
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.62677304
Short name T945
Test name
Test status
Simulation time 50037569 ps
CPU time 0.89 seconds
Started Jul 06 06:27:31 PM PDT 24
Finished Jul 06 06:27:32 PM PDT 24
Peak memory 218776 kb
Host smart-14cc46bc-77ae-4414-99a3-c1433692a768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62677304 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.62677304
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.992635048
Short name T739
Test name
Test status
Simulation time 105228050 ps
CPU time 2.05 seconds
Started Jul 06 06:27:35 PM PDT 24
Finished Jul 06 06:27:38 PM PDT 24
Peak memory 218976 kb
Host smart-aee092d7-8733-45f4-bac8-8516a404d647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992635048 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.992635048
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.672703918
Short name T63
Test name
Test status
Simulation time 47134261 ps
CPU time 0.98 seconds
Started Jul 06 06:27:28 PM PDT 24
Finished Jul 06 06:27:30 PM PDT 24
Peak memory 224144 kb
Host smart-6137bfc6-7e09-4ed5-8aab-49688759b9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672703918 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.672703918
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.1316980577
Short name T358
Test name
Test status
Simulation time 58232582 ps
CPU time 0.92 seconds
Started Jul 06 06:27:35 PM PDT 24
Finished Jul 06 06:27:37 PM PDT 24
Peak memory 215588 kb
Host smart-052a2766-a2ac-4d18-b043-ba9a9b9573bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316980577 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.1316980577
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.3650660724
Short name T569
Test name
Test status
Simulation time 1221345004 ps
CPU time 4.39 seconds
Started Jul 06 06:27:29 PM PDT 24
Finished Jul 06 06:27:34 PM PDT 24
Peak memory 217600 kb
Host smart-30a99f69-4c77-4e3b-8c0d-82608035d0c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650660724 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.3650660724
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.2493607550
Short name T230
Test name
Test status
Simulation time 23879584352 ps
CPU time 329.07 seconds
Started Jul 06 06:27:35 PM PDT 24
Finished Jul 06 06:33:04 PM PDT 24
Peak memory 224032 kb
Host smart-5395ec76-6086-4bee-8077-d07d3456fddb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493607550 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.2493607550
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.3231381898
Short name T845
Test name
Test status
Simulation time 53847696 ps
CPU time 1.17 seconds
Started Jul 06 06:29:13 PM PDT 24
Finished Jul 06 06:29:15 PM PDT 24
Peak memory 217600 kb
Host smart-8a943c44-ee73-4f67-a5fc-c1f36e1e9e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231381898 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.3231381898
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.233714469
Short name T533
Test name
Test status
Simulation time 33311660 ps
CPU time 1.4 seconds
Started Jul 06 06:29:14 PM PDT 24
Finished Jul 06 06:29:16 PM PDT 24
Peak memory 220324 kb
Host smart-73a9be64-03b3-4d16-8ede-482af2d3bd40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233714469 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.233714469
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.1663794558
Short name T620
Test name
Test status
Simulation time 35777347 ps
CPU time 1.33 seconds
Started Jul 06 06:29:12 PM PDT 24
Finished Jul 06 06:29:14 PM PDT 24
Peak memory 217648 kb
Host smart-3399dd18-88ba-46af-be89-e1c5691429e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663794558 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.1663794558
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.3939470550
Short name T322
Test name
Test status
Simulation time 46760036 ps
CPU time 1.77 seconds
Started Jul 06 06:29:29 PM PDT 24
Finished Jul 06 06:29:31 PM PDT 24
Peak memory 217828 kb
Host smart-2cf2fa28-e51f-47f3-b58d-bcbab94c6eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939470550 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.3939470550
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.2923822045
Short name T29
Test name
Test status
Simulation time 46368167 ps
CPU time 1.27 seconds
Started Jul 06 06:29:27 PM PDT 24
Finished Jul 06 06:29:29 PM PDT 24
Peak memory 217604 kb
Host smart-380b6678-7517-4fa8-bd41-27c001d586fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923822045 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.2923822045
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.3793044500
Short name T339
Test name
Test status
Simulation time 238175316 ps
CPU time 2.19 seconds
Started Jul 06 06:29:13 PM PDT 24
Finished Jul 06 06:29:16 PM PDT 24
Peak memory 218892 kb
Host smart-875627fc-ea0b-4f4e-a8df-5d5698fcf0e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793044500 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.3793044500
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.2726366497
Short name T772
Test name
Test status
Simulation time 34187880 ps
CPU time 1.61 seconds
Started Jul 06 06:29:22 PM PDT 24
Finished Jul 06 06:29:23 PM PDT 24
Peak memory 218796 kb
Host smart-2b73082a-f57b-4775-bbc9-9687aaadcf46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726366497 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.2726366497
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.3894572892
Short name T345
Test name
Test status
Simulation time 173184965 ps
CPU time 1.67 seconds
Started Jul 06 06:29:27 PM PDT 24
Finished Jul 06 06:29:30 PM PDT 24
Peak memory 217828 kb
Host smart-e373b1b8-902e-45b4-9690-54397e86d8bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894572892 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.3894572892
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.2130010603
Short name T381
Test name
Test status
Simulation time 42446953 ps
CPU time 1.69 seconds
Started Jul 06 06:29:13 PM PDT 24
Finished Jul 06 06:29:15 PM PDT 24
Peak memory 218828 kb
Host smart-9c1c9688-a83d-406c-acfe-bf8b61f3361b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130010603 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.2130010603
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.3611336444
Short name T521
Test name
Test status
Simulation time 106891507 ps
CPU time 1.62 seconds
Started Jul 06 06:29:14 PM PDT 24
Finished Jul 06 06:29:16 PM PDT 24
Peak memory 219520 kb
Host smart-1a67bf6c-df03-4354-93dd-b42cd92ede5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611336444 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.3611336444
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.2998265592
Short name T803
Test name
Test status
Simulation time 24867209 ps
CPU time 1.2 seconds
Started Jul 06 06:27:38 PM PDT 24
Finished Jul 06 06:27:39 PM PDT 24
Peak memory 220996 kb
Host smart-8f44665e-c31b-4a05-8434-88989ef2e592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998265592 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.2998265592
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.2378655048
Short name T612
Test name
Test status
Simulation time 42345902 ps
CPU time 0.81 seconds
Started Jul 06 06:27:33 PM PDT 24
Finished Jul 06 06:27:34 PM PDT 24
Peak memory 207144 kb
Host smart-385068d0-3b65-4d2c-b9be-c9c4afa291e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378655048 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.2378655048
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.2589469949
Short name T136
Test name
Test status
Simulation time 38311615 ps
CPU time 1.19 seconds
Started Jul 06 06:27:39 PM PDT 24
Finished Jul 06 06:27:41 PM PDT 24
Peak memory 220220 kb
Host smart-e7834552-00e5-4da5-a740-645200f31b56
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589469949 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.2589469949
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.1231920121
Short name T916
Test name
Test status
Simulation time 51238082 ps
CPU time 1.02 seconds
Started Jul 06 06:27:37 PM PDT 24
Finished Jul 06 06:27:38 PM PDT 24
Peak memory 220068 kb
Host smart-37102faa-f748-4f7c-ae1a-ce3b300fc5e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231920121 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.1231920121
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.1132192920
Short name T609
Test name
Test status
Simulation time 59927340 ps
CPU time 1.49 seconds
Started Jul 06 06:27:36 PM PDT 24
Finished Jul 06 06:27:38 PM PDT 24
Peak memory 218924 kb
Host smart-b30a3feb-88ea-4a90-a321-e148f1ea3806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132192920 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.1132192920
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.2050969318
Short name T880
Test name
Test status
Simulation time 25736698 ps
CPU time 0.88 seconds
Started Jul 06 06:27:34 PM PDT 24
Finished Jul 06 06:27:35 PM PDT 24
Peak memory 215968 kb
Host smart-fc75e4ab-eb37-45a4-86cb-f48747dd8e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050969318 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.2050969318
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.767959214
Short name T993
Test name
Test status
Simulation time 27705869 ps
CPU time 0.97 seconds
Started Jul 06 06:27:36 PM PDT 24
Finished Jul 06 06:27:38 PM PDT 24
Peak memory 215624 kb
Host smart-a945411e-e175-4a3f-809c-83fb5826490b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767959214 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.767959214
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.592761609
Short name T722
Test name
Test status
Simulation time 155106560 ps
CPU time 2.72 seconds
Started Jul 06 06:27:34 PM PDT 24
Finished Jul 06 06:27:37 PM PDT 24
Peak memory 217712 kb
Host smart-a13e54c8-e607-4d6e-97d0-58c5072583fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592761609 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.592761609
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.3949880172
Short name T516
Test name
Test status
Simulation time 83533761827 ps
CPU time 553.7 seconds
Started Jul 06 06:27:33 PM PDT 24
Finished Jul 06 06:36:47 PM PDT 24
Peak memory 220524 kb
Host smart-72044c4c-a2a6-4a5d-98a5-07287c458ac8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949880172 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.3949880172
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.2400553091
Short name T679
Test name
Test status
Simulation time 55049715 ps
CPU time 2.09 seconds
Started Jul 06 06:29:20 PM PDT 24
Finished Jul 06 06:29:23 PM PDT 24
Peak memory 220252 kb
Host smart-90650d2e-8248-4b53-b06f-9c272f6d9d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400553091 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.2400553091
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.2443154889
Short name T787
Test name
Test status
Simulation time 43198850 ps
CPU time 1.51 seconds
Started Jul 06 06:29:27 PM PDT 24
Finished Jul 06 06:29:30 PM PDT 24
Peak memory 218852 kb
Host smart-adb7e5f0-2dcd-452b-bc26-04afd0768a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443154889 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.2443154889
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.1990545950
Short name T855
Test name
Test status
Simulation time 56183732 ps
CPU time 1.1 seconds
Started Jul 06 06:29:30 PM PDT 24
Finished Jul 06 06:29:31 PM PDT 24
Peak memory 219144 kb
Host smart-ab40218f-9823-4223-b49c-33c19a5a27ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990545950 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.1990545950
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.2606031936
Short name T688
Test name
Test status
Simulation time 55223987 ps
CPU time 1.33 seconds
Started Jul 06 06:29:28 PM PDT 24
Finished Jul 06 06:29:30 PM PDT 24
Peak memory 220204 kb
Host smart-6c5a968e-816c-4377-9d0c-49848e15a92f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606031936 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.2606031936
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.1857163006
Short name T252
Test name
Test status
Simulation time 109195790 ps
CPU time 1.28 seconds
Started Jul 06 06:29:13 PM PDT 24
Finished Jul 06 06:29:15 PM PDT 24
Peak memory 220448 kb
Host smart-0ea276ca-3a2f-478c-b53b-12720deec09e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857163006 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.1857163006
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.2203873222
Short name T74
Test name
Test status
Simulation time 42755467 ps
CPU time 1.69 seconds
Started Jul 06 06:29:14 PM PDT 24
Finished Jul 06 06:29:16 PM PDT 24
Peak memory 218912 kb
Host smart-e77da356-9fe1-4dfb-9bc8-fcf8c2f01c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203873222 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.2203873222
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.2716048029
Short name T605
Test name
Test status
Simulation time 4403269267 ps
CPU time 89.91 seconds
Started Jul 06 06:29:24 PM PDT 24
Finished Jul 06 06:30:54 PM PDT 24
Peak memory 221080 kb
Host smart-f81023e1-7491-4ce9-b859-28de608df262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716048029 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.2716048029
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.2759169867
Short name T431
Test name
Test status
Simulation time 74290248 ps
CPU time 1.16 seconds
Started Jul 06 06:29:14 PM PDT 24
Finished Jul 06 06:29:16 PM PDT 24
Peak memory 217696 kb
Host smart-cb32b6b5-36b3-4e13-99a8-6a6839564205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759169867 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.2759169867
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.1397349482
Short name T414
Test name
Test status
Simulation time 44321412 ps
CPU time 1.1 seconds
Started Jul 06 06:29:11 PM PDT 24
Finished Jul 06 06:29:13 PM PDT 24
Peak memory 218772 kb
Host smart-248a0c8d-718c-40aa-b961-0894b5f1d391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397349482 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.1397349482
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.3256507948
Short name T963
Test name
Test status
Simulation time 41012945 ps
CPU time 1.08 seconds
Started Jul 06 06:29:13 PM PDT 24
Finished Jul 06 06:29:14 PM PDT 24
Peak memory 218732 kb
Host smart-1a991b30-d849-45da-b9c4-a05463a156a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256507948 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.3256507948
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.3283064606
Short name T53
Test name
Test status
Simulation time 49932634 ps
CPU time 1.19 seconds
Started Jul 06 06:27:37 PM PDT 24
Finished Jul 06 06:27:39 PM PDT 24
Peak memory 220728 kb
Host smart-9104f75c-ab2a-4d57-bac8-7ccc2736fc8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283064606 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.3283064606
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.1302400479
Short name T985
Test name
Test status
Simulation time 55997930 ps
CPU time 0.86 seconds
Started Jul 06 06:27:39 PM PDT 24
Finished Jul 06 06:27:40 PM PDT 24
Peak memory 207088 kb
Host smart-2fbe5bbc-4570-4e63-97b0-a8f9729c6275
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302400479 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.1302400479
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.260777578
Short name T58
Test name
Test status
Simulation time 16769277 ps
CPU time 0.91 seconds
Started Jul 06 06:27:38 PM PDT 24
Finished Jul 06 06:27:40 PM PDT 24
Peak memory 216560 kb
Host smart-3af17da1-3bb1-4b14-8bbb-e241648a85b6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260777578 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.260777578
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.1624874742
Short name T626
Test name
Test status
Simulation time 27794741 ps
CPU time 1.03 seconds
Started Jul 06 06:27:38 PM PDT 24
Finished Jul 06 06:27:39 PM PDT 24
Peak memory 217272 kb
Host smart-d8adf6e9-6188-4c9f-b4e6-254386e5715d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624874742 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.1624874742
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.3612304090
Short name T441
Test name
Test status
Simulation time 21087053 ps
CPU time 1.03 seconds
Started Jul 06 06:27:39 PM PDT 24
Finished Jul 06 06:27:41 PM PDT 24
Peak memory 224304 kb
Host smart-4be5053e-21aa-4718-bf99-98cfc8b27b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612304090 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.3612304090
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.60129124
Short name T573
Test name
Test status
Simulation time 161830977 ps
CPU time 0.96 seconds
Started Jul 06 06:27:48 PM PDT 24
Finished Jul 06 06:27:50 PM PDT 24
Peak memory 217732 kb
Host smart-3db7b3c0-47df-44c5-ae03-c259cd537e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60129124 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.60129124
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.1160165155
Short name T428
Test name
Test status
Simulation time 33811156 ps
CPU time 1.11 seconds
Started Jul 06 06:27:38 PM PDT 24
Finished Jul 06 06:27:40 PM PDT 24
Peak memory 224372 kb
Host smart-14dd6008-737d-4255-bfa8-764415125c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160165155 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.1160165155
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.2099922883
Short name T84
Test name
Test status
Simulation time 47211500 ps
CPU time 0.94 seconds
Started Jul 06 06:27:35 PM PDT 24
Finished Jul 06 06:27:36 PM PDT 24
Peak memory 215672 kb
Host smart-7a39a11c-e3ef-4824-ac84-7f6623c0a4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099922883 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.2099922883
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.523820598
Short name T105
Test name
Test status
Simulation time 195441676 ps
CPU time 1.72 seconds
Started Jul 06 06:27:36 PM PDT 24
Finished Jul 06 06:27:38 PM PDT 24
Peak memory 220220 kb
Host smart-0b4b08f9-6d62-4cc6-a10c-a6e48789ae6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523820598 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.523820598
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.867796741
Short name T540
Test name
Test status
Simulation time 21383465710 ps
CPU time 262.93 seconds
Started Jul 06 06:27:44 PM PDT 24
Finished Jul 06 06:32:07 PM PDT 24
Peak memory 218628 kb
Host smart-739933f2-47d9-40b3-a370-f4f4cf2e0410
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867796741 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.867796741
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.1073028545
Short name T711
Test name
Test status
Simulation time 64823106 ps
CPU time 1.28 seconds
Started Jul 06 06:29:17 PM PDT 24
Finished Jul 06 06:29:18 PM PDT 24
Peak memory 218856 kb
Host smart-29f90acf-1212-41e2-ad68-e222e57ae1fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073028545 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.1073028545
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.1149558033
Short name T457
Test name
Test status
Simulation time 10450193272 ps
CPU time 134.51 seconds
Started Jul 06 06:29:20 PM PDT 24
Finished Jul 06 06:31:35 PM PDT 24
Peak memory 218948 kb
Host smart-7b769f0c-5ca0-4e53-8809-5d274c898a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149558033 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.1149558033
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.2346346647
Short name T858
Test name
Test status
Simulation time 88508077 ps
CPU time 1.5 seconds
Started Jul 06 06:29:16 PM PDT 24
Finished Jul 06 06:29:17 PM PDT 24
Peak memory 219092 kb
Host smart-1a294612-cbc5-4fc2-b2a0-5be537924a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346346647 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.2346346647
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.1622389080
Short name T450
Test name
Test status
Simulation time 57863901 ps
CPU time 1.3 seconds
Started Jul 06 06:29:29 PM PDT 24
Finished Jul 06 06:29:30 PM PDT 24
Peak memory 218884 kb
Host smart-5402526f-9736-4809-beff-e6f901028671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622389080 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.1622389080
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.3933870847
Short name T983
Test name
Test status
Simulation time 405801221 ps
CPU time 4.47 seconds
Started Jul 06 06:29:30 PM PDT 24
Finished Jul 06 06:29:35 PM PDT 24
Peak memory 217816 kb
Host smart-96c41598-efed-4173-b49e-3952e6df8701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933870847 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.3933870847
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.698234774
Short name T93
Test name
Test status
Simulation time 37122969 ps
CPU time 1.11 seconds
Started Jul 06 06:29:22 PM PDT 24
Finished Jul 06 06:29:23 PM PDT 24
Peak memory 217748 kb
Host smart-68c9e731-fb43-4d3b-bc6f-c1f296220696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698234774 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.698234774
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.1606125385
Short name T479
Test name
Test status
Simulation time 80611008 ps
CPU time 1.28 seconds
Started Jul 06 06:29:20 PM PDT 24
Finished Jul 06 06:29:21 PM PDT 24
Peak memory 217640 kb
Host smart-71715c43-1fcd-4e94-96fd-4c57f738a088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606125385 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.1606125385
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.4243270319
Short name T59
Test name
Test status
Simulation time 225138552 ps
CPU time 1.29 seconds
Started Jul 06 06:29:21 PM PDT 24
Finished Jul 06 06:29:22 PM PDT 24
Peak memory 217752 kb
Host smart-13c97cbb-a420-4534-9f75-40e33af6b1a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243270319 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.4243270319
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.1876683870
Short name T337
Test name
Test status
Simulation time 42753527 ps
CPU time 1.79 seconds
Started Jul 06 06:29:25 PM PDT 24
Finished Jul 06 06:29:28 PM PDT 24
Peak memory 218748 kb
Host smart-00944d7d-92a6-47df-9b82-7e7246104269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876683870 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.1876683870
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.2582097508
Short name T897
Test name
Test status
Simulation time 96860025 ps
CPU time 1.48 seconds
Started Jul 06 06:29:29 PM PDT 24
Finished Jul 06 06:29:31 PM PDT 24
Peak memory 219072 kb
Host smart-41b5659e-fd6b-4733-a38d-ed112a62ca54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582097508 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.2582097508
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.2756775585
Short name T741
Test name
Test status
Simulation time 27089898 ps
CPU time 1.24 seconds
Started Jul 06 06:27:42 PM PDT 24
Finished Jul 06 06:27:44 PM PDT 24
Peak memory 220120 kb
Host smart-e75492d6-b134-4e71-bf9b-4ab802a2649f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756775585 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.2756775585
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.542565172
Short name T752
Test name
Test status
Simulation time 68454147 ps
CPU time 1.69 seconds
Started Jul 06 06:27:38 PM PDT 24
Finished Jul 06 06:27:40 PM PDT 24
Peak memory 207204 kb
Host smart-9ca4701c-8a22-444f-8871-f533b2dd5ec2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542565172 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.542565172
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.2818500722
Short name T639
Test name
Test status
Simulation time 35937097 ps
CPU time 0.88 seconds
Started Jul 06 06:27:42 PM PDT 24
Finished Jul 06 06:27:44 PM PDT 24
Peak memory 216316 kb
Host smart-573aa70a-5b6a-457e-8e46-e45220233b47
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818500722 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.2818500722
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.2679186735
Short name T155
Test name
Test status
Simulation time 28860222 ps
CPU time 1.18 seconds
Started Jul 06 06:27:38 PM PDT 24
Finished Jul 06 06:27:40 PM PDT 24
Peak memory 217296 kb
Host smart-ad37b53e-4deb-4950-8d6a-93c445f1e942
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679186735 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.2679186735
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.2349276556
Short name T141
Test name
Test status
Simulation time 32640588 ps
CPU time 1.04 seconds
Started Jul 06 06:27:40 PM PDT 24
Finished Jul 06 06:27:42 PM PDT 24
Peak memory 218892 kb
Host smart-272ba20c-e010-4159-8572-46d526b1abac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349276556 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.2349276556
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.3869763077
Short name T475
Test name
Test status
Simulation time 90877938 ps
CPU time 1.21 seconds
Started Jul 06 06:27:45 PM PDT 24
Finished Jul 06 06:27:47 PM PDT 24
Peak memory 220400 kb
Host smart-4bcfaf54-0b0c-4f8e-b70d-01ac324cd93a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869763077 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.3869763077
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.4042252223
Short name T372
Test name
Test status
Simulation time 24896098 ps
CPU time 1.09 seconds
Started Jul 06 06:27:37 PM PDT 24
Finished Jul 06 06:27:38 PM PDT 24
Peak memory 215984 kb
Host smart-a467cc80-0361-4506-a18a-52470dfd8dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042252223 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.4042252223
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.1423251799
Short name T70
Test name
Test status
Simulation time 20306383 ps
CPU time 1.02 seconds
Started Jul 06 06:27:45 PM PDT 24
Finished Jul 06 06:27:46 PM PDT 24
Peak memory 215684 kb
Host smart-988c4d63-aeb1-4502-aae4-338e47e50c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423251799 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.1423251799
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.4187989750
Short name T606
Test name
Test status
Simulation time 176853095 ps
CPU time 3.82 seconds
Started Jul 06 06:27:39 PM PDT 24
Finished Jul 06 06:27:43 PM PDT 24
Peak memory 218840 kb
Host smart-164051b4-0fbd-4871-b6cc-000e7641bf22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187989750 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.4187989750
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.3482533909
Short name T547
Test name
Test status
Simulation time 130435937146 ps
CPU time 1487.58 seconds
Started Jul 06 06:27:44 PM PDT 24
Finished Jul 06 06:52:32 PM PDT 24
Peak memory 224228 kb
Host smart-db7e5d0b-6dca-4c0c-bf0c-e89a0e1e56a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482533909 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.3482533909
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.3865631071
Short name T923
Test name
Test status
Simulation time 48530567 ps
CPU time 1.56 seconds
Started Jul 06 06:29:31 PM PDT 24
Finished Jul 06 06:29:33 PM PDT 24
Peak memory 219012 kb
Host smart-800b988d-c5d9-4e5d-9b16-9ce60c0f15c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865631071 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.3865631071
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.3231353320
Short name T653
Test name
Test status
Simulation time 57172656 ps
CPU time 1.3 seconds
Started Jul 06 06:29:21 PM PDT 24
Finished Jul 06 06:29:23 PM PDT 24
Peak memory 217712 kb
Host smart-116e2d4d-654d-42d0-bc91-ca7fdaec42c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231353320 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.3231353320
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.3081916241
Short name T451
Test name
Test status
Simulation time 82651852 ps
CPU time 1.1 seconds
Started Jul 06 06:29:33 PM PDT 24
Finished Jul 06 06:29:34 PM PDT 24
Peak memory 217684 kb
Host smart-4d03ca67-fa6f-4f6e-992c-fb794cbf864d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081916241 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.3081916241
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.2490266651
Short name T460
Test name
Test status
Simulation time 293112181 ps
CPU time 1.28 seconds
Started Jul 06 06:29:27 PM PDT 24
Finished Jul 06 06:29:29 PM PDT 24
Peak memory 217832 kb
Host smart-44c48666-68c3-4dcf-a2e6-b4f26369b76d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490266651 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.2490266651
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.3686889270
Short name T894
Test name
Test status
Simulation time 59781609 ps
CPU time 1.44 seconds
Started Jul 06 06:29:22 PM PDT 24
Finished Jul 06 06:29:24 PM PDT 24
Peak memory 218988 kb
Host smart-7e3d270f-0aa9-47a6-abc3-7ba6791704ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686889270 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.3686889270
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.473577387
Short name T341
Test name
Test status
Simulation time 62856030 ps
CPU time 2.23 seconds
Started Jul 06 06:29:21 PM PDT 24
Finished Jul 06 06:29:23 PM PDT 24
Peak memory 220332 kb
Host smart-582cfd40-4393-4a2e-b70a-f61467352dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473577387 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.473577387
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.2197562330
Short name T411
Test name
Test status
Simulation time 259488756 ps
CPU time 1.48 seconds
Started Jul 06 06:29:21 PM PDT 24
Finished Jul 06 06:29:23 PM PDT 24
Peak memory 220336 kb
Host smart-abdde63a-9cbf-421c-89e8-f929bc022035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197562330 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.2197562330
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.3287336847
Short name T456
Test name
Test status
Simulation time 56711475 ps
CPU time 1.57 seconds
Started Jul 06 06:29:32 PM PDT 24
Finished Jul 06 06:29:34 PM PDT 24
Peak memory 218896 kb
Host smart-b33a7289-8f3f-4dc6-b0de-f5944a90c590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287336847 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.3287336847
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.2827910049
Short name T823
Test name
Test status
Simulation time 70348421 ps
CPU time 1.57 seconds
Started Jul 06 06:29:21 PM PDT 24
Finished Jul 06 06:29:23 PM PDT 24
Peak memory 219024 kb
Host smart-62317df6-ec60-4bcf-8afd-b3aa303903af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827910049 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.2827910049
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.959033283
Short name T356
Test name
Test status
Simulation time 220961688 ps
CPU time 2.42 seconds
Started Jul 06 06:29:27 PM PDT 24
Finished Jul 06 06:29:31 PM PDT 24
Peak memory 217984 kb
Host smart-28aa7183-55c1-4cc5-91fd-2a4ae156c433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959033283 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.959033283
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.2731215628
Short name T585
Test name
Test status
Simulation time 75260360 ps
CPU time 1.18 seconds
Started Jul 06 06:27:40 PM PDT 24
Finished Jul 06 06:27:42 PM PDT 24
Peak memory 221228 kb
Host smart-3f7a5020-8d77-41b2-b43b-6b8078895443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731215628 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.2731215628
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.3188436857
Short name T367
Test name
Test status
Simulation time 19550867 ps
CPU time 1 seconds
Started Jul 06 06:27:37 PM PDT 24
Finished Jul 06 06:27:38 PM PDT 24
Peak memory 215456 kb
Host smart-d02a68a8-b94f-4f1b-b016-84700c190749
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188436857 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.3188436857
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.1621861768
Short name T685
Test name
Test status
Simulation time 13397170 ps
CPU time 0.92 seconds
Started Jul 06 06:27:37 PM PDT 24
Finished Jul 06 06:27:38 PM PDT 24
Peak memory 216860 kb
Host smart-734a77c5-babd-4927-9167-6c78dad50f50
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621861768 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.1621861768
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.590517728
Short name T197
Test name
Test status
Simulation time 32348220 ps
CPU time 1.2 seconds
Started Jul 06 06:27:39 PM PDT 24
Finished Jul 06 06:27:41 PM PDT 24
Peak memory 217268 kb
Host smart-b835e24e-d2fd-4ac8-b5a8-5fb026ac9e13
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590517728 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_di
sable_auto_req_mode.590517728
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.3850232983
Short name T159
Test name
Test status
Simulation time 22168850 ps
CPU time 1.23 seconds
Started Jul 06 06:27:40 PM PDT 24
Finished Jul 06 06:27:42 PM PDT 24
Peak memory 224268 kb
Host smart-108a9c8e-ddba-4a96-97f3-5c9f0b9bf789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850232983 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.3850232983
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.568303643
Short name T357
Test name
Test status
Simulation time 647424163 ps
CPU time 5.53 seconds
Started Jul 06 06:27:44 PM PDT 24
Finished Jul 06 06:27:50 PM PDT 24
Peak memory 220656 kb
Host smart-2726981f-cd85-4843-ac73-5c1818aee907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568303643 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.568303643
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.1989044583
Short name T528
Test name
Test status
Simulation time 30652263 ps
CPU time 0.87 seconds
Started Jul 06 06:27:42 PM PDT 24
Finished Jul 06 06:27:43 PM PDT 24
Peak memory 216016 kb
Host smart-9d7ca765-7c3e-4b0d-926d-b197bd69ee2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989044583 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.1989044583
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.607169141
Short name T980
Test name
Test status
Simulation time 15207233 ps
CPU time 0.95 seconds
Started Jul 06 06:27:38 PM PDT 24
Finished Jul 06 06:27:39 PM PDT 24
Peak memory 215624 kb
Host smart-4520abd9-9984-4a13-8f02-816113b15bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607169141 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.607169141
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.437260943
Short name T515
Test name
Test status
Simulation time 447114690 ps
CPU time 5.09 seconds
Started Jul 06 06:27:48 PM PDT 24
Finished Jul 06 06:27:54 PM PDT 24
Peak memory 215728 kb
Host smart-99e36cc3-e046-4f47-b718-c79af3d06ddd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437260943 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.437260943
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.757177620
Short name T236
Test name
Test status
Simulation time 141757058182 ps
CPU time 1552.73 seconds
Started Jul 06 06:27:38 PM PDT 24
Finished Jul 06 06:53:32 PM PDT 24
Peak memory 225152 kb
Host smart-79fa6324-c054-4ac0-a71b-c66b9f35c17a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757177620 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.757177620
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.1380019211
Short name T436
Test name
Test status
Simulation time 38176396 ps
CPU time 1.45 seconds
Started Jul 06 06:29:21 PM PDT 24
Finished Jul 06 06:29:23 PM PDT 24
Peak memory 218852 kb
Host smart-2b64d6d7-7c27-4251-9a65-7ce13014506e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380019211 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.1380019211
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.584322846
Short name T330
Test name
Test status
Simulation time 77236981 ps
CPU time 2.01 seconds
Started Jul 06 06:29:23 PM PDT 24
Finished Jul 06 06:29:26 PM PDT 24
Peak memory 219596 kb
Host smart-eb0eb703-d4ab-40c2-b11d-13f4f1a3b0a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584322846 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.584322846
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.390735099
Short name T492
Test name
Test status
Simulation time 85005197 ps
CPU time 1.14 seconds
Started Jul 06 06:29:28 PM PDT 24
Finished Jul 06 06:29:30 PM PDT 24
Peak memory 220144 kb
Host smart-4c79c2fe-a6e1-4f1f-9010-1f45273f0923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390735099 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.390735099
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.264600832
Short name T476
Test name
Test status
Simulation time 385379056 ps
CPU time 3.21 seconds
Started Jul 06 06:29:32 PM PDT 24
Finished Jul 06 06:29:36 PM PDT 24
Peak memory 217852 kb
Host smart-9c1da60d-e554-43ef-8554-4201e3df978d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264600832 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.264600832
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.788688853
Short name T342
Test name
Test status
Simulation time 90854675 ps
CPU time 1.19 seconds
Started Jul 06 06:29:27 PM PDT 24
Finished Jul 06 06:29:28 PM PDT 24
Peak memory 219244 kb
Host smart-ed4eb629-29ef-4e3a-b065-e1a75dc5ee25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788688853 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.788688853
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.920484877
Short name T364
Test name
Test status
Simulation time 43215393 ps
CPU time 1.36 seconds
Started Jul 06 06:29:31 PM PDT 24
Finished Jul 06 06:29:32 PM PDT 24
Peak memory 218688 kb
Host smart-0fa054c7-621b-48e6-a866-23b701ae8915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920484877 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.920484877
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.2508408213
Short name T698
Test name
Test status
Simulation time 459293567 ps
CPU time 1.67 seconds
Started Jul 06 06:29:31 PM PDT 24
Finished Jul 06 06:29:33 PM PDT 24
Peak memory 218888 kb
Host smart-429159f5-47b9-4b89-87e5-71862acdad1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508408213 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.2508408213
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.1359751443
Short name T409
Test name
Test status
Simulation time 34758279 ps
CPU time 1.26 seconds
Started Jul 06 06:29:30 PM PDT 24
Finished Jul 06 06:29:32 PM PDT 24
Peak memory 218856 kb
Host smart-adba91b6-fa02-44b7-a683-c3458048a9a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359751443 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.1359751443
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.1759225978
Short name T371
Test name
Test status
Simulation time 34799366 ps
CPU time 1.14 seconds
Started Jul 06 06:29:22 PM PDT 24
Finished Jul 06 06:29:24 PM PDT 24
Peak memory 220224 kb
Host smart-d662b6be-5a88-4686-a2ad-43b4de04e553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759225978 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.1759225978
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.48405045
Short name T415
Test name
Test status
Simulation time 54461425 ps
CPU time 1.36 seconds
Started Jul 06 06:29:23 PM PDT 24
Finished Jul 06 06:29:25 PM PDT 24
Peak memory 217536 kb
Host smart-2fef501c-d39b-4b30-a6eb-72d891f524ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48405045 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.48405045
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.2798040195
Short name T695
Test name
Test status
Simulation time 28000666 ps
CPU time 1.25 seconds
Started Jul 06 06:26:57 PM PDT 24
Finished Jul 06 06:26:59 PM PDT 24
Peak memory 220052 kb
Host smart-709d2eef-9908-4de6-a031-b4db56f91a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798040195 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.2798040195
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.238943632
Short name T672
Test name
Test status
Simulation time 171903070 ps
CPU time 0.97 seconds
Started Jul 06 06:26:54 PM PDT 24
Finished Jul 06 06:26:55 PM PDT 24
Peak memory 215500 kb
Host smart-0fb7a936-c032-46cb-8049-2db0367222fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238943632 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.238943632
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.1123336039
Short name T791
Test name
Test status
Simulation time 35772740 ps
CPU time 0.85 seconds
Started Jul 06 06:26:56 PM PDT 24
Finished Jul 06 06:26:57 PM PDT 24
Peak memory 216620 kb
Host smart-8b03f5cc-5954-4173-b388-c767812bf7bd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123336039 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.1123336039
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.65836695
Short name T366
Test name
Test status
Simulation time 58364499 ps
CPU time 1.13 seconds
Started Jul 06 06:26:54 PM PDT 24
Finished Jul 06 06:26:55 PM PDT 24
Peak memory 218752 kb
Host smart-43507777-93c2-41f8-af3c-abed3cd21ff6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65836695 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disa
ble_auto_req_mode.65836695
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.2516168540
Short name T127
Test name
Test status
Simulation time 36310266 ps
CPU time 1.08 seconds
Started Jul 06 06:26:56 PM PDT 24
Finished Jul 06 06:26:57 PM PDT 24
Peak memory 217712 kb
Host smart-8f7e7425-35f0-49e1-b5e8-f5189adaa1b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516168540 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.2516168540
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.661432411
Short name T539
Test name
Test status
Simulation time 90031153 ps
CPU time 1.13 seconds
Started Jul 06 06:26:57 PM PDT 24
Finished Jul 06 06:26:59 PM PDT 24
Peak memory 219824 kb
Host smart-3ecf2368-63bf-4174-9ac0-1925af01e7b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661432411 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.661432411
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.853848442
Short name T536
Test name
Test status
Simulation time 28764541 ps
CPU time 0.99 seconds
Started Jul 06 06:26:56 PM PDT 24
Finished Jul 06 06:26:57 PM PDT 24
Peak memory 216208 kb
Host smart-8758bb64-2ca5-422b-aaa1-91f1cfb394f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853848442 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.853848442
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.3645174643
Short name T31
Test name
Test status
Simulation time 97973897 ps
CPU time 0.99 seconds
Started Jul 06 06:26:58 PM PDT 24
Finished Jul 06 06:26:59 PM PDT 24
Peak memory 207448 kb
Host smart-5e0a3d80-b674-4c2e-ac39-c32364a932b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645174643 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.3645174643
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_smoke.3889946685
Short name T377
Test name
Test status
Simulation time 141201078 ps
CPU time 0.95 seconds
Started Jul 06 06:26:55 PM PDT 24
Finished Jul 06 06:26:56 PM PDT 24
Peak memory 215652 kb
Host smart-6d8e669f-32e5-45e7-a0aa-6de8136dee6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889946685 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.3889946685
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.2006888770
Short name T113
Test name
Test status
Simulation time 927910834 ps
CPU time 5.04 seconds
Started Jul 06 06:26:56 PM PDT 24
Finished Jul 06 06:27:02 PM PDT 24
Peak memory 217648 kb
Host smart-26dd30a5-7747-4e88-a485-a0a60b4a123f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006888770 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.2006888770
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.2647604890
Short name T228
Test name
Test status
Simulation time 35397100680 ps
CPU time 921.01 seconds
Started Jul 06 06:26:54 PM PDT 24
Finished Jul 06 06:42:15 PM PDT 24
Peak memory 219352 kb
Host smart-a8d147c0-059d-43c4-b240-7ae551de28d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647604890 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.2647604890
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert_test.339594028
Short name T529
Test name
Test status
Simulation time 49498625 ps
CPU time 0.9 seconds
Started Jul 06 06:27:48 PM PDT 24
Finished Jul 06 06:27:50 PM PDT 24
Peak memory 215164 kb
Host smart-f5c57016-20ae-4435-b3e9-d58ed460cfde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339594028 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.339594028
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.2353523116
Short name T526
Test name
Test status
Simulation time 13296764 ps
CPU time 0.94 seconds
Started Jul 06 06:27:42 PM PDT 24
Finished Jul 06 06:27:43 PM PDT 24
Peak memory 215940 kb
Host smart-48587250-fdfe-49cb-8290-61b39fcab720
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353523116 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.2353523116
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.3748640702
Short name T129
Test name
Test status
Simulation time 30160702 ps
CPU time 1.09 seconds
Started Jul 06 06:27:42 PM PDT 24
Finished Jul 06 06:27:43 PM PDT 24
Peak memory 217096 kb
Host smart-a2869ff3-cf9d-4877-890a-a39af4910a6d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748640702 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.3748640702
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.794538343
Short name T77
Test name
Test status
Simulation time 33465626 ps
CPU time 0.91 seconds
Started Jul 06 06:27:42 PM PDT 24
Finished Jul 06 06:27:43 PM PDT 24
Peak memory 218520 kb
Host smart-1dbcb88b-d4d4-4279-a54b-b9ebc577a4e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794538343 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.794538343
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.1387803120
Short name T596
Test name
Test status
Simulation time 56851020 ps
CPU time 1.14 seconds
Started Jul 06 06:27:38 PM PDT 24
Finished Jul 06 06:27:39 PM PDT 24
Peak memory 217800 kb
Host smart-67c80558-67a9-4e39-955f-5c2793643f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387803120 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.1387803120
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.2284930868
Short name T88
Test name
Test status
Simulation time 32478360 ps
CPU time 0.92 seconds
Started Jul 06 06:27:53 PM PDT 24
Finished Jul 06 06:27:55 PM PDT 24
Peak memory 215764 kb
Host smart-f3a5e629-b1d5-4392-845b-b9e7298dcfa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284930868 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.2284930868
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.3122661210
Short name T649
Test name
Test status
Simulation time 54625599 ps
CPU time 1.02 seconds
Started Jul 06 06:27:40 PM PDT 24
Finished Jul 06 06:27:42 PM PDT 24
Peak memory 215596 kb
Host smart-938ba8a2-240c-4e2e-a684-3fbc5bc69b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122661210 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.3122661210
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.1499706135
Short name T255
Test name
Test status
Simulation time 332801344 ps
CPU time 2.04 seconds
Started Jul 06 06:27:42 PM PDT 24
Finished Jul 06 06:27:45 PM PDT 24
Peak memory 215676 kb
Host smart-cbceb31b-b282-450e-9eb3-ea4220330469
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499706135 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.1499706135
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.2961042306
Short name T989
Test name
Test status
Simulation time 23672855765 ps
CPU time 604.45 seconds
Started Jul 06 06:27:39 PM PDT 24
Finished Jul 06 06:37:44 PM PDT 24
Peak memory 224072 kb
Host smart-14dfec3a-0398-4d09-b56b-b9d8b87d9c2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961042306 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.2961042306
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.829811367
Short name T907
Test name
Test status
Simulation time 29945917 ps
CPU time 1.29 seconds
Started Jul 06 06:27:45 PM PDT 24
Finished Jul 06 06:27:46 PM PDT 24
Peak memory 219900 kb
Host smart-d5628844-9659-40ad-8298-0c4cf4fc1c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829811367 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.829811367
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.2040225713
Short name T936
Test name
Test status
Simulation time 34643495 ps
CPU time 0.84 seconds
Started Jul 06 06:27:43 PM PDT 24
Finished Jul 06 06:27:44 PM PDT 24
Peak memory 206996 kb
Host smart-ec732df5-0d92-4523-affd-614a48a6bf23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040225713 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.2040225713
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.3825974888
Short name T227
Test name
Test status
Simulation time 31920056 ps
CPU time 0.84 seconds
Started Jul 06 06:27:52 PM PDT 24
Finished Jul 06 06:27:53 PM PDT 24
Peak memory 216552 kb
Host smart-647bbef1-9672-43af-8c29-c6e8a67bea96
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825974888 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.3825974888
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.2778862944
Short name T702
Test name
Test status
Simulation time 75443716 ps
CPU time 1.1 seconds
Started Jul 06 06:27:48 PM PDT 24
Finished Jul 06 06:27:50 PM PDT 24
Peak memory 217288 kb
Host smart-55fb19e6-086e-4ada-b25f-8b82378ffb1f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778862944 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.2778862944
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.278299563
Short name T1
Test name
Test status
Simulation time 19955776 ps
CPU time 1.06 seconds
Started Jul 06 06:27:42 PM PDT 24
Finished Jul 06 06:27:43 PM PDT 24
Peak memory 218960 kb
Host smart-d4efbea0-c6aa-463d-975b-caed61500110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278299563 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.278299563
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.3266557018
Short name T797
Test name
Test status
Simulation time 51017156 ps
CPU time 1.19 seconds
Started Jul 06 06:27:45 PM PDT 24
Finished Jul 06 06:27:46 PM PDT 24
Peak memory 219108 kb
Host smart-392869d1-bf0e-4da8-835d-dea120dfa7d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266557018 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.3266557018
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.3701031749
Short name T834
Test name
Test status
Simulation time 25853247 ps
CPU time 1.08 seconds
Started Jul 06 06:27:51 PM PDT 24
Finished Jul 06 06:27:53 PM PDT 24
Peak memory 224392 kb
Host smart-2f63dee3-2d82-463e-b275-5374a0621d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701031749 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.3701031749
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.2088120776
Short name T510
Test name
Test status
Simulation time 23297937 ps
CPU time 1.03 seconds
Started Jul 06 06:27:42 PM PDT 24
Finished Jul 06 06:27:43 PM PDT 24
Peak memory 215660 kb
Host smart-716039dc-da4b-45eb-bc04-7cfa89b69919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088120776 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.2088120776
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.2754506618
Short name T630
Test name
Test status
Simulation time 111903237 ps
CPU time 1.24 seconds
Started Jul 06 06:27:48 PM PDT 24
Finished Jul 06 06:27:49 PM PDT 24
Peak memory 217636 kb
Host smart-2cdfc1da-9ad5-4cec-a504-53a6f3777ba1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754506618 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.2754506618
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.1297588969
Short name T525
Test name
Test status
Simulation time 200657059448 ps
CPU time 1276.93 seconds
Started Jul 06 06:27:47 PM PDT 24
Finished Jul 06 06:49:04 PM PDT 24
Peak memory 225712 kb
Host smart-227541af-0cd5-4e5f-a3c2-010a660e575b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297588969 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.1297588969
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.1285559904
Short name T603
Test name
Test status
Simulation time 32152582 ps
CPU time 1.1 seconds
Started Jul 06 06:27:40 PM PDT 24
Finished Jul 06 06:27:42 PM PDT 24
Peak memory 219156 kb
Host smart-38095852-b703-4898-bc95-6c0c66c34eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285559904 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.1285559904
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.1249637442
Short name T508
Test name
Test status
Simulation time 48312793 ps
CPU time 0.87 seconds
Started Jul 06 06:27:45 PM PDT 24
Finished Jul 06 06:27:47 PM PDT 24
Peak memory 215524 kb
Host smart-1ab7ef9f-5bd3-4a10-a0a9-286f9bc84238
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249637442 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.1249637442
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.2377329525
Short name T625
Test name
Test status
Simulation time 85592425 ps
CPU time 0.88 seconds
Started Jul 06 06:27:47 PM PDT 24
Finished Jul 06 06:27:48 PM PDT 24
Peak memory 216656 kb
Host smart-b864461c-6c61-4807-8379-b75749435737
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377329525 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.2377329525
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.3560704620
Short name T836
Test name
Test status
Simulation time 153454690 ps
CPU time 1.35 seconds
Started Jul 06 06:27:52 PM PDT 24
Finished Jul 06 06:27:53 PM PDT 24
Peak memory 217336 kb
Host smart-dad94d76-c585-4392-898e-3d8b0d13ad85
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560704620 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.3560704620
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.1667038819
Short name T513
Test name
Test status
Simulation time 21373717 ps
CPU time 0.98 seconds
Started Jul 06 06:27:44 PM PDT 24
Finished Jul 06 06:27:45 PM PDT 24
Peak memory 219148 kb
Host smart-b0ada73f-c55e-447b-91a1-3e96d138c5e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667038819 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.1667038819
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.3349844944
Short name T783
Test name
Test status
Simulation time 46912088 ps
CPU time 1.41 seconds
Started Jul 06 06:27:51 PM PDT 24
Finished Jul 06 06:27:53 PM PDT 24
Peak memory 218872 kb
Host smart-d1a80aa9-51b1-44f9-a783-b311ba75c389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349844944 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.3349844944
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.3655273962
Short name T111
Test name
Test status
Simulation time 33463032 ps
CPU time 0.85 seconds
Started Jul 06 06:27:53 PM PDT 24
Finished Jul 06 06:27:55 PM PDT 24
Peak memory 216016 kb
Host smart-9d836e19-db8d-4af6-a62b-7d0936ba4ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655273962 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.3655273962
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.2828480421
Short name T882
Test name
Test status
Simulation time 24559931 ps
CPU time 0.91 seconds
Started Jul 06 06:27:48 PM PDT 24
Finished Jul 06 06:27:49 PM PDT 24
Peak memory 215564 kb
Host smart-3624e556-80cf-4f24-97f8-9185f1b56220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828480421 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.2828480421
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.1270286927
Short name T804
Test name
Test status
Simulation time 254812862 ps
CPU time 4.98 seconds
Started Jul 06 06:27:49 PM PDT 24
Finished Jul 06 06:27:55 PM PDT 24
Peak memory 219016 kb
Host smart-7fc45ea4-5847-4a90-8f02-aee645b0f05d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270286927 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.1270286927
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.2472035913
Short name T241
Test name
Test status
Simulation time 48107544530 ps
CPU time 523.64 seconds
Started Jul 06 06:27:48 PM PDT 24
Finished Jul 06 06:36:32 PM PDT 24
Peak memory 218580 kb
Host smart-1296acd1-bdf2-4787-8d57-ea3681bbac09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472035913 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.2472035913
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.406375483
Short name T143
Test name
Test status
Simulation time 25642360 ps
CPU time 1.23 seconds
Started Jul 06 06:27:53 PM PDT 24
Finished Jul 06 06:27:55 PM PDT 24
Peak memory 218824 kb
Host smart-4bda3a89-c511-42c3-bdf1-b6c3543f111b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406375483 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.406375483
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.2358615720
Short name T641
Test name
Test status
Simulation time 29167226 ps
CPU time 0.86 seconds
Started Jul 06 06:27:51 PM PDT 24
Finished Jul 06 06:27:53 PM PDT 24
Peak memory 215356 kb
Host smart-b511858b-64c4-438f-8db0-6c32edf0f51c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358615720 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.2358615720
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.1932923322
Short name T965
Test name
Test status
Simulation time 29679739 ps
CPU time 0.83 seconds
Started Jul 06 06:27:46 PM PDT 24
Finished Jul 06 06:27:47 PM PDT 24
Peak memory 215736 kb
Host smart-857ad3ab-e7d3-41c1-b990-4fb840d29139
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932923322 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.1932923322
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.3884136035
Short name T149
Test name
Test status
Simulation time 73923941 ps
CPU time 1 seconds
Started Jul 06 06:27:49 PM PDT 24
Finished Jul 06 06:27:51 PM PDT 24
Peak memory 217308 kb
Host smart-870f4ded-9079-44de-a5fc-137959881824
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884136035 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.3884136035
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.411795907
Short name T494
Test name
Test status
Simulation time 22344614 ps
CPU time 0.9 seconds
Started Jul 06 06:27:55 PM PDT 24
Finished Jul 06 06:27:57 PM PDT 24
Peak memory 218772 kb
Host smart-5a15d719-254d-47a0-b655-bcfde4ed8634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411795907 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.411795907
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.2397455577
Short name T325
Test name
Test status
Simulation time 82583500 ps
CPU time 1.17 seconds
Started Jul 06 06:27:48 PM PDT 24
Finished Jul 06 06:27:50 PM PDT 24
Peak memory 217652 kb
Host smart-7bf5959f-58d1-4f8a-8193-758b4320a3e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397455577 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.2397455577
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.3165279852
Short name T769
Test name
Test status
Simulation time 38059274 ps
CPU time 1 seconds
Started Jul 06 06:27:48 PM PDT 24
Finished Jul 06 06:27:49 PM PDT 24
Peak memory 224312 kb
Host smart-365835a7-72b9-4814-81ac-981c7851b3f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165279852 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.3165279852
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.3209070761
Short name T495
Test name
Test status
Simulation time 18382440 ps
CPU time 1 seconds
Started Jul 06 06:27:45 PM PDT 24
Finished Jul 06 06:27:46 PM PDT 24
Peak memory 215628 kb
Host smart-13911c33-466a-4695-ad7a-682c50dc47ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209070761 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.3209070761
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.1152295715
Short name T376
Test name
Test status
Simulation time 95909469 ps
CPU time 2.43 seconds
Started Jul 06 06:27:53 PM PDT 24
Finished Jul 06 06:27:56 PM PDT 24
Peak memory 207432 kb
Host smart-1c51c6fd-6542-4d12-8fed-d32494de7dd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152295715 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.1152295715
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.1188028868
Short name T917
Test name
Test status
Simulation time 88835789350 ps
CPU time 1264.9 seconds
Started Jul 06 06:27:54 PM PDT 24
Finished Jul 06 06:49:00 PM PDT 24
Peak memory 223040 kb
Host smart-f1550730-2301-4733-a8da-5e0e12cb29bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188028868 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.1188028868
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.2949238753
Short name T142
Test name
Test status
Simulation time 72590681 ps
CPU time 1.2 seconds
Started Jul 06 06:27:49 PM PDT 24
Finished Jul 06 06:27:50 PM PDT 24
Peak memory 219832 kb
Host smart-10c6c797-f31f-4391-8c77-2de91bae1685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949238753 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.2949238753
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.2449465500
Short name T405
Test name
Test status
Simulation time 40708849 ps
CPU time 0.92 seconds
Started Jul 06 06:27:55 PM PDT 24
Finished Jul 06 06:27:57 PM PDT 24
Peak memory 207036 kb
Host smart-aadcb174-f471-4626-a4d3-67cb8b170458
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449465500 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.2449465500
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.2291659629
Short name T205
Test name
Test status
Simulation time 25560408 ps
CPU time 0.8 seconds
Started Jul 06 06:27:44 PM PDT 24
Finished Jul 06 06:27:45 PM PDT 24
Peak memory 216556 kb
Host smart-705bc46d-bfdd-4732-a6d0-8e5a444deb84
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291659629 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.2291659629
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.2821213320
Short name T214
Test name
Test status
Simulation time 35846060 ps
CPU time 1.2 seconds
Started Jul 06 06:27:47 PM PDT 24
Finished Jul 06 06:27:48 PM PDT 24
Peak memory 217324 kb
Host smart-9764e1f7-2cb2-492d-9946-d87df7c264cd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821213320 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.2821213320
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.2587604651
Short name T583
Test name
Test status
Simulation time 37146529 ps
CPU time 1.08 seconds
Started Jul 06 06:27:55 PM PDT 24
Finished Jul 06 06:27:57 PM PDT 24
Peak memory 218960 kb
Host smart-4d681c29-fe99-48b5-b5df-8bbd6ebce35e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587604651 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.2587604651
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.2285677688
Short name T878
Test name
Test status
Simulation time 56727958 ps
CPU time 1.3 seconds
Started Jul 06 06:27:47 PM PDT 24
Finished Jul 06 06:27:48 PM PDT 24
Peak memory 217584 kb
Host smart-e6e64a03-9c84-4852-94f5-62e43fd29096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285677688 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.2285677688
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.2412622168
Short name T851
Test name
Test status
Simulation time 27101530 ps
CPU time 1.13 seconds
Started Jul 06 06:27:49 PM PDT 24
Finished Jul 06 06:27:51 PM PDT 24
Peak memory 215712 kb
Host smart-f4917599-12ee-435e-9481-aef46ee27836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412622168 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.2412622168
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.931946350
Short name T481
Test name
Test status
Simulation time 26771028 ps
CPU time 1.02 seconds
Started Jul 06 06:27:49 PM PDT 24
Finished Jul 06 06:27:50 PM PDT 24
Peak memory 215588 kb
Host smart-9f446bb3-5a5d-4f0a-a948-9dfd03477c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931946350 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.931946350
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.1330698016
Short name T683
Test name
Test status
Simulation time 303784944 ps
CPU time 6 seconds
Started Jul 06 06:27:50 PM PDT 24
Finished Jul 06 06:27:57 PM PDT 24
Peak memory 218748 kb
Host smart-7f86d125-c8ec-4ee1-9b7c-7dbbb36ef9d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330698016 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.1330698016
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.4059125035
Short name T816
Test name
Test status
Simulation time 105630269137 ps
CPU time 2364.05 seconds
Started Jul 06 06:27:47 PM PDT 24
Finished Jul 06 07:07:12 PM PDT 24
Peak memory 228964 kb
Host smart-90f20b7c-348f-4a1e-9353-5c28c58e1b11
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059125035 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.4059125035
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.1093250511
Short name T654
Test name
Test status
Simulation time 367909512 ps
CPU time 1.45 seconds
Started Jul 06 06:27:55 PM PDT 24
Finished Jul 06 06:27:57 PM PDT 24
Peak memory 216056 kb
Host smart-a3211b24-b9bd-4a2a-984a-4f8fb8ab4eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093250511 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.1093250511
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.3490752539
Short name T833
Test name
Test status
Simulation time 22891822 ps
CPU time 0.88 seconds
Started Jul 06 06:27:51 PM PDT 24
Finished Jul 06 06:27:53 PM PDT 24
Peak memory 207112 kb
Host smart-0f358a37-3a28-45fc-8f0d-c8be288921db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490752539 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.3490752539
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.765004450
Short name T223
Test name
Test status
Simulation time 15613475 ps
CPU time 0.81 seconds
Started Jul 06 06:27:51 PM PDT 24
Finished Jul 06 06:27:52 PM PDT 24
Peak memory 215700 kb
Host smart-928f0b6f-70a3-4241-8699-ff37cc43af4b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765004450 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.765004450
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.1792603800
Short name T781
Test name
Test status
Simulation time 42220614 ps
CPU time 1.31 seconds
Started Jul 06 06:27:54 PM PDT 24
Finished Jul 06 06:27:56 PM PDT 24
Peak memory 216056 kb
Host smart-099474f5-511f-47fc-b11f-d8079f8f83a8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792603800 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.1792603800
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.2042024970
Short name T195
Test name
Test status
Simulation time 23893014 ps
CPU time 1.02 seconds
Started Jul 06 06:27:51 PM PDT 24
Finished Jul 06 06:27:53 PM PDT 24
Peak memory 218904 kb
Host smart-67230fc6-4e5f-4287-9af5-d7e2302cb107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042024970 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.2042024970
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.663376698
Short name T474
Test name
Test status
Simulation time 62258346 ps
CPU time 1.5 seconds
Started Jul 06 06:27:50 PM PDT 24
Finished Jul 06 06:27:52 PM PDT 24
Peak memory 219272 kb
Host smart-10934d53-ba31-4ab0-8acc-68d1a2e77b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663376698 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.663376698
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.2753138795
Short name T44
Test name
Test status
Simulation time 33141078 ps
CPU time 0.86 seconds
Started Jul 06 06:27:54 PM PDT 24
Finished Jul 06 06:27:55 PM PDT 24
Peak memory 216068 kb
Host smart-d1781835-c83a-4fa9-ae6a-039c822acb78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753138795 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.2753138795
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.2650283312
Short name T647
Test name
Test status
Simulation time 21692164 ps
CPU time 0.97 seconds
Started Jul 06 06:27:49 PM PDT 24
Finished Jul 06 06:27:50 PM PDT 24
Peak memory 215636 kb
Host smart-5e6e1f65-a1b0-472a-81f2-380e1457c462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650283312 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.2650283312
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.3859204202
Short name T75
Test name
Test status
Simulation time 70080602 ps
CPU time 1.36 seconds
Started Jul 06 06:27:54 PM PDT 24
Finished Jul 06 06:27:57 PM PDT 24
Peak memory 215632 kb
Host smart-237bfe38-d503-4009-92a7-b624380f1916
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859204202 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.3859204202
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.1695280156
Short name T239
Test name
Test status
Simulation time 82069973416 ps
CPU time 1833.48 seconds
Started Jul 06 06:27:50 PM PDT 24
Finished Jul 06 06:58:25 PM PDT 24
Peak memory 226048 kb
Host smart-3935c9c6-3990-4c63-936e-9c30fa21eb8e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695280156 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.1695280156
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.3699222529
Short name T180
Test name
Test status
Simulation time 41176745 ps
CPU time 1.18 seconds
Started Jul 06 06:27:51 PM PDT 24
Finished Jul 06 06:27:52 PM PDT 24
Peak memory 220020 kb
Host smart-9e7b84d2-ab8a-43c6-b10a-4adf08fd14bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699222529 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.3699222529
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.393872966
Short name T504
Test name
Test status
Simulation time 109107471 ps
CPU time 1.47 seconds
Started Jul 06 06:27:48 PM PDT 24
Finished Jul 06 06:27:50 PM PDT 24
Peak memory 207160 kb
Host smart-f84f2f9c-8a04-45af-814c-5d9e1a81e8ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393872966 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.393872966
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.2206036198
Short name T566
Test name
Test status
Simulation time 41297035 ps
CPU time 0.86 seconds
Started Jul 06 06:27:52 PM PDT 24
Finished Jul 06 06:27:53 PM PDT 24
Peak memory 215680 kb
Host smart-23cfe63d-f88a-488b-86ad-8185bde3bc16
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206036198 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.2206036198
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.3978410951
Short name T498
Test name
Test status
Simulation time 41032176 ps
CPU time 1.3 seconds
Started Jul 06 06:27:54 PM PDT 24
Finished Jul 06 06:27:57 PM PDT 24
Peak memory 217324 kb
Host smart-8b16fff6-fe35-4b4b-b551-eb4e7a40d200
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978410951 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.3978410951
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.1917476571
Short name T745
Test name
Test status
Simulation time 30149662 ps
CPU time 0.9 seconds
Started Jul 06 06:27:50 PM PDT 24
Finished Jul 06 06:27:52 PM PDT 24
Peak memory 218328 kb
Host smart-d2240ba0-a108-4e31-b20e-65dd1e996ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917476571 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.1917476571
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.3419586621
Short name T959
Test name
Test status
Simulation time 38272415 ps
CPU time 1.13 seconds
Started Jul 06 06:27:52 PM PDT 24
Finished Jul 06 06:27:54 PM PDT 24
Peak memory 217828 kb
Host smart-e27b3c67-53ae-47e9-8ac0-3a5f4694ed2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419586621 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.3419586621
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.874937859
Short name T34
Test name
Test status
Simulation time 25115342 ps
CPU time 0.95 seconds
Started Jul 06 06:27:50 PM PDT 24
Finished Jul 06 06:27:52 PM PDT 24
Peak memory 216112 kb
Host smart-abbca727-9f00-4380-94a9-92d60a094a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874937859 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.874937859
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.1474642330
Short name T935
Test name
Test status
Simulation time 18984857 ps
CPU time 1 seconds
Started Jul 06 06:27:50 PM PDT 24
Finished Jul 06 06:27:52 PM PDT 24
Peak memory 215652 kb
Host smart-3a2d95b6-7d6e-4a7d-9037-554ed14d12bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474642330 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.1474642330
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.424971533
Short name T114
Test name
Test status
Simulation time 523677927 ps
CPU time 5.21 seconds
Started Jul 06 06:27:54 PM PDT 24
Finished Jul 06 06:27:59 PM PDT 24
Peak memory 217420 kb
Host smart-113a87c9-73dd-43b9-9a91-16669b8e854b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424971533 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.424971533
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.3654916183
Short name T721
Test name
Test status
Simulation time 53339855125 ps
CPU time 684.74 seconds
Started Jul 06 06:27:51 PM PDT 24
Finished Jul 06 06:39:16 PM PDT 24
Peak memory 224100 kb
Host smart-ba29fd6e-91a6-4ba9-88a3-8e4400aee49a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654916183 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.3654916183
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.2163339571
Short name T734
Test name
Test status
Simulation time 23537109 ps
CPU time 1.21 seconds
Started Jul 06 06:27:51 PM PDT 24
Finished Jul 06 06:27:53 PM PDT 24
Peak memory 218796 kb
Host smart-87c694df-db23-4abc-bb25-38d9fcca48bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163339571 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.2163339571
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.3600913147
Short name T369
Test name
Test status
Simulation time 52152813 ps
CPU time 0.97 seconds
Started Jul 06 06:27:55 PM PDT 24
Finished Jul 06 06:27:56 PM PDT 24
Peak memory 215152 kb
Host smart-00974bfb-e80d-49d1-986e-76fec344a591
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600913147 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.3600913147
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.984105558
Short name T199
Test name
Test status
Simulation time 50480410 ps
CPU time 0.82 seconds
Started Jul 06 06:27:53 PM PDT 24
Finished Jul 06 06:27:55 PM PDT 24
Peak memory 216448 kb
Host smart-101342c0-9edb-47fb-b4f1-de1b3bacab91
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984105558 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.984105558
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_err.2902259557
Short name T174
Test name
Test status
Simulation time 30946996 ps
CPU time 0.91 seconds
Started Jul 06 06:27:50 PM PDT 24
Finished Jul 06 06:27:51 PM PDT 24
Peak memory 218624 kb
Host smart-6d21cf9a-600a-4887-9c40-a97d278e5ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902259557 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.2902259557
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.954026275
Short name T735
Test name
Test status
Simulation time 61468475 ps
CPU time 2.29 seconds
Started Jul 06 06:27:54 PM PDT 24
Finished Jul 06 06:27:57 PM PDT 24
Peak memory 220180 kb
Host smart-7f2771aa-e378-4e9f-bfc9-9cf5f36dac21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954026275 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.954026275
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_smoke.2478796464
Short name T631
Test name
Test status
Simulation time 56179982 ps
CPU time 0.93 seconds
Started Jul 06 06:27:50 PM PDT 24
Finished Jul 06 06:27:52 PM PDT 24
Peak memory 215660 kb
Host smart-c6d5521b-4ec5-448a-85ff-bee0f6432c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478796464 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.2478796464
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.994110660
Short name T523
Test name
Test status
Simulation time 1021391248 ps
CPU time 5.78 seconds
Started Jul 06 06:27:51 PM PDT 24
Finished Jul 06 06:27:57 PM PDT 24
Peak memory 217644 kb
Host smart-771d4cd7-aab0-47f1-a102-f5ec62c79b77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994110660 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.994110660
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.1620089453
Short name T232
Test name
Test status
Simulation time 57079293235 ps
CPU time 498.78 seconds
Started Jul 06 06:27:50 PM PDT 24
Finished Jul 06 06:36:10 PM PDT 24
Peak memory 218436 kb
Host smart-589fcc18-1176-4ee0-9595-af870e80d65b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620089453 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.1620089453
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.1764784610
Short name T131
Test name
Test status
Simulation time 35462576 ps
CPU time 1.3 seconds
Started Jul 06 06:27:54 PM PDT 24
Finished Jul 06 06:27:56 PM PDT 24
Peak memory 220312 kb
Host smart-f4e5d1a6-4235-433e-ac8c-5a575dd083e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764784610 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.1764784610
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.1448965334
Short name T968
Test name
Test status
Simulation time 25557534 ps
CPU time 0.84 seconds
Started Jul 06 06:27:56 PM PDT 24
Finished Jul 06 06:27:57 PM PDT 24
Peak memory 207076 kb
Host smart-59e2e346-5d36-4f4c-8460-40f393ec1806
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448965334 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.1448965334
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_err.279061613
Short name T89
Test name
Test status
Simulation time 30945763 ps
CPU time 0.9 seconds
Started Jul 06 06:27:55 PM PDT 24
Finished Jul 06 06:27:56 PM PDT 24
Peak memory 218664 kb
Host smart-a4ac497a-4442-4c25-921f-28b895b3199b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279061613 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.279061613
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.335622760
Short name T534
Test name
Test status
Simulation time 76060594 ps
CPU time 1.35 seconds
Started Jul 06 06:27:54 PM PDT 24
Finished Jul 06 06:27:57 PM PDT 24
Peak memory 219128 kb
Host smart-be74f96b-040c-4c2d-adac-695660b8c475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335622760 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.335622760
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.1462825323
Short name T764
Test name
Test status
Simulation time 23172592 ps
CPU time 1.04 seconds
Started Jul 06 06:28:00 PM PDT 24
Finished Jul 06 06:28:01 PM PDT 24
Peak memory 215712 kb
Host smart-44b2d513-e48e-445d-b3b5-920010ba168f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462825323 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.1462825323
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.3583511232
Short name T410
Test name
Test status
Simulation time 39529049 ps
CPU time 0.9 seconds
Started Jul 06 06:27:58 PM PDT 24
Finished Jul 06 06:27:59 PM PDT 24
Peak memory 215600 kb
Host smart-03bb8e20-f4cc-4be3-a516-60af22d7a001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583511232 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.3583511232
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.3431210851
Short name T247
Test name
Test status
Simulation time 174870411 ps
CPU time 3.64 seconds
Started Jul 06 06:28:00 PM PDT 24
Finished Jul 06 06:28:04 PM PDT 24
Peak memory 217488 kb
Host smart-2309a768-3d54-453a-880f-b045a84c9d13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431210851 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.3431210851
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.3515857220
Short name T229
Test name
Test status
Simulation time 96586157124 ps
CPU time 1217.35 seconds
Started Jul 06 06:27:54 PM PDT 24
Finished Jul 06 06:48:12 PM PDT 24
Peak memory 224512 kb
Host smart-32be6841-bc42-4a00-975e-1e623ff05a90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515857220 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.3515857220
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.1212054332
Short name T613
Test name
Test status
Simulation time 106459165 ps
CPU time 1.24 seconds
Started Jul 06 06:28:02 PM PDT 24
Finished Jul 06 06:28:04 PM PDT 24
Peak memory 219952 kb
Host smart-4972762b-bc3a-4fe8-b95f-e0b606d0b8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212054332 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.1212054332
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.343571830
Short name T449
Test name
Test status
Simulation time 46235735 ps
CPU time 0.91 seconds
Started Jul 06 06:28:02 PM PDT 24
Finished Jul 06 06:28:03 PM PDT 24
Peak memory 215496 kb
Host smart-92993dfb-72eb-4afb-a9ac-d53ba6bd198e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343571830 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.343571830
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.1405436629
Short name T209
Test name
Test status
Simulation time 38791234 ps
CPU time 0.88 seconds
Started Jul 06 06:28:01 PM PDT 24
Finished Jul 06 06:28:02 PM PDT 24
Peak memory 216676 kb
Host smart-99b24e80-2354-4434-b470-ee02e07f6b2f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405436629 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.1405436629
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.3632485125
Short name T22
Test name
Test status
Simulation time 18627504 ps
CPU time 0.95 seconds
Started Jul 06 06:27:59 PM PDT 24
Finished Jul 06 06:28:00 PM PDT 24
Peak memory 218728 kb
Host smart-a5f8353d-a41f-416b-b08a-11526215ce7c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632485125 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.3632485125
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.1257647273
Short name T176
Test name
Test status
Simulation time 29202305 ps
CPU time 0.86 seconds
Started Jul 06 06:27:59 PM PDT 24
Finished Jul 06 06:28:00 PM PDT 24
Peak memory 218304 kb
Host smart-9ca6ab7b-c804-4b55-900e-087e4e0fef91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257647273 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.1257647273
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.2045114159
Short name T24
Test name
Test status
Simulation time 270856954 ps
CPU time 3.58 seconds
Started Jul 06 06:27:57 PM PDT 24
Finished Jul 06 06:28:01 PM PDT 24
Peak memory 219088 kb
Host smart-b1a4a6df-cf45-40da-a927-87394975b5ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045114159 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.2045114159
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.356968164
Short name T406
Test name
Test status
Simulation time 26535004 ps
CPU time 0.99 seconds
Started Jul 06 06:27:58 PM PDT 24
Finished Jul 06 06:27:59 PM PDT 24
Peak memory 215912 kb
Host smart-84dd668e-fece-4b84-9945-7d39c15f837e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356968164 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.356968164
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.1869979693
Short name T750
Test name
Test status
Simulation time 16024317 ps
CPU time 0.97 seconds
Started Jul 06 06:27:53 PM PDT 24
Finished Jul 06 06:27:55 PM PDT 24
Peak memory 215632 kb
Host smart-8a2c20a4-3a50-4b3d-990e-18287e26871f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869979693 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.1869979693
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.3759693752
Short name T568
Test name
Test status
Simulation time 125472646 ps
CPU time 2.88 seconds
Started Jul 06 06:27:54 PM PDT 24
Finished Jul 06 06:27:57 PM PDT 24
Peak memory 220444 kb
Host smart-4bf9aa56-1427-4928-908a-5bb5de24f018
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759693752 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.3759693752
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.2333047133
Short name T709
Test name
Test status
Simulation time 51925442106 ps
CPU time 1195.68 seconds
Started Jul 06 06:27:53 PM PDT 24
Finished Jul 06 06:47:49 PM PDT 24
Peak memory 221884 kb
Host smart-eabbe903-6e50-4509-b657-c2cc1a16692f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333047133 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.2333047133
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.1223045954
Short name T646
Test name
Test status
Simulation time 22480688 ps
CPU time 1.17 seconds
Started Jul 06 06:26:58 PM PDT 24
Finished Jul 06 06:27:00 PM PDT 24
Peak memory 219228 kb
Host smart-70e244f0-a6a3-4043-9eb6-616800b7aee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223045954 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.1223045954
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.2405286298
Short name T365
Test name
Test status
Simulation time 27824473 ps
CPU time 1.1 seconds
Started Jul 06 06:27:02 PM PDT 24
Finished Jul 06 06:27:04 PM PDT 24
Peak memory 207100 kb
Host smart-7ec5ed4b-367b-424e-9325-895fe3ff1502
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405286298 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.2405286298
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.798593911
Short name T925
Test name
Test status
Simulation time 36295156 ps
CPU time 0.9 seconds
Started Jul 06 06:27:06 PM PDT 24
Finished Jul 06 06:27:08 PM PDT 24
Peak memory 216460 kb
Host smart-2bc8ca6f-cacd-47d1-ba21-492f60ad6868
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798593911 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.798593911
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.3677603008
Short name T611
Test name
Test status
Simulation time 30848711 ps
CPU time 1.2 seconds
Started Jul 06 06:26:58 PM PDT 24
Finished Jul 06 06:26:59 PM PDT 24
Peak memory 218508 kb
Host smart-2ae812bd-9c84-46b6-a23c-ea09d1378bff
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677603008 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.3677603008
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.3846950112
Short name T5
Test name
Test status
Simulation time 20337677 ps
CPU time 1.23 seconds
Started Jul 06 06:27:06 PM PDT 24
Finished Jul 06 06:27:08 PM PDT 24
Peak memory 219900 kb
Host smart-3d1ccdbd-97f4-486f-9b9e-b525afb615fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846950112 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.3846950112
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.3295569552
Short name T56
Test name
Test status
Simulation time 77313691 ps
CPU time 1.53 seconds
Started Jul 06 06:26:57 PM PDT 24
Finished Jul 06 06:26:59 PM PDT 24
Peak memory 219396 kb
Host smart-99e7b9c6-ee59-4da2-971d-fea540b9430e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295569552 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.3295569552
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.2836947308
Short name T948
Test name
Test status
Simulation time 41989784 ps
CPU time 0.93 seconds
Started Jul 06 06:26:59 PM PDT 24
Finished Jul 06 06:27:01 PM PDT 24
Peak memory 215784 kb
Host smart-c32d0e6e-505b-473e-b4df-305d0cb7fa2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836947308 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.2836947308
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.745867707
Short name T868
Test name
Test status
Simulation time 32114481 ps
CPU time 0.88 seconds
Started Jul 06 06:26:55 PM PDT 24
Finished Jul 06 06:26:56 PM PDT 24
Peak memory 207372 kb
Host smart-823df332-4d4e-4ee2-adb3-2a308adc69c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745867707 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.745867707
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.4009240339
Short name T18
Test name
Test status
Simulation time 1000383991 ps
CPU time 8.53 seconds
Started Jul 06 06:26:59 PM PDT 24
Finished Jul 06 06:27:08 PM PDT 24
Peak memory 236548 kb
Host smart-ba1bbb4d-e17e-4fa6-a92b-1e1e95cd53f6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009240339 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.4009240339
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.1672062239
Short name T426
Test name
Test status
Simulation time 31532889 ps
CPU time 0.91 seconds
Started Jul 06 06:26:54 PM PDT 24
Finished Jul 06 06:26:55 PM PDT 24
Peak memory 215588 kb
Host smart-3f54851c-2cd2-45ef-9e0f-4cd8379cd3db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672062239 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.1672062239
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.66326505
Short name T874
Test name
Test status
Simulation time 260039542 ps
CPU time 1.93 seconds
Started Jul 06 06:26:54 PM PDT 24
Finished Jul 06 06:26:56 PM PDT 24
Peak memory 215636 kb
Host smart-9eb85ded-4cd2-473d-8fd6-2dd737091b02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66326505 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.66326505
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.804962753
Short name T872
Test name
Test status
Simulation time 1051296114606 ps
CPU time 3039.93 seconds
Started Jul 06 06:26:58 PM PDT 24
Finished Jul 06 07:17:39 PM PDT 24
Peak memory 239896 kb
Host smart-e56c0e2c-c4d1-4711-86a8-7ab0a4e5fdc3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804962753 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.804962753
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.1950708156
Short name T895
Test name
Test status
Simulation time 29939167 ps
CPU time 1.2 seconds
Started Jul 06 06:27:57 PM PDT 24
Finished Jul 06 06:27:59 PM PDT 24
Peak memory 216024 kb
Host smart-71636e5e-b68a-4114-8e99-1f6746967110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950708156 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.1950708156
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.3924143519
Short name T929
Test name
Test status
Simulation time 98261815 ps
CPU time 0.8 seconds
Started Jul 06 06:27:59 PM PDT 24
Finished Jul 06 06:28:00 PM PDT 24
Peak memory 206704 kb
Host smart-e722f899-790a-48b6-811d-5c6cb6a56b3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924143519 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.3924143519
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.521555772
Short name T217
Test name
Test status
Simulation time 62246420 ps
CPU time 0.93 seconds
Started Jul 06 06:27:59 PM PDT 24
Finished Jul 06 06:28:01 PM PDT 24
Peak memory 216548 kb
Host smart-9c284336-8a89-4575-b30b-c44d69dd213d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521555772 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.521555772
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.1743375887
Short name T850
Test name
Test status
Simulation time 43473989 ps
CPU time 1.04 seconds
Started Jul 06 06:28:03 PM PDT 24
Finished Jul 06 06:28:05 PM PDT 24
Peak memory 218492 kb
Host smart-705a520b-a495-4384-8106-a2135c6c9841
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743375887 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.1743375887
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.1013571451
Short name T152
Test name
Test status
Simulation time 26199193 ps
CPU time 1.13 seconds
Started Jul 06 06:28:00 PM PDT 24
Finished Jul 06 06:28:01 PM PDT 24
Peak memory 229964 kb
Host smart-f9e563c9-57c9-4350-917c-a36e740d3fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013571451 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.1013571451
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.3493903348
Short name T60
Test name
Test status
Simulation time 54819415 ps
CPU time 2.05 seconds
Started Jul 06 06:27:59 PM PDT 24
Finished Jul 06 06:28:01 PM PDT 24
Peak memory 218888 kb
Host smart-c40ab623-2b06-4b5c-995f-fd70d0c81bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493903348 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.3493903348
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.1210245733
Short name T37
Test name
Test status
Simulation time 21984540 ps
CPU time 1.11 seconds
Started Jul 06 06:27:59 PM PDT 24
Finished Jul 06 06:28:00 PM PDT 24
Peak memory 216200 kb
Host smart-e4be0031-7939-434b-8e5d-fbcc11360f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210245733 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.1210245733
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.772876969
Short name T956
Test name
Test status
Simulation time 17007708 ps
CPU time 1.01 seconds
Started Jul 06 06:28:00 PM PDT 24
Finished Jul 06 06:28:02 PM PDT 24
Peak memory 215668 kb
Host smart-fd636dbb-91b9-40fa-9cd8-8d7c67bc8889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772876969 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.772876969
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.502775982
Short name T697
Test name
Test status
Simulation time 293932825 ps
CPU time 5.81 seconds
Started Jul 06 06:28:00 PM PDT 24
Finished Jul 06 06:28:07 PM PDT 24
Peak memory 217636 kb
Host smart-5e68049c-7158-4dfe-8714-dbb9bb33d229
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502775982 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.502775982
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.533798069
Short name T635
Test name
Test status
Simulation time 53588394269 ps
CPU time 1179.85 seconds
Started Jul 06 06:27:58 PM PDT 24
Finished Jul 06 06:47:38 PM PDT 24
Peak memory 221512 kb
Host smart-5ddc175b-fb05-41b1-8dd6-4551c97eb714
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533798069 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.533798069
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.1524796524
Short name T814
Test name
Test status
Simulation time 268083604 ps
CPU time 1.29 seconds
Started Jul 06 06:27:58 PM PDT 24
Finished Jul 06 06:27:59 PM PDT 24
Peak memory 220780 kb
Host smart-8aa5574e-6716-4719-907e-14dcb5285426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524796524 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.1524796524
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.1844049947
Short name T383
Test name
Test status
Simulation time 28558706 ps
CPU time 0.97 seconds
Started Jul 06 06:28:02 PM PDT 24
Finished Jul 06 06:28:03 PM PDT 24
Peak memory 207068 kb
Host smart-614136fe-ed37-4378-8849-5997e7caf12c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844049947 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.1844049947
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.599972641
Short name T862
Test name
Test status
Simulation time 25548373 ps
CPU time 0.89 seconds
Started Jul 06 06:27:59 PM PDT 24
Finished Jul 06 06:28:01 PM PDT 24
Peak memory 216572 kb
Host smart-82da91fc-050f-49af-9096-079ca0cc55fe
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599972641 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.599972641
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.1776737127
Short name T541
Test name
Test status
Simulation time 59989613 ps
CPU time 1.21 seconds
Started Jul 06 06:28:01 PM PDT 24
Finished Jul 06 06:28:03 PM PDT 24
Peak memory 218872 kb
Host smart-0f87777b-f249-46b0-9f79-ef7e3feae8f6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776737127 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.1776737127
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.3058298489
Short name T40
Test name
Test status
Simulation time 21103553 ps
CPU time 1.1 seconds
Started Jul 06 06:28:00 PM PDT 24
Finished Jul 06 06:28:01 PM PDT 24
Peak memory 218864 kb
Host smart-b2b6a196-dc1b-41f7-87bd-db53497613ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058298489 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.3058298489
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.1183476982
Short name T896
Test name
Test status
Simulation time 41227927 ps
CPU time 1.41 seconds
Started Jul 06 06:27:59 PM PDT 24
Finished Jul 06 06:28:01 PM PDT 24
Peak memory 217584 kb
Host smart-bd836ba4-a160-40cf-b760-98cabc055fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183476982 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.1183476982
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.275874531
Short name T64
Test name
Test status
Simulation time 36655387 ps
CPU time 1 seconds
Started Jul 06 06:27:56 PM PDT 24
Finished Jul 06 06:27:57 PM PDT 24
Peak memory 224180 kb
Host smart-0270e58c-db8f-479f-8a8e-bca943d7e7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275874531 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.275874531
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.956125508
Short name T854
Test name
Test status
Simulation time 50854107 ps
CPU time 1 seconds
Started Jul 06 06:28:02 PM PDT 24
Finished Jul 06 06:28:03 PM PDT 24
Peak memory 215620 kb
Host smart-b7ba993c-89ab-4ec0-a3c7-e89c37853451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956125508 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.956125508
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.954043030
Short name T615
Test name
Test status
Simulation time 175061114 ps
CPU time 3.13 seconds
Started Jul 06 06:28:03 PM PDT 24
Finished Jul 06 06:28:07 PM PDT 24
Peak memory 217516 kb
Host smart-65f9b2fd-a96a-437b-afb2-21837bc7e340
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954043030 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.954043030
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.2453345586
Short name T235
Test name
Test status
Simulation time 227892824746 ps
CPU time 1327.95 seconds
Started Jul 06 06:28:04 PM PDT 24
Finished Jul 06 06:50:13 PM PDT 24
Peak memory 224132 kb
Host smart-72537b58-4cc1-48a1-a196-6f83429e8c0e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453345586 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.2453345586
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.2840936425
Short name T918
Test name
Test status
Simulation time 69930979 ps
CPU time 1.25 seconds
Started Jul 06 06:28:06 PM PDT 24
Finished Jul 06 06:28:08 PM PDT 24
Peak memory 220072 kb
Host smart-2fe3ff96-f7db-4137-95bb-62af7a619ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840936425 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.2840936425
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.2851672577
Short name T970
Test name
Test status
Simulation time 12910628 ps
CPU time 0.86 seconds
Started Jul 06 06:28:15 PM PDT 24
Finished Jul 06 06:28:17 PM PDT 24
Peak memory 207248 kb
Host smart-b17423be-7782-48f5-89e0-286075b46780
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851672577 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.2851672577
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.804479446
Short name T200
Test name
Test status
Simulation time 28173591 ps
CPU time 0.94 seconds
Started Jul 06 06:28:14 PM PDT 24
Finished Jul 06 06:28:15 PM PDT 24
Peak memory 216424 kb
Host smart-547e4bc9-d895-4ce7-b8f4-ed772d827ff5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804479446 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.804479446
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.3560471801
Short name T471
Test name
Test status
Simulation time 24302382 ps
CPU time 1.01 seconds
Started Jul 06 06:28:03 PM PDT 24
Finished Jul 06 06:28:05 PM PDT 24
Peak memory 218788 kb
Host smart-805bea4d-15be-45d4-98eb-b19838b5df9c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560471801 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.3560471801
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.3573042693
Short name T112
Test name
Test status
Simulation time 91668795 ps
CPU time 1.08 seconds
Started Jul 06 06:28:02 PM PDT 24
Finished Jul 06 06:28:03 PM PDT 24
Peak memory 218792 kb
Host smart-2d36018b-a3bc-4a36-9a81-0cad36c36181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573042693 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.3573042693
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.1642153476
Short name T624
Test name
Test status
Simulation time 199144256 ps
CPU time 1.26 seconds
Started Jul 06 06:28:02 PM PDT 24
Finished Jul 06 06:28:04 PM PDT 24
Peak memory 220388 kb
Host smart-b698f679-6ab6-46b5-9e08-0081792244c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642153476 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.1642153476
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.1552440091
Short name T36
Test name
Test status
Simulation time 22006665 ps
CPU time 1.09 seconds
Started Jul 06 06:28:14 PM PDT 24
Finished Jul 06 06:28:15 PM PDT 24
Peak memory 215944 kb
Host smart-4dcb67f7-0df2-496b-bc97-6be823c310d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552440091 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.1552440091
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.845831466
Short name T700
Test name
Test status
Simulation time 20260226 ps
CPU time 1.02 seconds
Started Jul 06 06:28:04 PM PDT 24
Finished Jul 06 06:28:05 PM PDT 24
Peak memory 215628 kb
Host smart-7d2bc63e-2bdb-4890-86a6-444ed0798d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845831466 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.845831466
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.3470161979
Short name T744
Test name
Test status
Simulation time 45569992 ps
CPU time 1.28 seconds
Started Jul 06 06:28:03 PM PDT 24
Finished Jul 06 06:28:05 PM PDT 24
Peak memory 207532 kb
Host smart-45379bb5-6e0f-44a4-8450-0db572584249
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470161979 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.3470161979
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.1962345033
Short name T452
Test name
Test status
Simulation time 133708895193 ps
CPU time 1975.45 seconds
Started Jul 06 06:28:03 PM PDT 24
Finished Jul 06 07:01:00 PM PDT 24
Peak memory 227312 kb
Host smart-2560a748-cb91-4014-b27e-fc8074151270
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962345033 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.1962345033
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.3047069783
Short name T287
Test name
Test status
Simulation time 186297250 ps
CPU time 1.3 seconds
Started Jul 06 06:28:05 PM PDT 24
Finished Jul 06 06:28:07 PM PDT 24
Peak memory 218736 kb
Host smart-b864c8ec-1475-414c-bbbe-1dd7b8046f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047069783 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.3047069783
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.1402578514
Short name T473
Test name
Test status
Simulation time 41761532 ps
CPU time 0.93 seconds
Started Jul 06 06:28:03 PM PDT 24
Finished Jul 06 06:28:05 PM PDT 24
Peak memory 215164 kb
Host smart-e8aa601d-c47d-4696-9049-6ac04a7446a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402578514 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.1402578514
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.2331979269
Short name T584
Test name
Test status
Simulation time 13672720 ps
CPU time 0.94 seconds
Started Jul 06 06:28:04 PM PDT 24
Finished Jul 06 06:28:05 PM PDT 24
Peak memory 216368 kb
Host smart-bd7fa0d1-6a90-48e6-bfab-451945a8b180
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331979269 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.2331979269
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_err.779034371
Short name T563
Test name
Test status
Simulation time 19890032 ps
CPU time 1.05 seconds
Started Jul 06 06:28:07 PM PDT 24
Finished Jul 06 06:28:09 PM PDT 24
Peak memory 218744 kb
Host smart-20082e47-4930-4e44-bfd3-85822e115cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779034371 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.779034371
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.3900762032
Short name T348
Test name
Test status
Simulation time 44889945 ps
CPU time 1.65 seconds
Started Jul 06 06:28:01 PM PDT 24
Finished Jul 06 06:28:03 PM PDT 24
Peak memory 218912 kb
Host smart-3d847ce8-5a8a-4543-ab49-befaade5ea17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900762032 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.3900762032
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.3949414987
Short name T867
Test name
Test status
Simulation time 21868544 ps
CPU time 1.17 seconds
Started Jul 06 06:28:15 PM PDT 24
Finished Jul 06 06:28:17 PM PDT 24
Peak memory 224296 kb
Host smart-f7c3f014-0fb4-434d-8abf-2f60963994a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949414987 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.3949414987
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.2991096088
Short name T810
Test name
Test status
Simulation time 19995605 ps
CPU time 1.05 seconds
Started Jul 06 06:28:04 PM PDT 24
Finished Jul 06 06:28:05 PM PDT 24
Peak memory 215656 kb
Host smart-83437e67-492c-4e1e-ad67-88e2f154c6ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991096088 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.2991096088
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.1612150272
Short name T85
Test name
Test status
Simulation time 402138837 ps
CPU time 2.74 seconds
Started Jul 06 06:28:13 PM PDT 24
Finished Jul 06 06:28:17 PM PDT 24
Peak memory 217460 kb
Host smart-0439de29-fbd5-4e6b-b714-a0feb177e359
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612150272 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.1612150272
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.1111272228
Short name T733
Test name
Test status
Simulation time 58801552155 ps
CPU time 1523.04 seconds
Started Jul 06 06:28:04 PM PDT 24
Finished Jul 06 06:53:28 PM PDT 24
Peak memory 225404 kb
Host smart-43e69806-0872-4c1e-b4ac-d4f389f25482
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111272228 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.1111272228
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.4057868365
Short name T393
Test name
Test status
Simulation time 134116609 ps
CPU time 1.2 seconds
Started Jul 06 06:28:14 PM PDT 24
Finished Jul 06 06:28:15 PM PDT 24
Peak memory 218708 kb
Host smart-2de81ad9-b45e-4e5c-84f0-34bedd5ecd27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057868365 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.4057868365
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.1189683285
Short name T748
Test name
Test status
Simulation time 40390651 ps
CPU time 0.98 seconds
Started Jul 06 06:28:12 PM PDT 24
Finished Jul 06 06:28:14 PM PDT 24
Peak memory 207028 kb
Host smart-bb82cec0-7cec-4d4d-9e84-059d6313c7e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189683285 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.1189683285
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.182551525
Short name T161
Test name
Test status
Simulation time 16983977 ps
CPU time 0.84 seconds
Started Jul 06 06:28:07 PM PDT 24
Finished Jul 06 06:28:08 PM PDT 24
Peak memory 215680 kb
Host smart-425be182-a0b9-44a5-bc80-372effb07570
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182551525 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.182551525
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.140847811
Short name T548
Test name
Test status
Simulation time 88426821 ps
CPU time 1.05 seconds
Started Jul 06 06:28:04 PM PDT 24
Finished Jul 06 06:28:06 PM PDT 24
Peak memory 218608 kb
Host smart-1b6f346e-7689-4523-90f1-41b1fea15bcf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140847811 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_di
sable_auto_req_mode.140847811
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.1185841399
Short name T167
Test name
Test status
Simulation time 19631078 ps
CPU time 1.14 seconds
Started Jul 06 06:28:16 PM PDT 24
Finished Jul 06 06:28:17 PM PDT 24
Peak memory 224244 kb
Host smart-3eb029ed-1eb4-4550-af63-d2c9b98dd489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185841399 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.1185841399
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.3096181920
Short name T736
Test name
Test status
Simulation time 237571565 ps
CPU time 2.81 seconds
Started Jul 06 06:28:04 PM PDT 24
Finished Jul 06 06:28:08 PM PDT 24
Peak memory 219976 kb
Host smart-8f954455-016c-4ad3-84ac-2f7335a7be1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096181920 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.3096181920
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.3516102246
Short name T79
Test name
Test status
Simulation time 36973941 ps
CPU time 0.87 seconds
Started Jul 06 06:28:12 PM PDT 24
Finished Jul 06 06:28:13 PM PDT 24
Peak memory 216012 kb
Host smart-84eebcc9-7dac-4d70-8003-e83c60575146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516102246 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.3516102246
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.3854481425
Short name T392
Test name
Test status
Simulation time 14613264 ps
CPU time 1 seconds
Started Jul 06 06:28:03 PM PDT 24
Finished Jul 06 06:28:04 PM PDT 24
Peak memory 215672 kb
Host smart-af231dbc-754e-4590-98de-30119d0d0a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854481425 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.3854481425
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.2101514430
Short name T253
Test name
Test status
Simulation time 119772346 ps
CPU time 2.67 seconds
Started Jul 06 06:28:06 PM PDT 24
Finished Jul 06 06:28:10 PM PDT 24
Peak memory 215568 kb
Host smart-93831bf4-c8d5-48bd-ae96-225145fe5b37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101514430 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.2101514430
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.405951999
Short name T958
Test name
Test status
Simulation time 161515899352 ps
CPU time 384.22 seconds
Started Jul 06 06:28:04 PM PDT 24
Finished Jul 06 06:34:29 PM PDT 24
Peak memory 224140 kb
Host smart-09f026d2-fe5e-4398-b755-14526f79fd4e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405951999 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.405951999
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.3874517341
Short name T953
Test name
Test status
Simulation time 78092111 ps
CPU time 1.18 seconds
Started Jul 06 06:28:06 PM PDT 24
Finished Jul 06 06:28:08 PM PDT 24
Peak memory 218892 kb
Host smart-367a97b2-9c2e-4fd1-817b-125ff61b5d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874517341 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.3874517341
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.2943762063
Short name T30
Test name
Test status
Simulation time 30627965 ps
CPU time 1.09 seconds
Started Jul 06 06:28:07 PM PDT 24
Finished Jul 06 06:28:09 PM PDT 24
Peak memory 215464 kb
Host smart-df851d5d-5bb3-4ae5-8421-b95678638841
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943762063 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.2943762063
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.2979404935
Short name T571
Test name
Test status
Simulation time 14583677 ps
CPU time 0.92 seconds
Started Jul 06 06:28:07 PM PDT 24
Finished Jul 06 06:28:08 PM PDT 24
Peak memory 216692 kb
Host smart-b850f371-ad68-49ab-84a7-e29c74efbf9d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979404935 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.2979404935
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.1655069686
Short name T796
Test name
Test status
Simulation time 56798555 ps
CPU time 1.23 seconds
Started Jul 06 06:28:08 PM PDT 24
Finished Jul 06 06:28:10 PM PDT 24
Peak memory 217348 kb
Host smart-4ac0d512-4663-4916-8817-e18d4ecb2879
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655069686 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.1655069686
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_genbits.2977226292
Short name T598
Test name
Test status
Simulation time 46976477 ps
CPU time 1.81 seconds
Started Jul 06 06:28:04 PM PDT 24
Finished Jul 06 06:28:06 PM PDT 24
Peak memory 218884 kb
Host smart-819f0536-9a8e-4657-98da-3595a498ef43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977226292 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.2977226292
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.1376423972
Short name T979
Test name
Test status
Simulation time 22669921 ps
CPU time 1.26 seconds
Started Jul 06 06:28:17 PM PDT 24
Finished Jul 06 06:28:19 PM PDT 24
Peak memory 224296 kb
Host smart-1dfb086d-8ab1-433e-bf6e-ee6a2ae04e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376423972 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.1376423972
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.689956363
Short name T869
Test name
Test status
Simulation time 20193346 ps
CPU time 0.95 seconds
Started Jul 06 06:28:07 PM PDT 24
Finished Jul 06 06:28:09 PM PDT 24
Peak memory 207384 kb
Host smart-65424539-965c-47de-a14c-0d3d43827cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689956363 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.689956363
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.2965310926
Short name T488
Test name
Test status
Simulation time 107027831 ps
CPU time 1.18 seconds
Started Jul 06 06:28:14 PM PDT 24
Finished Jul 06 06:28:16 PM PDT 24
Peak memory 207384 kb
Host smart-6fc9c22d-fed7-41b5-a304-22b5e2de97a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965310926 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.2965310926
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.1577129556
Short name T891
Test name
Test status
Simulation time 50454996530 ps
CPU time 1122.11 seconds
Started Jul 06 06:28:15 PM PDT 24
Finished Jul 06 06:46:58 PM PDT 24
Peak memory 223988 kb
Host smart-02edb25d-129e-4414-9545-210d07ffa7ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577129556 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.1577129556
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.1019486096
Short name T790
Test name
Test status
Simulation time 39661823 ps
CPU time 1.16 seconds
Started Jul 06 06:28:12 PM PDT 24
Finished Jul 06 06:28:14 PM PDT 24
Peak memory 218800 kb
Host smart-76a6567a-23e7-4436-a282-bdf5f8b40079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019486096 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.1019486096
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.3671708763
Short name T607
Test name
Test status
Simulation time 57273713 ps
CPU time 0.91 seconds
Started Jul 06 06:28:21 PM PDT 24
Finished Jul 06 06:28:23 PM PDT 24
Peak memory 215172 kb
Host smart-c16886ee-5578-494b-b51e-231887a9a363
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671708763 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.3671708763
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.678115855
Short name T95
Test name
Test status
Simulation time 19210570 ps
CPU time 0.86 seconds
Started Jul 06 06:28:06 PM PDT 24
Finished Jul 06 06:28:07 PM PDT 24
Peak memory 215780 kb
Host smart-183d2ede-d47e-40c8-839f-8079bca3cee6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678115855 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.678115855
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.2826302988
Short name T901
Test name
Test status
Simulation time 116602809 ps
CPU time 1.03 seconds
Started Jul 06 06:28:06 PM PDT 24
Finished Jul 06 06:28:07 PM PDT 24
Peak memory 219940 kb
Host smart-ca2f80a6-fa6f-419f-b115-e20657d5038c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826302988 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.2826302988
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.1992110060
Short name T809
Test name
Test status
Simulation time 21209211 ps
CPU time 0.9 seconds
Started Jul 06 06:28:07 PM PDT 24
Finished Jul 06 06:28:08 PM PDT 24
Peak memory 218616 kb
Host smart-f0fa52e7-4c2b-446f-940b-ceb3e480ea29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992110060 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.1992110060
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.1418755698
Short name T417
Test name
Test status
Simulation time 56836609 ps
CPU time 1.65 seconds
Started Jul 06 06:28:08 PM PDT 24
Finished Jul 06 06:28:10 PM PDT 24
Peak memory 218908 kb
Host smart-2da44339-ed06-44ae-be64-c7bcd5305c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418755698 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.1418755698
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.1901887724
Short name T42
Test name
Test status
Simulation time 30297388 ps
CPU time 0.91 seconds
Started Jul 06 06:28:06 PM PDT 24
Finished Jul 06 06:28:08 PM PDT 24
Peak memory 215948 kb
Host smart-4e64e762-f967-44dd-8c76-86882b05b195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901887724 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.1901887724
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.4090257348
Short name T360
Test name
Test status
Simulation time 18830982 ps
CPU time 1.06 seconds
Started Jul 06 06:28:06 PM PDT 24
Finished Jul 06 06:28:08 PM PDT 24
Peak memory 215608 kb
Host smart-e6d69c72-9bda-4fe3-89ec-576301afbe6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090257348 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.4090257348
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.1135043336
Short name T746
Test name
Test status
Simulation time 634192404 ps
CPU time 3.27 seconds
Started Jul 06 06:28:07 PM PDT 24
Finished Jul 06 06:28:11 PM PDT 24
Peak memory 215572 kb
Host smart-1c22f15f-ce39-4877-ab88-63f1a259abb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135043336 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.1135043336
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.3675696474
Short name T233
Test name
Test status
Simulation time 430334509888 ps
CPU time 2417.62 seconds
Started Jul 06 06:28:06 PM PDT 24
Finished Jul 06 07:08:24 PM PDT 24
Peak memory 228880 kb
Host smart-d3e6a5cb-7819-48ef-988d-7f4bda4d46d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675696474 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.3675696474
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.2323304459
Short name T817
Test name
Test status
Simulation time 89521023 ps
CPU time 1.26 seconds
Started Jul 06 06:28:04 PM PDT 24
Finished Jul 06 06:28:06 PM PDT 24
Peak memory 215964 kb
Host smart-dd57c8f5-8a0e-499f-87dc-2b4bd17781d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323304459 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.2323304459
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.1213716421
Short name T578
Test name
Test status
Simulation time 18522048 ps
CPU time 0.96 seconds
Started Jul 06 06:28:10 PM PDT 24
Finished Jul 06 06:28:11 PM PDT 24
Peak memory 207348 kb
Host smart-18967342-7f68-4b91-9b0b-75c3e929995a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213716421 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.1213716421
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.197362853
Short name T196
Test name
Test status
Simulation time 12111514 ps
CPU time 0.92 seconds
Started Jul 06 06:28:09 PM PDT 24
Finished Jul 06 06:28:10 PM PDT 24
Peak memory 216764 kb
Host smart-2425d8f8-e3ee-4e13-ab37-cba6837e3ab3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197362853 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.197362853
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.39278699
Short name T97
Test name
Test status
Simulation time 96842849 ps
CPU time 1.05 seconds
Started Jul 06 06:28:16 PM PDT 24
Finished Jul 06 06:28:18 PM PDT 24
Peak memory 217376 kb
Host smart-b3a168b0-254e-4e83-a52d-474e8bc7a13c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39278699 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_dis
able_auto_req_mode.39278699
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.1410949397
Short name T147
Test name
Test status
Simulation time 24406244 ps
CPU time 1 seconds
Started Jul 06 06:28:06 PM PDT 24
Finished Jul 06 06:28:07 PM PDT 24
Peak memory 220184 kb
Host smart-c799bf61-89ac-4673-875c-adca5985e6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410949397 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.1410949397
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.2564181335
Short name T321
Test name
Test status
Simulation time 28818530 ps
CPU time 1.32 seconds
Started Jul 06 06:28:09 PM PDT 24
Finished Jul 06 06:28:10 PM PDT 24
Peak memory 217940 kb
Host smart-1501f6f1-27ab-4b05-9386-d39f3e0410ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564181335 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.2564181335
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.13188977
Short name T416
Test name
Test status
Simulation time 22233807 ps
CPU time 1.07 seconds
Started Jul 06 06:28:16 PM PDT 24
Finished Jul 06 06:28:17 PM PDT 24
Peak memory 216132 kb
Host smart-3ee932ac-48e8-4a60-9ac4-1dec16594126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13188977 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.13188977
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.3944489816
Short name T506
Test name
Test status
Simulation time 20094875 ps
CPU time 1.09 seconds
Started Jul 06 06:28:06 PM PDT 24
Finished Jul 06 06:28:07 PM PDT 24
Peak memory 215660 kb
Host smart-ad13b892-7131-4454-b673-33a79e729e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944489816 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.3944489816
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.851107775
Short name T681
Test name
Test status
Simulation time 718212947 ps
CPU time 4.02 seconds
Started Jul 06 06:28:15 PM PDT 24
Finished Jul 06 06:28:19 PM PDT 24
Peak memory 217708 kb
Host smart-82e80af0-b5a2-4674-a5da-a875d3f8c4b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851107775 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.851107775
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.2624249607
Short name T849
Test name
Test status
Simulation time 315954623265 ps
CPU time 1999.94 seconds
Started Jul 06 06:28:06 PM PDT 24
Finished Jul 06 07:01:26 PM PDT 24
Peak memory 230172 kb
Host smart-dc32dddd-f813-4fa1-9699-068956ffe011
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624249607 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.2624249607
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.2473443976
Short name T243
Test name
Test status
Simulation time 38215037 ps
CPU time 1.1 seconds
Started Jul 06 06:28:18 PM PDT 24
Finished Jul 06 06:28:19 PM PDT 24
Peak memory 219004 kb
Host smart-5042e8a0-9723-4435-85fe-00304ff10028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473443976 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.2473443976
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.3358834631
Short name T829
Test name
Test status
Simulation time 119365699 ps
CPU time 0.89 seconds
Started Jul 06 06:28:11 PM PDT 24
Finished Jul 06 06:28:12 PM PDT 24
Peak memory 207088 kb
Host smart-8ee9cb4e-bb2a-4db3-8ef1-0bdce5940b8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358834631 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.3358834631
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.709726867
Short name T419
Test name
Test status
Simulation time 27738949 ps
CPU time 0.86 seconds
Started Jul 06 06:28:12 PM PDT 24
Finished Jul 06 06:28:13 PM PDT 24
Peak memory 216564 kb
Host smart-3818c3c0-a529-485f-956d-d3d457f0cdfc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709726867 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.709726867
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.653741392
Short name T249
Test name
Test status
Simulation time 47684466 ps
CPU time 1.03 seconds
Started Jul 06 06:28:09 PM PDT 24
Finished Jul 06 06:28:10 PM PDT 24
Peak memory 217188 kb
Host smart-ff3789e0-6c36-4628-be76-e3189e86c768
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653741392 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_di
sable_auto_req_mode.653741392
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.2054906762
Short name T218
Test name
Test status
Simulation time 101606037 ps
CPU time 0.89 seconds
Started Jul 06 06:28:19 PM PDT 24
Finished Jul 06 06:28:20 PM PDT 24
Peak memory 219952 kb
Host smart-fa7b9e25-1eed-4748-8713-dd8ed6b1153d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054906762 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.2054906762
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.3171833488
Short name T694
Test name
Test status
Simulation time 70105313 ps
CPU time 1.12 seconds
Started Jul 06 06:28:05 PM PDT 24
Finished Jul 06 06:28:07 PM PDT 24
Peak memory 218720 kb
Host smart-7176bce8-7845-4973-8898-ec9343fe63fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171833488 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.3171833488
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.8288666
Short name T665
Test name
Test status
Simulation time 30917149 ps
CPU time 0.88 seconds
Started Jul 06 06:28:15 PM PDT 24
Finished Jul 06 06:28:17 PM PDT 24
Peak memory 215912 kb
Host smart-b1d0aed4-285a-4907-8955-fb6b4c876399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8288666 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.8288666
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.3220685594
Short name T430
Test name
Test status
Simulation time 15524631 ps
CPU time 0.96 seconds
Started Jul 06 06:28:06 PM PDT 24
Finished Jul 06 06:28:07 PM PDT 24
Peak memory 215612 kb
Host smart-c621fa2d-3d86-4e67-a3f7-3c5460a873d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220685594 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.3220685594
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.1736757924
Short name T424
Test name
Test status
Simulation time 520552087 ps
CPU time 4.13 seconds
Started Jul 06 06:28:07 PM PDT 24
Finished Jul 06 06:28:12 PM PDT 24
Peak memory 217696 kb
Host smart-e9e964cd-ad4a-4908-9759-daf84e6f8b05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736757924 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.1736757924
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.1900203268
Short name T465
Test name
Test status
Simulation time 1410816388422 ps
CPU time 1633.79 seconds
Started Jul 06 06:28:15 PM PDT 24
Finished Jul 06 06:55:29 PM PDT 24
Peak memory 226392 kb
Host smart-81d3a36e-0f20-4269-9229-2ae58c86b654
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900203268 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.1900203268
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.727378768
Short name T812
Test name
Test status
Simulation time 46156112 ps
CPU time 1.19 seconds
Started Jul 06 06:28:10 PM PDT 24
Finished Jul 06 06:28:12 PM PDT 24
Peak memory 220080 kb
Host smart-ad3aaa04-8115-4206-aea4-6f75a3a77673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727378768 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.727378768
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.1540250491
Short name T645
Test name
Test status
Simulation time 73329918 ps
CPU time 0.97 seconds
Started Jul 06 06:28:12 PM PDT 24
Finished Jul 06 06:28:14 PM PDT 24
Peak memory 215512 kb
Host smart-8af25e1a-6138-44b3-90cf-94ebb5571218
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540250491 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.1540250491
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.4271383551
Short name T939
Test name
Test status
Simulation time 22253918 ps
CPU time 0.91 seconds
Started Jul 06 06:28:12 PM PDT 24
Finished Jul 06 06:28:13 PM PDT 24
Peak memory 215732 kb
Host smart-d18b3eb8-ebaa-46ee-aa4d-6a717c204bcf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271383551 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.4271383551
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.1960925616
Short name T124
Test name
Test status
Simulation time 131892977 ps
CPU time 1.22 seconds
Started Jul 06 06:28:19 PM PDT 24
Finished Jul 06 06:28:20 PM PDT 24
Peak memory 217332 kb
Host smart-b48cc753-d158-425d-9624-c87fdba20170
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960925616 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.1960925616
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.25512757
Short name T904
Test name
Test status
Simulation time 24818193 ps
CPU time 1.17 seconds
Started Jul 06 06:28:12 PM PDT 24
Finished Jul 06 06:28:13 PM PDT 24
Peak memory 218704 kb
Host smart-618fc81e-f528-4274-87ca-f407d3ad3d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25512757 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.25512757
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.661340144
Short name T751
Test name
Test status
Simulation time 79670127 ps
CPU time 1.41 seconds
Started Jul 06 06:28:18 PM PDT 24
Finished Jul 06 06:28:20 PM PDT 24
Peak memory 218872 kb
Host smart-4bc668ad-5cb4-4e14-ab5c-b9d7c95f9d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661340144 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.661340144
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.3328862819
Short name T38
Test name
Test status
Simulation time 19875261 ps
CPU time 1.09 seconds
Started Jul 06 06:28:12 PM PDT 24
Finished Jul 06 06:28:13 PM PDT 24
Peak memory 216084 kb
Host smart-a93edf10-f949-471d-a094-d11e4ab12e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328862819 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.3328862819
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.4291448448
Short name T831
Test name
Test status
Simulation time 15239613 ps
CPU time 0.98 seconds
Started Jul 06 06:28:09 PM PDT 24
Finished Jul 06 06:28:11 PM PDT 24
Peak memory 215632 kb
Host smart-fb7426e3-8c92-4cd2-8064-0a3711531f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291448448 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.4291448448
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.3094336264
Short name T296
Test name
Test status
Simulation time 151863561 ps
CPU time 3.21 seconds
Started Jul 06 06:28:12 PM PDT 24
Finished Jul 06 06:28:16 PM PDT 24
Peak memory 217588 kb
Host smart-e305be45-0b60-4303-af38-73f578d1a887
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094336264 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.3094336264
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.1091834466
Short name T240
Test name
Test status
Simulation time 360742121781 ps
CPU time 1346.76 seconds
Started Jul 06 06:28:12 PM PDT 24
Finished Jul 06 06:50:40 PM PDT 24
Peak memory 223284 kb
Host smart-c819acca-3bd1-4148-b97f-c4f50949892f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091834466 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.1091834466
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.1229931353
Short name T310
Test name
Test status
Simulation time 62971822 ps
CPU time 1.07 seconds
Started Jul 06 06:26:59 PM PDT 24
Finished Jul 06 06:27:00 PM PDT 24
Peak memory 220072 kb
Host smart-24cb52a0-a595-473d-9c98-ffb70784797f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229931353 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.1229931353
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.2970656315
Short name T82
Test name
Test status
Simulation time 65214853 ps
CPU time 1 seconds
Started Jul 06 06:27:01 PM PDT 24
Finished Jul 06 06:27:03 PM PDT 24
Peak memory 207088 kb
Host smart-4d3c4a58-48ec-4b67-aafa-80d8d655a1b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970656315 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.2970656315
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.2407541192
Short name T170
Test name
Test status
Simulation time 12047170 ps
CPU time 0.88 seconds
Started Jul 06 06:27:00 PM PDT 24
Finished Jul 06 06:27:01 PM PDT 24
Peak memory 216848 kb
Host smart-6f4c395f-e3db-4753-9161-e4d727d1c711
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407541192 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.2407541192
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.114859841
Short name T446
Test name
Test status
Simulation time 29944850 ps
CPU time 1.19 seconds
Started Jul 06 06:27:03 PM PDT 24
Finished Jul 06 06:27:05 PM PDT 24
Peak memory 220028 kb
Host smart-c2777035-f652-4def-afa7-c4cfea88b091
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114859841 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_dis
able_auto_req_mode.114859841
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.1589389961
Short name T658
Test name
Test status
Simulation time 120043789 ps
CPU time 0.96 seconds
Started Jul 06 06:27:02 PM PDT 24
Finished Jul 06 06:27:04 PM PDT 24
Peak memory 220072 kb
Host smart-63b242c7-8d2f-4974-8255-8e7f0789f168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589389961 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.1589389961
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.1423765513
Short name T777
Test name
Test status
Simulation time 62864753 ps
CPU time 1.68 seconds
Started Jul 06 06:26:59 PM PDT 24
Finished Jul 06 06:27:01 PM PDT 24
Peak memory 218848 kb
Host smart-fa01be39-1f90-4845-a0e4-914952445f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423765513 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.1423765513
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.1951185536
Short name T407
Test name
Test status
Simulation time 22522012 ps
CPU time 1.23 seconds
Started Jul 06 06:26:59 PM PDT 24
Finished Jul 06 06:27:01 PM PDT 24
Peak memory 224332 kb
Host smart-68dc9c28-ef64-40fe-8950-eb91037e624a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951185536 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.1951185536
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.2919601165
Short name T785
Test name
Test status
Simulation time 20733684 ps
CPU time 0.93 seconds
Started Jul 06 06:26:57 PM PDT 24
Finished Jul 06 06:26:58 PM PDT 24
Peak memory 207404 kb
Host smart-3e25519f-37d3-4bb5-9d1c-78747333568d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919601165 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.2919601165
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.630836578
Short name T837
Test name
Test status
Simulation time 15251595 ps
CPU time 0.99 seconds
Started Jul 06 06:27:00 PM PDT 24
Finished Jul 06 06:27:02 PM PDT 24
Peak memory 215600 kb
Host smart-f26aff7c-189c-4c40-9263-c38b818ff695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630836578 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.630836578
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.3901322775
Short name T78
Test name
Test status
Simulation time 605104894 ps
CPU time 2.85 seconds
Started Jul 06 06:26:59 PM PDT 24
Finished Jul 06 06:27:02 PM PDT 24
Peak memory 220800 kb
Host smart-02e23b12-c9f2-4fb4-883f-501bb4458066
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901322775 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.3901322775
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.2883618271
Short name T807
Test name
Test status
Simulation time 63464294876 ps
CPU time 397.66 seconds
Started Jul 06 06:27:01 PM PDT 24
Finished Jul 06 06:33:39 PM PDT 24
Peak memory 218836 kb
Host smart-6e1706b6-5cf0-4e7e-aa26-652ba3668dc2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883618271 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.2883618271
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_alert.2988933981
Short name T556
Test name
Test status
Simulation time 26078240 ps
CPU time 1.23 seconds
Started Jul 06 06:28:10 PM PDT 24
Finished Jul 06 06:28:11 PM PDT 24
Peak memory 220172 kb
Host smart-ec9ac9a8-91d7-4c98-86ca-c827e6cc9bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988933981 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_alert.2988933981
Directory /workspace/50.edn_alert/latest

Test location /workspace/coverage/default/50.edn_err.1032283046
Short name T213
Test name
Test status
Simulation time 18746318 ps
CPU time 1 seconds
Started Jul 06 06:28:09 PM PDT 24
Finished Jul 06 06:28:11 PM PDT 24
Peak memory 218972 kb
Host smart-fd19d2c4-ecb1-4845-b375-4810c218aa2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032283046 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.1032283046
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.1448610157
Short name T699
Test name
Test status
Simulation time 77139022 ps
CPU time 1.54 seconds
Started Jul 06 06:28:15 PM PDT 24
Finished Jul 06 06:28:17 PM PDT 24
Peak memory 219032 kb
Host smart-730b2fb1-5e0d-4418-91cc-558397ff16a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448610157 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.1448610157
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_alert.825739895
Short name T8
Test name
Test status
Simulation time 93346543 ps
CPU time 1.25 seconds
Started Jul 06 06:28:13 PM PDT 24
Finished Jul 06 06:28:15 PM PDT 24
Peak memory 220080 kb
Host smart-7fb6beeb-6a6d-46e5-b37a-d406ad608503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825739895 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_alert.825739895
Directory /workspace/51.edn_alert/latest

Test location /workspace/coverage/default/51.edn_err.620158256
Short name T119
Test name
Test status
Simulation time 33883484 ps
CPU time 1.04 seconds
Started Jul 06 06:28:22 PM PDT 24
Finished Jul 06 06:28:23 PM PDT 24
Peak memory 229960 kb
Host smart-f56be2e8-0bf5-464e-8b4e-2baf98ecc157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620158256 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.620158256
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.334214254
Short name T975
Test name
Test status
Simulation time 43347545 ps
CPU time 1.67 seconds
Started Jul 06 06:28:22 PM PDT 24
Finished Jul 06 06:28:24 PM PDT 24
Peak memory 218680 kb
Host smart-3ad1ea13-123a-4b2a-9eb6-02193a426ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334214254 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.334214254
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_alert.81888917
Short name T549
Test name
Test status
Simulation time 42045601 ps
CPU time 1.13 seconds
Started Jul 06 06:28:22 PM PDT 24
Finished Jul 06 06:28:23 PM PDT 24
Peak memory 221428 kb
Host smart-b41bfb5a-dc73-4a2f-85fa-97dc1215eb90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81888917 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_alert.81888917
Directory /workspace/52.edn_alert/latest

Test location /workspace/coverage/default/52.edn_err.4005046087
Short name T67
Test name
Test status
Simulation time 42211649 ps
CPU time 1.3 seconds
Started Jul 06 06:28:22 PM PDT 24
Finished Jul 06 06:28:23 PM PDT 24
Peak memory 226024 kb
Host smart-84ea685e-d226-4557-9b1e-d75c72b70dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005046087 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.4005046087
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.4058748818
Short name T46
Test name
Test status
Simulation time 103282446 ps
CPU time 1.28 seconds
Started Jul 06 06:28:23 PM PDT 24
Finished Jul 06 06:28:25 PM PDT 24
Peak memory 219192 kb
Host smart-69a1512e-7bed-45c0-b833-3d7051d23be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058748818 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.4058748818
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_alert.3686951120
Short name T670
Test name
Test status
Simulation time 144420490 ps
CPU time 1.16 seconds
Started Jul 06 06:28:17 PM PDT 24
Finished Jul 06 06:28:19 PM PDT 24
Peak memory 215968 kb
Host smart-0696b53a-5f83-40a3-a440-74fea7cb3611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686951120 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_alert.3686951120
Directory /workspace/53.edn_alert/latest

Test location /workspace/coverage/default/53.edn_err.2633314134
Short name T977
Test name
Test status
Simulation time 26125965 ps
CPU time 1 seconds
Started Jul 06 06:28:16 PM PDT 24
Finished Jul 06 06:28:18 PM PDT 24
Peak memory 219624 kb
Host smart-9bfd61d4-5753-460b-a33a-15eca11cc23f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633314134 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.2633314134
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.1759797325
Short name T343
Test name
Test status
Simulation time 48629803 ps
CPU time 1.7 seconds
Started Jul 06 06:28:13 PM PDT 24
Finished Jul 06 06:28:15 PM PDT 24
Peak memory 218908 kb
Host smart-5d5d88ba-0524-49f1-8691-09253ce49875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759797325 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.1759797325
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_alert.303460893
Short name T715
Test name
Test status
Simulation time 73842717 ps
CPU time 1.12 seconds
Started Jul 06 06:28:14 PM PDT 24
Finished Jul 06 06:28:15 PM PDT 24
Peak memory 219824 kb
Host smart-313d9e4a-9fec-41bc-a942-ba6a443dabc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303460893 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_alert.303460893
Directory /workspace/54.edn_alert/latest

Test location /workspace/coverage/default/54.edn_err.323009192
Short name T581
Test name
Test status
Simulation time 18711665 ps
CPU time 1.04 seconds
Started Jul 06 06:28:14 PM PDT 24
Finished Jul 06 06:28:16 PM PDT 24
Peak memory 218864 kb
Host smart-7638819e-a227-4665-a638-1115d3abbe34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323009192 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.323009192
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.1126201538
Short name T824
Test name
Test status
Simulation time 30274154 ps
CPU time 1.29 seconds
Started Jul 06 06:28:16 PM PDT 24
Finished Jul 06 06:28:18 PM PDT 24
Peak memory 217412 kb
Host smart-7a4e2e3c-d268-419c-89e5-2251ab6cb8c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126201538 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.1126201538
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_alert.339496709
Short name T628
Test name
Test status
Simulation time 184598601 ps
CPU time 1.34 seconds
Started Jul 06 06:28:22 PM PDT 24
Finished Jul 06 06:28:24 PM PDT 24
Peak memory 218672 kb
Host smart-064759c2-47e8-4a23-9416-7d44e07a8c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339496709 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_alert.339496709
Directory /workspace/55.edn_alert/latest

Test location /workspace/coverage/default/55.edn_err.2079147697
Short name T841
Test name
Test status
Simulation time 49730880 ps
CPU time 1.03 seconds
Started Jul 06 06:28:16 PM PDT 24
Finished Jul 06 06:28:18 PM PDT 24
Peak memory 218732 kb
Host smart-7f783631-8c3c-4d67-808f-cf52e9de6c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079147697 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.2079147697
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.3916261092
Short name T311
Test name
Test status
Simulation time 43699008 ps
CPU time 1.38 seconds
Started Jul 06 06:28:21 PM PDT 24
Finished Jul 06 06:28:23 PM PDT 24
Peak memory 219244 kb
Host smart-466f7523-f78c-4597-9c82-f6017c888046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916261092 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.3916261092
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_alert.622794646
Short name T924
Test name
Test status
Simulation time 215574305 ps
CPU time 1.37 seconds
Started Jul 06 06:28:15 PM PDT 24
Finished Jul 06 06:28:17 PM PDT 24
Peak memory 220644 kb
Host smart-f33b840f-1245-429c-9edb-bc73f07f3b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622794646 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_alert.622794646
Directory /workspace/56.edn_alert/latest

Test location /workspace/coverage/default/56.edn_err.4079969440
Short name T373
Test name
Test status
Simulation time 23842483 ps
CPU time 1 seconds
Started Jul 06 06:28:22 PM PDT 24
Finished Jul 06 06:28:24 PM PDT 24
Peak memory 218784 kb
Host smart-3e4be320-72e9-488c-95f2-0ea940ffe24a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079969440 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.4079969440
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.3317538951
Short name T402
Test name
Test status
Simulation time 51786325 ps
CPU time 1.42 seconds
Started Jul 06 06:28:16 PM PDT 24
Finished Jul 06 06:28:18 PM PDT 24
Peak memory 219016 kb
Host smart-6987b6a6-86fb-412c-8500-2f1b1f338bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317538951 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.3317538951
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_alert.2958769100
Short name T138
Test name
Test status
Simulation time 23217419 ps
CPU time 1.19 seconds
Started Jul 06 06:28:20 PM PDT 24
Finished Jul 06 06:28:21 PM PDT 24
Peak memory 218880 kb
Host smart-70543671-7dc6-4628-9294-408a9c095351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958769100 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_alert.2958769100
Directory /workspace/57.edn_alert/latest

Test location /workspace/coverage/default/57.edn_err.3150570664
Short name T888
Test name
Test status
Simulation time 25787511 ps
CPU time 1.13 seconds
Started Jul 06 06:28:15 PM PDT 24
Finished Jul 06 06:28:16 PM PDT 24
Peak memory 219032 kb
Host smart-23db419e-e654-4bbe-9b4a-646676e07730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150570664 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.3150570664
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.1128232481
Short name T560
Test name
Test status
Simulation time 93606605 ps
CPU time 1.37 seconds
Started Jul 06 06:28:22 PM PDT 24
Finished Jul 06 06:28:24 PM PDT 24
Peak memory 218932 kb
Host smart-d63bdb31-935c-49d6-8b2b-a9b993ab62f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128232481 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.1128232481
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_alert.1620740442
Short name T468
Test name
Test status
Simulation time 39851136 ps
CPU time 1.17 seconds
Started Jul 06 06:28:15 PM PDT 24
Finished Jul 06 06:28:17 PM PDT 24
Peak memory 220152 kb
Host smart-9990bb73-7163-46c0-ba4e-ac939a34c107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620740442 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_alert.1620740442
Directory /workspace/58.edn_alert/latest

Test location /workspace/coverage/default/58.edn_err.480652362
Short name T163
Test name
Test status
Simulation time 21453424 ps
CPU time 0.97 seconds
Started Jul 06 06:28:17 PM PDT 24
Finished Jul 06 06:28:18 PM PDT 24
Peak memory 218684 kb
Host smart-c199b792-d53e-4073-ae22-0787481286e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480652362 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.480652362
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.1556756298
Short name T425
Test name
Test status
Simulation time 85628118 ps
CPU time 1.26 seconds
Started Jul 06 06:28:19 PM PDT 24
Finished Jul 06 06:28:21 PM PDT 24
Peak memory 215676 kb
Host smart-866d4af6-79dc-4a50-9e67-c70908e33ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556756298 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.1556756298
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_alert.3785196638
Short name T225
Test name
Test status
Simulation time 43684683 ps
CPU time 1.23 seconds
Started Jul 06 06:28:19 PM PDT 24
Finished Jul 06 06:28:20 PM PDT 24
Peak memory 218896 kb
Host smart-9d15def8-0752-4dac-8744-d29ab2ac1678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785196638 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_alert.3785196638
Directory /workspace/59.edn_alert/latest

Test location /workspace/coverage/default/59.edn_err.572422970
Short name T193
Test name
Test status
Simulation time 21336991 ps
CPU time 1.09 seconds
Started Jul 06 06:28:21 PM PDT 24
Finished Jul 06 06:28:22 PM PDT 24
Peak memory 219760 kb
Host smart-2b2be0b9-f532-4db0-bb5b-f0d3e0982af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572422970 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.572422970
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.970051921
Short name T396
Test name
Test status
Simulation time 38676593 ps
CPU time 1.42 seconds
Started Jul 06 06:28:14 PM PDT 24
Finished Jul 06 06:28:16 PM PDT 24
Peak memory 218868 kb
Host smart-a464eb20-949f-4f37-ba46-ee1bba434ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970051921 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.970051921
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert_test.2022308499
Short name T905
Test name
Test status
Simulation time 46738779 ps
CPU time 0.84 seconds
Started Jul 06 06:27:02 PM PDT 24
Finished Jul 06 06:27:04 PM PDT 24
Peak memory 206804 kb
Host smart-c8befaf1-1c4a-48a1-a41b-f04bd3347a3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022308499 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.2022308499
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.184124584
Short name T706
Test name
Test status
Simulation time 10105933 ps
CPU time 0.87 seconds
Started Jul 06 06:27:04 PM PDT 24
Finished Jul 06 06:27:05 PM PDT 24
Peak memory 216676 kb
Host smart-b16107ba-08f3-431a-a367-076bd5b0c59f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184124584 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.184124584
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.2220699848
Short name T881
Test name
Test status
Simulation time 26263580 ps
CPU time 1.11 seconds
Started Jul 06 06:27:03 PM PDT 24
Finished Jul 06 06:27:05 PM PDT 24
Peak memory 218920 kb
Host smart-2427a2bd-7e86-4758-8b1b-6649ad07a15b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220699848 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.2220699848
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.67737478
Short name T120
Test name
Test status
Simulation time 106083537 ps
CPU time 1 seconds
Started Jul 06 06:27:03 PM PDT 24
Finished Jul 06 06:27:05 PM PDT 24
Peak memory 219716 kb
Host smart-f3b2fb63-94c9-4412-920f-babfefafab09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67737478 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.67737478
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.3591440676
Short name T997
Test name
Test status
Simulation time 58132255 ps
CPU time 1.02 seconds
Started Jul 06 06:27:00 PM PDT 24
Finished Jul 06 06:27:02 PM PDT 24
Peak memory 217684 kb
Host smart-7a7a2672-3b90-4c8e-bdac-9b90932b28d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591440676 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.3591440676
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.3031959305
Short name T763
Test name
Test status
Simulation time 26942704 ps
CPU time 0.92 seconds
Started Jul 06 06:27:01 PM PDT 24
Finished Jul 06 06:27:02 PM PDT 24
Peak memory 216228 kb
Host smart-3d2e7a87-31e3-40a1-bd15-c03d8ac36a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031959305 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.3031959305
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.342259746
Short name T33
Test name
Test status
Simulation time 47933298 ps
CPU time 0.9 seconds
Started Jul 06 06:27:00 PM PDT 24
Finished Jul 06 06:27:02 PM PDT 24
Peak memory 207444 kb
Host smart-207cce45-8ae2-4cf4-9604-cb42b4e0ff40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342259746 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.342259746
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.515350202
Short name T710
Test name
Test status
Simulation time 102626628 ps
CPU time 0.87 seconds
Started Jul 06 06:27:01 PM PDT 24
Finished Jul 06 06:27:03 PM PDT 24
Peak memory 215648 kb
Host smart-f03f3437-c0c8-4838-9218-ec3f6357a089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515350202 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.515350202
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.4211702788
Short name T976
Test name
Test status
Simulation time 224578824 ps
CPU time 4.53 seconds
Started Jul 06 06:27:01 PM PDT 24
Finished Jul 06 06:27:06 PM PDT 24
Peak memory 215640 kb
Host smart-04d744a2-fd8d-4489-abcd-35218cfc5621
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211702788 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.4211702788
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.614420521
Short name T753
Test name
Test status
Simulation time 272851430199 ps
CPU time 2334.38 seconds
Started Jul 06 06:27:02 PM PDT 24
Finished Jul 06 07:05:57 PM PDT 24
Peak memory 236060 kb
Host smart-2495d26c-0834-4452-b8bf-72b58bb5299f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614420521 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.614420521
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_alert.1765878889
Short name T156
Test name
Test status
Simulation time 49379427 ps
CPU time 1.34 seconds
Started Jul 06 06:28:22 PM PDT 24
Finished Jul 06 06:28:23 PM PDT 24
Peak memory 218952 kb
Host smart-cb95a98f-2ea3-46ac-b9aa-ab0970b71a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765878889 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_alert.1765878889
Directory /workspace/60.edn_alert/latest

Test location /workspace/coverage/default/60.edn_err.1655265357
Short name T514
Test name
Test status
Simulation time 19349556 ps
CPU time 1.07 seconds
Started Jul 06 06:28:15 PM PDT 24
Finished Jul 06 06:28:17 PM PDT 24
Peak memory 218964 kb
Host smart-1e50b258-e313-495a-aae2-fec8d59fbb2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655265357 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.1655265357
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.2673551427
Short name T648
Test name
Test status
Simulation time 50614070 ps
CPU time 1.61 seconds
Started Jul 06 06:28:16 PM PDT 24
Finished Jul 06 06:28:18 PM PDT 24
Peak memory 218704 kb
Host smart-4eeea4f1-cda2-441a-afed-608d25687b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673551427 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.2673551427
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_alert.1362362953
Short name T290
Test name
Test status
Simulation time 97141102 ps
CPU time 1.21 seconds
Started Jul 06 06:28:20 PM PDT 24
Finished Jul 06 06:28:22 PM PDT 24
Peak memory 221116 kb
Host smart-180ac3a3-2e8c-4e12-9db1-deb15d5e6a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362362953 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_alert.1362362953
Directory /workspace/61.edn_alert/latest

Test location /workspace/coverage/default/61.edn_err.1192880726
Short name T391
Test name
Test status
Simulation time 28088509 ps
CPU time 1.25 seconds
Started Jul 06 06:28:19 PM PDT 24
Finished Jul 06 06:28:20 PM PDT 24
Peak memory 220160 kb
Host smart-09859438-1a94-4a2d-9916-f24b52f69397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192880726 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.1192880726
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.4207279979
Short name T861
Test name
Test status
Simulation time 59919097 ps
CPU time 1.53 seconds
Started Jul 06 06:28:22 PM PDT 24
Finished Jul 06 06:28:24 PM PDT 24
Peak memory 217656 kb
Host smart-3ac54226-8c1c-410e-a116-d8e89879b01e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207279979 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.4207279979
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_alert.2559682991
Short name T182
Test name
Test status
Simulation time 58690621 ps
CPU time 1.31 seconds
Started Jul 06 06:28:18 PM PDT 24
Finished Jul 06 06:28:20 PM PDT 24
Peak memory 216052 kb
Host smart-49e76782-7e1e-4b5c-8854-1561d417edca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559682991 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_alert.2559682991
Directory /workspace/62.edn_alert/latest

Test location /workspace/coverage/default/62.edn_err.3488494253
Short name T175
Test name
Test status
Simulation time 18610151 ps
CPU time 1.13 seconds
Started Jul 06 06:28:17 PM PDT 24
Finished Jul 06 06:28:18 PM PDT 24
Peak memory 224248 kb
Host smart-d5784b36-d137-4927-b33d-480b097b1446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488494253 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.3488494253
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.1575846307
Short name T454
Test name
Test status
Simulation time 62846634 ps
CPU time 1.81 seconds
Started Jul 06 06:28:19 PM PDT 24
Finished Jul 06 06:28:21 PM PDT 24
Peak memory 219056 kb
Host smart-11fdd7fd-3e06-427e-96e6-0a416edcb443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575846307 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.1575846307
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_alert.3534286194
Short name T638
Test name
Test status
Simulation time 43068713 ps
CPU time 1.18 seconds
Started Jul 06 06:28:19 PM PDT 24
Finished Jul 06 06:28:21 PM PDT 24
Peak memory 219356 kb
Host smart-22282664-7a27-45ed-a474-811edcc435f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534286194 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_alert.3534286194
Directory /workspace/63.edn_alert/latest

Test location /workspace/coverage/default/63.edn_err.2431847987
Short name T115
Test name
Test status
Simulation time 25749967 ps
CPU time 1.21 seconds
Started Jul 06 06:28:18 PM PDT 24
Finished Jul 06 06:28:20 PM PDT 24
Peak memory 220936 kb
Host smart-d8bd4a12-c72e-4854-8edf-4956dbf834ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431847987 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.2431847987
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.2478712851
Short name T323
Test name
Test status
Simulation time 134193699 ps
CPU time 1.57 seconds
Started Jul 06 06:28:17 PM PDT 24
Finished Jul 06 06:28:19 PM PDT 24
Peak memory 219252 kb
Host smart-f030a5be-c600-4eab-9678-0bf8e272a921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478712851 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.2478712851
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_alert.545753533
Short name T704
Test name
Test status
Simulation time 25468109 ps
CPU time 1.21 seconds
Started Jul 06 06:28:22 PM PDT 24
Finished Jul 06 06:28:24 PM PDT 24
Peak memory 220088 kb
Host smart-4714a4e7-9225-40a0-a059-357696c47187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545753533 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_alert.545753533
Directory /workspace/64.edn_alert/latest

Test location /workspace/coverage/default/64.edn_err.3944926069
Short name T737
Test name
Test status
Simulation time 37657065 ps
CPU time 0.89 seconds
Started Jul 06 06:28:20 PM PDT 24
Finished Jul 06 06:28:22 PM PDT 24
Peak memory 215636 kb
Host smart-07c0dc4b-542a-4e7b-b735-e3c059ea35f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944926069 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.3944926069
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.1853523778
Short name T892
Test name
Test status
Simulation time 44757081 ps
CPU time 1.52 seconds
Started Jul 06 06:28:19 PM PDT 24
Finished Jul 06 06:28:21 PM PDT 24
Peak memory 217852 kb
Host smart-790c0f01-1210-49b6-89f7-08bfb2c21e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853523778 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.1853523778
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_err.4142874757
Short name T707
Test name
Test status
Simulation time 80827576 ps
CPU time 1.07 seconds
Started Jul 06 06:28:16 PM PDT 24
Finished Jul 06 06:28:18 PM PDT 24
Peak memory 219800 kb
Host smart-c5473c61-60ee-4973-8c10-9e652311282c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142874757 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.4142874757
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.2937533353
Short name T784
Test name
Test status
Simulation time 46350167 ps
CPU time 1.18 seconds
Started Jul 06 06:28:18 PM PDT 24
Finished Jul 06 06:28:19 PM PDT 24
Peak memory 217864 kb
Host smart-17c54a98-89e4-4788-a8e8-f06777cd9ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937533353 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.2937533353
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_alert.2976570386
Short name T295
Test name
Test status
Simulation time 34239499 ps
CPU time 1.22 seconds
Started Jul 06 06:28:20 PM PDT 24
Finished Jul 06 06:28:22 PM PDT 24
Peak memory 219880 kb
Host smart-f9b15993-d095-46bc-bcb8-d1f30c505b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976570386 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_alert.2976570386
Directory /workspace/66.edn_alert/latest

Test location /workspace/coverage/default/66.edn_err.3465150046
Short name T967
Test name
Test status
Simulation time 22631824 ps
CPU time 0.93 seconds
Started Jul 06 06:28:18 PM PDT 24
Finished Jul 06 06:28:19 PM PDT 24
Peak memory 218996 kb
Host smart-4eba73a1-5413-489b-9def-aee29933985e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465150046 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.3465150046
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.2788212098
Short name T370
Test name
Test status
Simulation time 44178264 ps
CPU time 1.44 seconds
Started Jul 06 06:28:18 PM PDT 24
Finished Jul 06 06:28:20 PM PDT 24
Peak memory 219004 kb
Host smart-886c882c-22fe-4fd1-991d-cd10a967e59f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788212098 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.2788212098
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_alert.2232512842
Short name T162
Test name
Test status
Simulation time 69123043 ps
CPU time 1.07 seconds
Started Jul 06 06:28:23 PM PDT 24
Finished Jul 06 06:28:24 PM PDT 24
Peak memory 219380 kb
Host smart-34550ca9-0c4b-4838-9fca-81e9388a5a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232512842 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_alert.2232512842
Directory /workspace/67.edn_alert/latest

Test location /workspace/coverage/default/67.edn_err.1694838687
Short name T798
Test name
Test status
Simulation time 30006309 ps
CPU time 1.2 seconds
Started Jul 06 06:28:22 PM PDT 24
Finished Jul 06 06:28:24 PM PDT 24
Peak memory 219992 kb
Host smart-0483b62f-15d8-42f2-9728-b21df5e7f186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694838687 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.1694838687
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.3396915520
Short name T50
Test name
Test status
Simulation time 72764102 ps
CPU time 1.3 seconds
Started Jul 06 06:28:16 PM PDT 24
Finished Jul 06 06:28:18 PM PDT 24
Peak memory 217676 kb
Host smart-691223ac-87b8-4569-9fda-8c9eb1e694f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396915520 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.3396915520
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_alert.498206247
Short name T902
Test name
Test status
Simulation time 25987138 ps
CPU time 1.28 seconds
Started Jul 06 06:28:37 PM PDT 24
Finished Jul 06 06:28:38 PM PDT 24
Peak memory 220136 kb
Host smart-f2c2d686-6d49-48fe-96a0-9dd7bfd3a399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498206247 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_alert.498206247
Directory /workspace/68.edn_alert/latest

Test location /workspace/coverage/default/68.edn_err.813266814
Short name T400
Test name
Test status
Simulation time 22662896 ps
CPU time 0.94 seconds
Started Jul 06 06:28:26 PM PDT 24
Finished Jul 06 06:28:28 PM PDT 24
Peak memory 219004 kb
Host smart-6a44c17c-0a87-49e8-b4f1-3a446e0a30d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813266814 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.813266814
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.1771010394
Short name T574
Test name
Test status
Simulation time 34787916 ps
CPU time 1.45 seconds
Started Jul 06 06:28:26 PM PDT 24
Finished Jul 06 06:28:28 PM PDT 24
Peak memory 220280 kb
Host smart-4f47026e-447b-43ed-b091-a659f979905c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771010394 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.1771010394
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_alert.282617753
Short name T94
Test name
Test status
Simulation time 90288180 ps
CPU time 1.35 seconds
Started Jul 06 06:28:37 PM PDT 24
Finished Jul 06 06:28:39 PM PDT 24
Peak memory 218884 kb
Host smart-9730af4a-f1aa-47e4-b946-80d1606b52cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282617753 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_alert.282617753
Directory /workspace/69.edn_alert/latest

Test location /workspace/coverage/default/69.edn_err.3821317807
Short name T692
Test name
Test status
Simulation time 62389920 ps
CPU time 1.2 seconds
Started Jul 06 06:28:26 PM PDT 24
Finished Jul 06 06:28:27 PM PDT 24
Peak memory 225720 kb
Host smart-98fb4e0e-cad2-4874-a964-d7a16f2c219e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821317807 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.3821317807
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.739456723
Short name T978
Test name
Test status
Simulation time 85430427 ps
CPU time 1.38 seconds
Started Jul 06 06:28:24 PM PDT 24
Finished Jul 06 06:28:25 PM PDT 24
Peak memory 215764 kb
Host smart-58f662d8-64a7-4b8e-8209-c73eb1e305e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739456723 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.739456723
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.3970592323
Short name T567
Test name
Test status
Simulation time 50941668 ps
CPU time 1.17 seconds
Started Jul 06 06:27:12 PM PDT 24
Finished Jul 06 06:27:13 PM PDT 24
Peak memory 218816 kb
Host smart-918d2ea4-1daa-4cde-a899-05e1c5bce3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970592323 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.3970592323
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.3746957866
Short name T361
Test name
Test status
Simulation time 31228337 ps
CPU time 0.93 seconds
Started Jul 06 06:27:00 PM PDT 24
Finished Jul 06 06:27:01 PM PDT 24
Peak memory 215264 kb
Host smart-a8c6a6c7-62eb-4497-b45d-f81fc3b3b731
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746957866 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.3746957866
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.868738439
Short name T651
Test name
Test status
Simulation time 114859406 ps
CPU time 1.19 seconds
Started Jul 06 06:27:01 PM PDT 24
Finished Jul 06 06:27:03 PM PDT 24
Peak memory 217260 kb
Host smart-b2d5ec77-96a8-476f-94d0-717f0cbf87e2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868738439 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_dis
able_auto_req_mode.868738439
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_genbits.1617208148
Short name T912
Test name
Test status
Simulation time 22974972 ps
CPU time 1.21 seconds
Started Jul 06 06:27:02 PM PDT 24
Finished Jul 06 06:27:04 PM PDT 24
Peak memory 220124 kb
Host smart-25d2ce85-1671-4cad-a207-cdc25f6b6097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617208148 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.1617208148
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.3592200512
Short name T928
Test name
Test status
Simulation time 26635761 ps
CPU time 0.97 seconds
Started Jul 06 06:27:02 PM PDT 24
Finished Jul 06 06:27:04 PM PDT 24
Peak memory 215996 kb
Host smart-d1a96970-7881-4362-91a9-a3b90617b10a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592200512 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.3592200512
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.2989704425
Short name T32
Test name
Test status
Simulation time 21273383 ps
CPU time 1.01 seconds
Started Jul 06 06:27:03 PM PDT 24
Finished Jul 06 06:27:04 PM PDT 24
Peak memory 207420 kb
Host smart-eadb2a14-0ac7-4da4-9bfa-204416fe9e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989704425 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.2989704425
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.1529520030
Short name T643
Test name
Test status
Simulation time 18909386 ps
CPU time 1.04 seconds
Started Jul 06 06:27:01 PM PDT 24
Finished Jul 06 06:27:03 PM PDT 24
Peak memory 207460 kb
Host smart-50e51eff-a877-4698-bbe4-6b8840661701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529520030 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.1529520030
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.924282913
Short name T982
Test name
Test status
Simulation time 1528348453 ps
CPU time 4.99 seconds
Started Jul 06 06:27:11 PM PDT 24
Finished Jul 06 06:27:16 PM PDT 24
Peak memory 217320 kb
Host smart-a3318e7f-f279-4581-b5bb-cadaece90a25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924282913 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.924282913
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.2555209514
Short name T447
Test name
Test status
Simulation time 35882954629 ps
CPU time 455.34 seconds
Started Jul 06 06:27:11 PM PDT 24
Finished Jul 06 06:34:47 PM PDT 24
Peak memory 217508 kb
Host smart-b8cd66f4-7bae-467e-b0d9-e203840c72cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555209514 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.2555209514
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_alert.740429302
Short name T259
Test name
Test status
Simulation time 31601728 ps
CPU time 1.33 seconds
Started Jul 06 06:28:22 PM PDT 24
Finished Jul 06 06:28:24 PM PDT 24
Peak memory 216008 kb
Host smart-2846a570-23b6-475b-aef4-ab2ffb1fcce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740429302 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_alert.740429302
Directory /workspace/70.edn_alert/latest

Test location /workspace/coverage/default/70.edn_err.978171184
Short name T839
Test name
Test status
Simulation time 48142370 ps
CPU time 1.01 seconds
Started Jul 06 06:28:28 PM PDT 24
Finished Jul 06 06:28:29 PM PDT 24
Peak memory 218856 kb
Host smart-94f4363e-9318-480f-be29-b67c5b8c40b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978171184 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.978171184
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.2765113915
Short name T728
Test name
Test status
Simulation time 47292772 ps
CPU time 1.73 seconds
Started Jul 06 06:28:27 PM PDT 24
Finished Jul 06 06:28:29 PM PDT 24
Peak memory 220516 kb
Host smart-79dbdeb5-911b-49e1-892c-f0cf1c27c988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765113915 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.2765113915
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_alert.1940410070
Short name T600
Test name
Test status
Simulation time 31596471 ps
CPU time 1.26 seconds
Started Jul 06 06:28:22 PM PDT 24
Finished Jul 06 06:28:24 PM PDT 24
Peak memory 220100 kb
Host smart-db699e15-0519-430c-9b4c-143759f1d1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940410070 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_alert.1940410070
Directory /workspace/71.edn_alert/latest

Test location /workspace/coverage/default/71.edn_err.2617721660
Short name T198
Test name
Test status
Simulation time 42849778 ps
CPU time 0.98 seconds
Started Jul 06 06:28:24 PM PDT 24
Finished Jul 06 06:28:25 PM PDT 24
Peak memory 219060 kb
Host smart-1cef6255-1088-45ff-b0a5-acaf925ad3c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617721660 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.2617721660
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.2828130394
Short name T969
Test name
Test status
Simulation time 396733988 ps
CPU time 4.46 seconds
Started Jul 06 06:28:22 PM PDT 24
Finished Jul 06 06:28:27 PM PDT 24
Peak memory 215676 kb
Host smart-35daaacf-4b61-4030-8ffb-d4bd257d84a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828130394 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.2828130394
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_alert.1047101043
Short name T469
Test name
Test status
Simulation time 39119527 ps
CPU time 1.23 seconds
Started Jul 06 06:28:30 PM PDT 24
Finished Jul 06 06:28:31 PM PDT 24
Peak memory 220808 kb
Host smart-793dc11b-93e1-47e5-b172-44f4ffa8dde4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047101043 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_alert.1047101043
Directory /workspace/72.edn_alert/latest

Test location /workspace/coverage/default/72.edn_err.3109942166
Short name T815
Test name
Test status
Simulation time 123423629 ps
CPU time 1.1 seconds
Started Jul 06 06:28:25 PM PDT 24
Finished Jul 06 06:28:26 PM PDT 24
Peak memory 219904 kb
Host smart-499284a6-2d4b-4c4b-a84c-39e9d537538d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109942166 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.3109942166
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.205354286
Short name T61
Test name
Test status
Simulation time 84822761 ps
CPU time 2.95 seconds
Started Jul 06 06:28:28 PM PDT 24
Finished Jul 06 06:28:32 PM PDT 24
Peak memory 219276 kb
Host smart-8bf50f85-b5b4-4601-bc47-2502816a5bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205354286 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.205354286
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_alert.794991660
Short name T260
Test name
Test status
Simulation time 45754235 ps
CPU time 1.21 seconds
Started Jul 06 06:28:33 PM PDT 24
Finished Jul 06 06:28:35 PM PDT 24
Peak memory 219484 kb
Host smart-4d2de5d6-4880-4580-ae9f-5fb2948329e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794991660 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_alert.794991660
Directory /workspace/73.edn_alert/latest

Test location /workspace/coverage/default/73.edn_err.667736352
Short name T146
Test name
Test status
Simulation time 56113661 ps
CPU time 1.15 seconds
Started Jul 06 06:28:25 PM PDT 24
Finished Jul 06 06:28:26 PM PDT 24
Peak memory 220884 kb
Host smart-0e54115c-3455-4555-97f9-0740ab100378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667736352 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.667736352
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.3294411385
Short name T550
Test name
Test status
Simulation time 24854346 ps
CPU time 1.2 seconds
Started Jul 06 06:28:32 PM PDT 24
Finished Jul 06 06:28:34 PM PDT 24
Peak memory 219020 kb
Host smart-21dcab68-7b11-4f34-b1f9-4fbf3da0ed2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294411385 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.3294411385
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_alert.13848009
Short name T666
Test name
Test status
Simulation time 21340675 ps
CPU time 1.11 seconds
Started Jul 06 06:28:27 PM PDT 24
Finished Jul 06 06:28:28 PM PDT 24
Peak memory 220100 kb
Host smart-11cf1421-44fe-422e-8343-68b29146e993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13848009 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_alert.13848009
Directory /workspace/74.edn_alert/latest

Test location /workspace/coverage/default/74.edn_err.3680577909
Short name T145
Test name
Test status
Simulation time 46147544 ps
CPU time 1.21 seconds
Started Jul 06 06:28:32 PM PDT 24
Finished Jul 06 06:28:34 PM PDT 24
Peak memory 230148 kb
Host smart-69d08417-8123-4e07-a289-a24ff7a8c0d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680577909 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.3680577909
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.1015501459
Short name T675
Test name
Test status
Simulation time 72456254 ps
CPU time 1.12 seconds
Started Jul 06 06:28:31 PM PDT 24
Finished Jul 06 06:28:32 PM PDT 24
Peak memory 217692 kb
Host smart-cb7e9d23-286a-4912-9616-39d821590c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015501459 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.1015501459
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_alert.1922817408
Short name T173
Test name
Test status
Simulation time 28607399 ps
CPU time 1.25 seconds
Started Jul 06 06:28:27 PM PDT 24
Finished Jul 06 06:28:29 PM PDT 24
Peak memory 216036 kb
Host smart-3e3a3fd2-fdce-4b6d-92ab-9311a1ab3e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922817408 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_alert.1922817408
Directory /workspace/75.edn_alert/latest

Test location /workspace/coverage/default/75.edn_err.3186709038
Short name T134
Test name
Test status
Simulation time 41573407 ps
CPU time 1.11 seconds
Started Jul 06 06:28:30 PM PDT 24
Finished Jul 06 06:28:32 PM PDT 24
Peak memory 217640 kb
Host smart-1922c5cd-1c6c-4309-81db-572817956bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186709038 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.3186709038
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.3715606703
Short name T389
Test name
Test status
Simulation time 33476508 ps
CPU time 1.09 seconds
Started Jul 06 06:28:27 PM PDT 24
Finished Jul 06 06:28:28 PM PDT 24
Peak memory 217624 kb
Host smart-644da78b-0cab-4743-995d-73bd3f27a097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715606703 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.3715606703
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_alert.834963657
Short name T938
Test name
Test status
Simulation time 29014068 ps
CPU time 1.35 seconds
Started Jul 06 06:28:30 PM PDT 24
Finished Jul 06 06:28:32 PM PDT 24
Peak memory 218980 kb
Host smart-1f8c1268-73da-41a7-b639-f4ad703132df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834963657 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_alert.834963657
Directory /workspace/76.edn_alert/latest

Test location /workspace/coverage/default/76.edn_err.3617733977
Short name T844
Test name
Test status
Simulation time 52563548 ps
CPU time 1.01 seconds
Started Jul 06 06:28:26 PM PDT 24
Finished Jul 06 06:28:28 PM PDT 24
Peak memory 218900 kb
Host smart-ef73be4f-4a81-4c9d-990a-a70ada31adf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617733977 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.3617733977
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/77.edn_err.1410918940
Short name T153
Test name
Test status
Simulation time 34464585 ps
CPU time 1.05 seconds
Started Jul 06 06:28:26 PM PDT 24
Finished Jul 06 06:28:27 PM PDT 24
Peak memory 230000 kb
Host smart-b47cac98-6b63-4b8c-974e-c62ba2974812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410918940 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.1410918940
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.1228293739
Short name T682
Test name
Test status
Simulation time 23094693 ps
CPU time 1.15 seconds
Started Jul 06 06:28:30 PM PDT 24
Finished Jul 06 06:28:32 PM PDT 24
Peak memory 218812 kb
Host smart-94705258-480f-4122-8143-a615ab1cfbd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228293739 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.1228293739
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_alert.157666283
Short name T418
Test name
Test status
Simulation time 69006235 ps
CPU time 1.06 seconds
Started Jul 06 06:28:30 PM PDT 24
Finished Jul 06 06:28:32 PM PDT 24
Peak memory 219008 kb
Host smart-db03c234-85ea-4a21-bd88-7e5933c8bddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157666283 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_alert.157666283
Directory /workspace/78.edn_alert/latest

Test location /workspace/coverage/default/78.edn_err.658185376
Short name T811
Test name
Test status
Simulation time 29735053 ps
CPU time 1.3 seconds
Started Jul 06 06:28:27 PM PDT 24
Finished Jul 06 06:28:29 PM PDT 24
Peak memory 219952 kb
Host smart-f137d7d3-657d-4832-97df-5a855b9e477e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658185376 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.658185376
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/79.edn_alert.2274634423
Short name T906
Test name
Test status
Simulation time 27226242 ps
CPU time 1.23 seconds
Started Jul 06 06:28:33 PM PDT 24
Finished Jul 06 06:28:34 PM PDT 24
Peak memory 219080 kb
Host smart-e0996a79-28c1-44d6-91ba-78c71ee77ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274634423 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_alert.2274634423
Directory /workspace/79.edn_alert/latest

Test location /workspace/coverage/default/79.edn_err.3606967865
Short name T215
Test name
Test status
Simulation time 19036933 ps
CPU time 1.05 seconds
Started Jul 06 06:28:27 PM PDT 24
Finished Jul 06 06:28:29 PM PDT 24
Peak memory 218820 kb
Host smart-deeb4aeb-dc14-413c-a54f-e00aa3b82923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606967865 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.3606967865
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.2022134663
Short name T470
Test name
Test status
Simulation time 110129302 ps
CPU time 1.42 seconds
Started Jul 06 06:28:35 PM PDT 24
Finished Jul 06 06:28:37 PM PDT 24
Peak memory 217824 kb
Host smart-13b7364b-fa39-4440-938e-1d49eb5a9aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022134663 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.2022134663
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.3550818285
Short name T257
Test name
Test status
Simulation time 82123836 ps
CPU time 1.18 seconds
Started Jul 06 06:27:02 PM PDT 24
Finished Jul 06 06:27:04 PM PDT 24
Peak memory 220036 kb
Host smart-a528321e-81a6-41d3-a23a-e2c36819df51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550818285 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.3550818285
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.2852507416
Short name T981
Test name
Test status
Simulation time 30993875 ps
CPU time 0.82 seconds
Started Jul 06 06:27:09 PM PDT 24
Finished Jul 06 06:27:11 PM PDT 24
Peak memory 206712 kb
Host smart-4ea3fb02-ee91-462b-9c5c-6d104d16ed80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852507416 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.2852507416
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.3138673180
Short name T960
Test name
Test status
Simulation time 12997016 ps
CPU time 0.93 seconds
Started Jul 06 06:27:05 PM PDT 24
Finished Jul 06 06:27:06 PM PDT 24
Peak memory 216840 kb
Host smart-7fb2d8a7-6ec1-430d-94ae-073e756e98dc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138673180 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.3138673180
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.2126830511
Short name T420
Test name
Test status
Simulation time 41291776 ps
CPU time 1.37 seconds
Started Jul 06 06:27:05 PM PDT 24
Finished Jul 06 06:27:07 PM PDT 24
Peak memory 217324 kb
Host smart-f08f0515-cc7b-4cd4-ac77-a99c4e0af775
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126830511 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.2126830511
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.4071891030
Short name T988
Test name
Test status
Simulation time 19481465 ps
CPU time 1.14 seconds
Started Jul 06 06:27:06 PM PDT 24
Finished Jul 06 06:27:08 PM PDT 24
Peak memory 219996 kb
Host smart-35775455-26c3-4512-88e5-41e820836b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071891030 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.4071891030
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.3483631543
Short name T987
Test name
Test status
Simulation time 57496363 ps
CPU time 1.54 seconds
Started Jul 06 06:27:01 PM PDT 24
Finished Jul 06 06:27:04 PM PDT 24
Peak memory 220556 kb
Host smart-00ea6f9f-14a0-4812-b80f-09bad804394d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483631543 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.3483631543
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.25868023
Short name T109
Test name
Test status
Simulation time 36344688 ps
CPU time 0.92 seconds
Started Jul 06 06:27:01 PM PDT 24
Finished Jul 06 06:27:03 PM PDT 24
Peak memory 216040 kb
Host smart-1a4572e7-8ac3-424a-b406-854a32b52858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25868023 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.25868023
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.2321152113
Short name T250
Test name
Test status
Simulation time 17369279 ps
CPU time 0.97 seconds
Started Jul 06 06:27:03 PM PDT 24
Finished Jul 06 06:27:05 PM PDT 24
Peak memory 207392 kb
Host smart-bf157ce4-668e-4e63-8725-f0523fc29967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321152113 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.2321152113
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.4063168379
Short name T394
Test name
Test status
Simulation time 37786171 ps
CPU time 0.94 seconds
Started Jul 06 06:27:01 PM PDT 24
Finished Jul 06 06:27:03 PM PDT 24
Peak memory 215628 kb
Host smart-7dbf31f1-79c8-4317-bd63-b4c4410dc486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063168379 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.4063168379
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.3605660751
Short name T994
Test name
Test status
Simulation time 348153267 ps
CPU time 3.53 seconds
Started Jul 06 06:27:11 PM PDT 24
Finished Jul 06 06:27:15 PM PDT 24
Peak memory 220120 kb
Host smart-c1652d18-2535-4da3-ae0c-043576fcae5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605660751 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.3605660751
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.112584746
Short name T4
Test name
Test status
Simulation time 28081014151 ps
CPU time 700.66 seconds
Started Jul 06 06:27:04 PM PDT 24
Finished Jul 06 06:38:45 PM PDT 24
Peak memory 218756 kb
Host smart-a65a6842-b8d2-4dfc-838d-e2f2fc9d4388
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112584746 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.112584746
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_alert.2408633313
Short name T742
Test name
Test status
Simulation time 29822145 ps
CPU time 1.35 seconds
Started Jul 06 06:28:32 PM PDT 24
Finished Jul 06 06:28:34 PM PDT 24
Peak memory 215976 kb
Host smart-0d6c15c1-db43-4c71-8b2b-3f4a1f494bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408633313 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_alert.2408633313
Directory /workspace/80.edn_alert/latest

Test location /workspace/coverage/default/80.edn_err.3372947307
Short name T877
Test name
Test status
Simulation time 20116688 ps
CPU time 1.09 seconds
Started Jul 06 06:28:32 PM PDT 24
Finished Jul 06 06:28:34 PM PDT 24
Peak memory 219020 kb
Host smart-ac9b70cc-6825-4c45-bf90-abbe36f15623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372947307 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.3372947307
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.1509319307
Short name T771
Test name
Test status
Simulation time 130459655 ps
CPU time 1.12 seconds
Started Jul 06 06:28:35 PM PDT 24
Finished Jul 06 06:28:36 PM PDT 24
Peak memory 220320 kb
Host smart-9da4972e-2ef7-468a-9e1c-633725b6c1ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509319307 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.1509319307
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_genbits.1479703422
Short name T535
Test name
Test status
Simulation time 81487629 ps
CPU time 1.08 seconds
Started Jul 06 06:28:35 PM PDT 24
Finished Jul 06 06:28:36 PM PDT 24
Peak memory 217740 kb
Host smart-e2406286-135d-4f51-a09f-004f5edc7936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479703422 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.1479703422
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_alert.1705015303
Short name T81
Test name
Test status
Simulation time 104699626 ps
CPU time 1.13 seconds
Started Jul 06 06:28:32 PM PDT 24
Finished Jul 06 06:28:34 PM PDT 24
Peak memory 220536 kb
Host smart-d9d1e600-c8d1-48a2-b8c9-5ae72bed5e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705015303 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_alert.1705015303
Directory /workspace/82.edn_alert/latest

Test location /workspace/coverage/default/82.edn_err.4108726536
Short name T132
Test name
Test status
Simulation time 26898501 ps
CPU time 1.3 seconds
Started Jul 06 06:28:32 PM PDT 24
Finished Jul 06 06:28:33 PM PDT 24
Peak memory 229860 kb
Host smart-7dea5988-5b1a-4fb6-b93c-810efd46a259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108726536 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.4108726536
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.2773520859
Short name T664
Test name
Test status
Simulation time 48145384 ps
CPU time 1.33 seconds
Started Jul 06 06:28:38 PM PDT 24
Finished Jul 06 06:28:40 PM PDT 24
Peak memory 217584 kb
Host smart-083fa4d2-6e21-4540-a168-42362639ea76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773520859 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.2773520859
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_alert.1120255391
Short name T315
Test name
Test status
Simulation time 210501390 ps
CPU time 1.28 seconds
Started Jul 06 06:28:30 PM PDT 24
Finished Jul 06 06:28:32 PM PDT 24
Peak memory 218828 kb
Host smart-f8b80ff6-bd0a-46a3-a91e-f976fcd24221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120255391 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_alert.1120255391
Directory /workspace/83.edn_alert/latest

Test location /workspace/coverage/default/83.edn_err.1765141417
Short name T171
Test name
Test status
Simulation time 36173687 ps
CPU time 0.96 seconds
Started Jul 06 06:28:35 PM PDT 24
Finished Jul 06 06:28:37 PM PDT 24
Peak memory 224136 kb
Host smart-04dbd41d-6ee5-41cb-8a33-283784f09a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765141417 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.1765141417
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.3728187760
Short name T731
Test name
Test status
Simulation time 73003136 ps
CPU time 1.31 seconds
Started Jul 06 06:28:32 PM PDT 24
Finished Jul 06 06:28:34 PM PDT 24
Peak memory 215620 kb
Host smart-1758a062-51bc-4fe1-baef-b1c4c5ce13ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728187760 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.3728187760
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_alert.2117932410
Short name T286
Test name
Test status
Simulation time 134240473 ps
CPU time 1.13 seconds
Started Jul 06 06:28:31 PM PDT 24
Finished Jul 06 06:28:33 PM PDT 24
Peak memory 220948 kb
Host smart-3290fc55-da01-4cdf-85dc-2d5851d82a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117932410 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_alert.2117932410
Directory /workspace/84.edn_alert/latest

Test location /workspace/coverage/default/84.edn_err.3638518914
Short name T165
Test name
Test status
Simulation time 78531776 ps
CPU time 1.21 seconds
Started Jul 06 06:28:29 PM PDT 24
Finished Jul 06 06:28:30 PM PDT 24
Peak memory 226188 kb
Host smart-dce871f5-1f43-4b85-a641-231e469e430e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638518914 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.3638518914
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.3475473198
Short name T919
Test name
Test status
Simulation time 40050231 ps
CPU time 1.28 seconds
Started Jul 06 06:28:30 PM PDT 24
Finished Jul 06 06:28:31 PM PDT 24
Peak memory 217696 kb
Host smart-039c227c-dfee-4397-ae62-b8f46447c898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475473198 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.3475473198
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_alert.3325087991
Short name T693
Test name
Test status
Simulation time 26297655 ps
CPU time 1.25 seconds
Started Jul 06 06:28:32 PM PDT 24
Finished Jul 06 06:28:33 PM PDT 24
Peak memory 220004 kb
Host smart-37050cb7-b620-462d-a64d-6e180cebb0d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325087991 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_alert.3325087991
Directory /workspace/85.edn_alert/latest

Test location /workspace/coverage/default/85.edn_err.168793839
Short name T462
Test name
Test status
Simulation time 30786153 ps
CPU time 0.91 seconds
Started Jul 06 06:28:34 PM PDT 24
Finished Jul 06 06:28:35 PM PDT 24
Peak memory 224040 kb
Host smart-fd548e36-0f98-44b2-9893-b331e22bb9bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168793839 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.168793839
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.2956099494
Short name T729
Test name
Test status
Simulation time 79366008 ps
CPU time 1.17 seconds
Started Jul 06 06:28:27 PM PDT 24
Finished Jul 06 06:28:29 PM PDT 24
Peak memory 217824 kb
Host smart-f5318220-7c9e-4cb7-9987-997163542444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956099494 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.2956099494
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_alert.1062457042
Short name T387
Test name
Test status
Simulation time 54473332 ps
CPU time 1.28 seconds
Started Jul 06 06:28:31 PM PDT 24
Finished Jul 06 06:28:33 PM PDT 24
Peak memory 220196 kb
Host smart-f674f264-355d-4a94-b818-b836c44b1875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062457042 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_alert.1062457042
Directory /workspace/86.edn_alert/latest

Test location /workspace/coverage/default/86.edn_err.2347892434
Short name T6
Test name
Test status
Simulation time 34883238 ps
CPU time 0.92 seconds
Started Jul 06 06:28:35 PM PDT 24
Finished Jul 06 06:28:36 PM PDT 24
Peak memory 220000 kb
Host smart-e9015b85-ce22-42f4-9285-9fee8886decb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347892434 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.2347892434
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.3697551321
Short name T48
Test name
Test status
Simulation time 40979220 ps
CPU time 1.19 seconds
Started Jul 06 06:28:32 PM PDT 24
Finished Jul 06 06:28:34 PM PDT 24
Peak memory 219060 kb
Host smart-dd386106-8354-4576-b798-b6dcae4fbb5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697551321 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.3697551321
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_alert.2588268132
Short name T408
Test name
Test status
Simulation time 61668426 ps
CPU time 1.26 seconds
Started Jul 06 06:28:33 PM PDT 24
Finished Jul 06 06:28:34 PM PDT 24
Peak memory 220040 kb
Host smart-357b7cd3-1fe8-461a-87f1-3a455399da71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588268132 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_alert.2588268132
Directory /workspace/87.edn_alert/latest

Test location /workspace/coverage/default/87.edn_err.3682786618
Short name T640
Test name
Test status
Simulation time 24705990 ps
CPU time 0.98 seconds
Started Jul 06 06:28:30 PM PDT 24
Finished Jul 06 06:28:31 PM PDT 24
Peak memory 219008 kb
Host smart-02d88d7c-35b0-4702-ba47-f453084c8f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682786618 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.3682786618
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.3669609691
Short name T13
Test name
Test status
Simulation time 40452260 ps
CPU time 1.22 seconds
Started Jul 06 06:28:35 PM PDT 24
Finished Jul 06 06:28:37 PM PDT 24
Peak memory 219392 kb
Host smart-67d0d856-091a-49aa-9746-00de06441ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669609691 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.3669609691
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_alert.1844327576
Short name T189
Test name
Test status
Simulation time 74949791 ps
CPU time 1.14 seconds
Started Jul 06 06:28:32 PM PDT 24
Finished Jul 06 06:28:34 PM PDT 24
Peak memory 220724 kb
Host smart-d09863ef-e5d7-4090-b3c7-e7ef3e5a0b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844327576 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_alert.1844327576
Directory /workspace/88.edn_alert/latest

Test location /workspace/coverage/default/88.edn_err.884467968
Short name T942
Test name
Test status
Simulation time 35258018 ps
CPU time 1.29 seconds
Started Jul 06 06:28:31 PM PDT 24
Finished Jul 06 06:28:33 PM PDT 24
Peak memory 220648 kb
Host smart-e7bc7d7b-8e55-4efb-a607-91f2dade23ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884467968 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.884467968
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.2209830449
Short name T852
Test name
Test status
Simulation time 90000064 ps
CPU time 1.48 seconds
Started Jul 06 06:28:29 PM PDT 24
Finished Jul 06 06:28:31 PM PDT 24
Peak memory 219440 kb
Host smart-6a7e2ad2-4b09-4811-be91-57cf559b0044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209830449 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.2209830449
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_alert.1955826679
Short name T937
Test name
Test status
Simulation time 170890359 ps
CPU time 1.2 seconds
Started Jul 06 06:28:31 PM PDT 24
Finished Jul 06 06:28:32 PM PDT 24
Peak memory 219696 kb
Host smart-2f8ab4cf-abf5-49db-a9bd-81bedb75ef7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955826679 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_alert.1955826679
Directory /workspace/89.edn_alert/latest

Test location /workspace/coverage/default/89.edn_err.426484390
Short name T208
Test name
Test status
Simulation time 40017511 ps
CPU time 0.96 seconds
Started Jul 06 06:28:34 PM PDT 24
Finished Jul 06 06:28:35 PM PDT 24
Peak memory 224056 kb
Host smart-48688213-f0b4-4a74-8df0-f0fdabc88fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426484390 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.426484390
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.1527086455
Short name T961
Test name
Test status
Simulation time 30623393 ps
CPU time 1.28 seconds
Started Jul 06 06:28:37 PM PDT 24
Finished Jul 06 06:28:38 PM PDT 24
Peak memory 217724 kb
Host smart-f7f3e0a2-81d5-4841-94db-7789ef5f6fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527086455 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.1527086455
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.796694988
Short name T309
Test name
Test status
Simulation time 52010949 ps
CPU time 1.26 seconds
Started Jul 06 06:27:07 PM PDT 24
Finished Jul 06 06:27:08 PM PDT 24
Peak memory 220572 kb
Host smart-f21f4594-a5b6-495d-9ee0-bd86d2844a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796694988 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.796694988
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.944589356
Short name T532
Test name
Test status
Simulation time 14237014 ps
CPU time 0.92 seconds
Started Jul 06 06:27:08 PM PDT 24
Finished Jul 06 06:27:10 PM PDT 24
Peak memory 215228 kb
Host smart-d99aee93-23eb-4f80-ace5-83e9762f3b40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944589356 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.944589356
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.1730189826
Short name T996
Test name
Test status
Simulation time 11895437 ps
CPU time 0.94 seconds
Started Jul 06 06:27:08 PM PDT 24
Finished Jul 06 06:27:10 PM PDT 24
Peak memory 216508 kb
Host smart-3af46000-78e1-4a95-8792-e6d841325c24
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730189826 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.1730189826
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.3137433872
Short name T562
Test name
Test status
Simulation time 42771461 ps
CPU time 1.3 seconds
Started Jul 06 06:27:05 PM PDT 24
Finished Jul 06 06:27:06 PM PDT 24
Peak memory 220084 kb
Host smart-f4e39d9f-4e4f-49a6-858a-43c99e08a84d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137433872 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.3137433872
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.1606162842
Short name T931
Test name
Test status
Simulation time 73670671 ps
CPU time 1.08 seconds
Started Jul 06 06:27:08 PM PDT 24
Finished Jul 06 06:27:09 PM PDT 24
Peak memory 220132 kb
Host smart-8170344f-6f20-4662-8a93-890251fb40eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606162842 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.1606162842
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.2798851679
Short name T656
Test name
Test status
Simulation time 294051231 ps
CPU time 3.77 seconds
Started Jul 06 06:27:06 PM PDT 24
Finished Jul 06 06:27:11 PM PDT 24
Peak memory 220580 kb
Host smart-5e8a0f4f-62c1-4894-b9f5-e2bc5f88ac9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798851679 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.2798851679
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.2486248572
Short name T932
Test name
Test status
Simulation time 20799592 ps
CPU time 1.18 seconds
Started Jul 06 06:27:06 PM PDT 24
Finished Jul 06 06:27:08 PM PDT 24
Peak memory 224308 kb
Host smart-2c5963de-7d2f-487d-811d-bece0d6a9044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486248572 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.2486248572
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.2855511837
Short name T898
Test name
Test status
Simulation time 16914411 ps
CPU time 1 seconds
Started Jul 06 06:27:07 PM PDT 24
Finished Jul 06 06:27:08 PM PDT 24
Peak memory 207484 kb
Host smart-1e1f0218-08ed-40fc-ae76-2d52f0c94fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855511837 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.2855511837
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.3799701139
Short name T843
Test name
Test status
Simulation time 85546993 ps
CPU time 0.9 seconds
Started Jul 06 06:27:08 PM PDT 24
Finished Jul 06 06:27:10 PM PDT 24
Peak memory 215656 kb
Host smart-d99e789e-0a5f-4308-a6c8-f36a86088cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799701139 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.3799701139
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.1197269022
Short name T439
Test name
Test status
Simulation time 502977892 ps
CPU time 1.47 seconds
Started Jul 06 06:27:06 PM PDT 24
Finished Jul 06 06:27:07 PM PDT 24
Peak memory 217716 kb
Host smart-2872dd65-4b02-49f1-913e-b6080fdcd998
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197269022 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.1197269022
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.3569684691
Short name T909
Test name
Test status
Simulation time 69788161398 ps
CPU time 346.41 seconds
Started Jul 06 06:27:06 PM PDT 24
Finished Jul 06 06:32:53 PM PDT 24
Peak memory 219188 kb
Host smart-3fee7da0-7461-4ae7-abed-7280282a6067
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569684691 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.3569684691
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_alert.13182091
Short name T819
Test name
Test status
Simulation time 25526674 ps
CPU time 1.19 seconds
Started Jul 06 06:28:37 PM PDT 24
Finished Jul 06 06:28:38 PM PDT 24
Peak memory 220004 kb
Host smart-556d68b7-ee64-445b-8862-7b5b5247c437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13182091 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_alert.13182091
Directory /workspace/90.edn_alert/latest

Test location /workspace/coverage/default/90.edn_genbits.1568731072
Short name T703
Test name
Test status
Simulation time 61292996 ps
CPU time 1.35 seconds
Started Jul 06 06:28:32 PM PDT 24
Finished Jul 06 06:28:34 PM PDT 24
Peak memory 219260 kb
Host smart-a83170a5-eeae-443f-9c37-04bcf59ea430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568731072 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.1568731072
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_alert.833474805
Short name T251
Test name
Test status
Simulation time 123691885 ps
CPU time 1.18 seconds
Started Jul 06 06:28:30 PM PDT 24
Finished Jul 06 06:28:32 PM PDT 24
Peak memory 219832 kb
Host smart-f4a9ed29-c325-4ef6-81be-91d529a93031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833474805 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_alert.833474805
Directory /workspace/91.edn_alert/latest

Test location /workspace/coverage/default/91.edn_err.3385243695
Short name T553
Test name
Test status
Simulation time 18459029 ps
CPU time 1.08 seconds
Started Jul 06 06:28:34 PM PDT 24
Finished Jul 06 06:28:36 PM PDT 24
Peak memory 218768 kb
Host smart-d46a00e5-602e-4fa0-85f7-6d87e3f3a867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385243695 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.3385243695
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.268167386
Short name T347
Test name
Test status
Simulation time 74233907 ps
CPU time 1.43 seconds
Started Jul 06 06:28:30 PM PDT 24
Finished Jul 06 06:28:32 PM PDT 24
Peak memory 217688 kb
Host smart-09c1eed0-594e-49b8-9a46-b3e2497206b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268167386 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.268167386
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_alert.369232437
Short name T289
Test name
Test status
Simulation time 100569802 ps
CPU time 1.28 seconds
Started Jul 06 06:28:32 PM PDT 24
Finished Jul 06 06:28:34 PM PDT 24
Peak memory 215984 kb
Host smart-a53d75ae-f4ed-4429-b05d-d4ad9c56c8e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369232437 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_alert.369232437
Directory /workspace/92.edn_alert/latest

Test location /workspace/coverage/default/92.edn_err.501731022
Short name T211
Test name
Test status
Simulation time 19311748 ps
CPU time 1.04 seconds
Started Jul 06 06:28:32 PM PDT 24
Finished Jul 06 06:28:34 PM PDT 24
Peak memory 218828 kb
Host smart-66ee7e62-007f-44d2-98ca-1cc9c7c46d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501731022 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.501731022
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.380686538
Short name T673
Test name
Test status
Simulation time 31614724 ps
CPU time 1.35 seconds
Started Jul 06 06:28:41 PM PDT 24
Finished Jul 06 06:28:42 PM PDT 24
Peak memory 217856 kb
Host smart-5b73e6a8-73ba-4d34-891e-fdebb9266c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380686538 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.380686538
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_err.3729995688
Short name T202
Test name
Test status
Simulation time 34298383 ps
CPU time 0.88 seconds
Started Jul 06 06:28:35 PM PDT 24
Finished Jul 06 06:28:37 PM PDT 24
Peak memory 218692 kb
Host smart-f19b0b2d-649c-402b-81d5-ac320d13573d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729995688 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.3729995688
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.4124821314
Short name T331
Test name
Test status
Simulation time 45997051 ps
CPU time 1.16 seconds
Started Jul 06 06:28:30 PM PDT 24
Finished Jul 06 06:28:31 PM PDT 24
Peak memory 217676 kb
Host smart-78097e43-4543-44f1-a13e-3130ce5abc8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124821314 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.4124821314
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_alert.4167927646
Short name T660
Test name
Test status
Simulation time 174146673 ps
CPU time 1.21 seconds
Started Jul 06 06:28:34 PM PDT 24
Finished Jul 06 06:28:36 PM PDT 24
Peak memory 219840 kb
Host smart-4afd52cd-aea5-4fda-b28a-73ac826fac2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167927646 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_alert.4167927646
Directory /workspace/94.edn_alert/latest

Test location /workspace/coverage/default/94.edn_err.479279553
Short name T207
Test name
Test status
Simulation time 24852387 ps
CPU time 0.95 seconds
Started Jul 06 06:28:31 PM PDT 24
Finished Jul 06 06:28:32 PM PDT 24
Peak memory 219940 kb
Host smart-4f580778-6296-48ec-817c-4d5af75aa5cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479279553 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.479279553
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.2369879922
Short name T351
Test name
Test status
Simulation time 69741917 ps
CPU time 1.14 seconds
Started Jul 06 06:28:36 PM PDT 24
Finished Jul 06 06:28:38 PM PDT 24
Peak memory 220372 kb
Host smart-6013fb67-3511-49e5-84fa-71651e8c44ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369879922 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.2369879922
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_alert.3203858566
Short name T725
Test name
Test status
Simulation time 107831051 ps
CPU time 1.24 seconds
Started Jul 06 06:28:29 PM PDT 24
Finished Jul 06 06:28:31 PM PDT 24
Peak memory 219592 kb
Host smart-7f04d921-097a-4a3c-b19b-fae3cd521001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203858566 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_alert.3203858566
Directory /workspace/95.edn_alert/latest

Test location /workspace/coverage/default/95.edn_err.75315655
Short name T776
Test name
Test status
Simulation time 19342791 ps
CPU time 1.07 seconds
Started Jul 06 06:28:30 PM PDT 24
Finished Jul 06 06:28:31 PM PDT 24
Peak memory 215800 kb
Host smart-19889a6e-3845-469e-af65-65a2ab34e7b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75315655 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.75315655
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.1833800577
Short name T927
Test name
Test status
Simulation time 71637023 ps
CPU time 1.53 seconds
Started Jul 06 06:28:31 PM PDT 24
Finished Jul 06 06:28:33 PM PDT 24
Peak memory 218752 kb
Host smart-73dd82bd-44db-4ca3-b281-4f1af424d7ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833800577 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.1833800577
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_alert.1826584371
Short name T151
Test name
Test status
Simulation time 39736427 ps
CPU time 1.14 seconds
Started Jul 06 06:28:34 PM PDT 24
Finished Jul 06 06:28:36 PM PDT 24
Peak memory 220072 kb
Host smart-0cbb0a47-58c2-4175-ab49-f89a67be4c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826584371 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_alert.1826584371
Directory /workspace/96.edn_alert/latest

Test location /workspace/coverage/default/96.edn_err.2080912599
Short name T140
Test name
Test status
Simulation time 30459469 ps
CPU time 1.11 seconds
Started Jul 06 06:28:43 PM PDT 24
Finished Jul 06 06:28:45 PM PDT 24
Peak memory 224208 kb
Host smart-8cabe536-2677-440e-98c9-cfd095b45602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080912599 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.2080912599
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.2304097231
Short name T359
Test name
Test status
Simulation time 42402829 ps
CPU time 1.37 seconds
Started Jul 06 06:28:36 PM PDT 24
Finished Jul 06 06:28:38 PM PDT 24
Peak memory 218812 kb
Host smart-81267afc-fa99-4613-b775-3a607b880d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304097231 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.2304097231
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_alert.3160419573
Short name T621
Test name
Test status
Simulation time 87973613 ps
CPU time 1.23 seconds
Started Jul 06 06:28:40 PM PDT 24
Finished Jul 06 06:28:42 PM PDT 24
Peak memory 221196 kb
Host smart-2a72a69d-827e-4cb3-97f2-35997e8329ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160419573 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_alert.3160419573
Directory /workspace/97.edn_alert/latest

Test location /workspace/coverage/default/97.edn_err.1803192945
Short name T599
Test name
Test status
Simulation time 42486847 ps
CPU time 0.81 seconds
Started Jul 06 06:28:35 PM PDT 24
Finished Jul 06 06:28:37 PM PDT 24
Peak memory 218556 kb
Host smart-4a44a838-27d9-4adf-bf82-cd1ae6fde1e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803192945 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.1803192945
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.922324503
Short name T505
Test name
Test status
Simulation time 72491458 ps
CPU time 1.09 seconds
Started Jul 06 06:28:40 PM PDT 24
Finished Jul 06 06:28:42 PM PDT 24
Peak memory 219956 kb
Host smart-654e7228-a8ba-477b-939c-76f6f3ec9386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922324503 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.922324503
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_alert.323267128
Short name T875
Test name
Test status
Simulation time 43697089 ps
CPU time 1.18 seconds
Started Jul 06 06:28:37 PM PDT 24
Finished Jul 06 06:28:39 PM PDT 24
Peak memory 219836 kb
Host smart-b3aac70e-e52f-4f23-b910-6f08e31e8376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323267128 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_alert.323267128
Directory /workspace/98.edn_alert/latest

Test location /workspace/coverage/default/98.edn_err.418587384
Short name T192
Test name
Test status
Simulation time 25485392 ps
CPU time 0.94 seconds
Started Jul 06 06:28:34 PM PDT 24
Finished Jul 06 06:28:35 PM PDT 24
Peak memory 219804 kb
Host smart-f90b6f3b-02bd-4911-8719-177d760ac121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418587384 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.418587384
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.1962464010
Short name T701
Test name
Test status
Simulation time 70763357 ps
CPU time 1.47 seconds
Started Jul 06 06:28:40 PM PDT 24
Finished Jul 06 06:28:42 PM PDT 24
Peak memory 217884 kb
Host smart-0d4fe6da-ff51-469a-a55b-c7886325bb4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962464010 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.1962464010
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_alert.2977780283
Short name T319
Test name
Test status
Simulation time 71984540 ps
CPU time 1.19 seconds
Started Jul 06 06:28:44 PM PDT 24
Finished Jul 06 06:28:45 PM PDT 24
Peak memory 220988 kb
Host smart-ba29c027-c60d-4720-88e3-41d14b151de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977780283 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_alert.2977780283
Directory /workspace/99.edn_alert/latest

Test location /workspace/coverage/default/99.edn_err.2732223919
Short name T893
Test name
Test status
Simulation time 34463537 ps
CPU time 1.05 seconds
Started Jul 06 06:28:42 PM PDT 24
Finished Jul 06 06:28:43 PM PDT 24
Peak memory 224248 kb
Host smart-6cd87072-79ec-4750-963f-8c4a3943c937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732223919 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.2732223919
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.2095087955
Short name T554
Test name
Test status
Simulation time 219652780 ps
CPU time 1.67 seconds
Started Jul 06 06:28:44 PM PDT 24
Finished Jul 06 06:28:46 PM PDT 24
Peak memory 219240 kb
Host smart-82dae363-56c7-4c12-b123-228d666a68a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095087955 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.2095087955
Directory /workspace/99.edn_genbits/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%