Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	601522	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4722081

1

T1

3

T2

76

T3

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1415962	1			T1	1		T2	14		T3	20
values[0x0]	1804993	1			T1	2		T2	31		T3	3
values[0x1]	2102648	1			T1	3		T2	46		T3	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	300235	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5023368

1

T1

5

T2

81

T3

16

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	18790	1			T4	448		T28	1		T47	1
valid_sources[0x01]	20463	1			T4	489		T89	1		T43	530
valid_sources[0x02]	21415	1			T4	488		T27	4		T28	4
valid_sources[0x03]	19866	1			T2	3		T4	461		T85	6
valid_sources[0x04]	19579	1			T2	1		T9	1		T4	432
valid_sources[0x05]	21065	1			T4	448		T46	3		T48	1
valid_sources[0x06]	21930	1			T3	1		T9	1		T4	456
valid_sources[0x07]	20546	1			T4	460		T46	1		T32	1
valid_sources[0x08]	21621	1			T2	1		T9	1		T4	472
valid_sources[0x09]	20902	1			T4	467		T46	1		T32	1
valid_sources[0x0a]	22395	1			T4	442		T28	5		T43	524
valid_sources[0x0b]	19355	1			T4	444		T48	1		T89	2
valid_sources[0x0c]	20858	1			T2	3		T4	444		T33	2
valid_sources[0x0d]	19816	1			T4	460		T46	1		T33	1
valid_sources[0x0e]	19480	1			T2	1		T4	479		T28	1
valid_sources[0x0f]	23085	1			T4	512		T28	1		T85	1
valid_sources[0x10]	20388	1			T4	438		T48	1		T90	1
valid_sources[0x11]	22496	1			T4	462		T28	1		T59	2
valid_sources[0x12]	21003	1			T4	470		T48	2		T43	473
valid_sources[0x13]	20335	1			T2	3		T4	492		T28	4
valid_sources[0x14]	20383	1			T4	433		T27	1		T23	3
valid_sources[0x15]	20288	1			T9	2		T4	459		T28	1
valid_sources[0x16]	20245	1			T9	1		T4	514		T28	2
valid_sources[0x17]	21866	1			T4	466		T46	1		T43	528
valid_sources[0x18]	21115	1			T4	479		T28	1		T46	1
valid_sources[0x19]	20056	1			T2	1		T4	472		T28	1
valid_sources[0x1a]	21896	1			T9	1		T4	459		T28	3
valid_sources[0x1b]	20939	1			T4	406		T27	4		T28	3
valid_sources[0x1c]	20391	1			T4	465		T46	1		T33	1
valid_sources[0x1d]	19757	1			T4	425		T28	1		T47	2
valid_sources[0x1e]	21036	1			T4	449		T46	1		T33	1
valid_sources[0x1f]	23876	1			T4	430		T85	6		T48	1
valid_sources[0x20]	19986	1			T4	478		T33	3		T48	1
valid_sources[0x21]	19418	1			T4	414		T28	1		T89	2
valid_sources[0x22]	20835	1			T2	1		T9	1		T4	437
valid_sources[0x23]	19975	1			T9	1		T10	1		T4	411
valid_sources[0x24]	21223	1			T25	11		T4	476		T28	1
valid_sources[0x25]	20429	1			T2	3		T3	1		T4	439
valid_sources[0x26]	21369	1			T4	469		T48	1		T43	580
valid_sources[0x27]	21192	1			T2	1		T4	433		T46	2
valid_sources[0x28]	21143	1			T3	1		T4	464		T28	2
valid_sources[0x29]	20270	1			T2	1		T4	463		T28	5
valid_sources[0x2a]	19292	1			T9	1		T4	465		T23	3
valid_sources[0x2b]	22194	1			T4	485		T48	2		T6	2
valid_sources[0x2c]	21651	1			T4	468		T43	523		T44	178
valid_sources[0x2d]	22670	1			T3	1		T10	1		T4	459
valid_sources[0x2e]	20227	1			T25	3		T9	2		T26	7
valid_sources[0x2f]	19888	1			T2	2		T25	6		T10	60
valid_sources[0x30]	21911	1			T26	11		T4	479		T28	2
valid_sources[0x31]	20173	1			T4	443		T89	1		T43	461
valid_sources[0x32]	20214	1			T25	12		T4	473		T43	548
valid_sources[0x33]	20470	1			T4	481		T46	1		T33	1
valid_sources[0x34]	20443	1			T4	459		T28	2		T46	1
valid_sources[0x35]	21275	1			T9	1		T4	494		T48	2
valid_sources[0x36]	20223	1			T4	433		T28	2		T46	1
valid_sources[0x37]	21703	1			T4	444		T85	12		T33	1
valid_sources[0x38]	21362	1			T2	2		T3	1		T4	448
valid_sources[0x39]	19607	1			T4	428		T28	1		T46	3
valid_sources[0x3a]	21568	1			T2	1		T4	444		T28	3
valid_sources[0x3b]	19643	1			T10	1		T4	458		T23	1
valid_sources[0x3c]	22883	1			T9	2		T4	481		T32	1
valid_sources[0x3d]	19431	1			T2	2		T3	1		T4	467
valid_sources[0x3e]	21252	1			T4	489		T28	3		T46	2
valid_sources[0x3f]	19990	1			T9	1		T4	455		T32	1
valid_sources[0x40]	20599	1			T4	475		T23	4		T59	1
valid_sources[0x41]	19848	1			T4	485		T28	1		T23	2
valid_sources[0x42]	20927	1			T4	415		T59	1		T6	2
valid_sources[0x43]	21570	1			T4	463		T46	1		T32	1
valid_sources[0x44]	22469	1			T25	2		T9	1		T4	482
valid_sources[0x45]	20734	1			T9	1		T4	436		T46	2
valid_sources[0x46]	20654	1			T3	1		T4	461		T33	1
valid_sources[0x47]	20656	1			T4	463		T48	1		T43	460
valid_sources[0x48]	20620	1			T2	1		T4	445		T28	2
valid_sources[0x49]	20995	1			T9	2		T4	503		T33	1
valid_sources[0x4a]	21420	1			T4	460		T48	2		T6	5
valid_sources[0x4b]	21365	1			T9	2		T10	1		T4	424
valid_sources[0x4c]	20118	1			T4	464		T89	1		T43	536
valid_sources[0x4d]	22312	1			T2	2		T3	1		T4	400
valid_sources[0x4e]	20376	1			T2	2		T3	1		T9	1
valid_sources[0x4f]	21021	1			T4	430		T43	507		T44	150
valid_sources[0x50]	20312	1			T4	461		T43	559		T84	146
valid_sources[0x51]	21171	1			T9	1		T4	431		T28	1
valid_sources[0x52]	21686	1			T4	478		T23	4		T43	485
valid_sources[0x53]	20914	1			T2	1		T10	1		T4	452
valid_sources[0x54]	22431	1			T2	1		T4	489		T32	1
valid_sources[0x55]	18296	1			T9	1		T4	411		T23	1
valid_sources[0x56]	21632	1			T4	450		T27	1		T28	4
valid_sources[0x57]	21486	1			T4	413		T28	2		T32	1
valid_sources[0x58]	20303	1			T4	485		T28	3		T85	5
valid_sources[0x59]	20251	1			T2	5		T4	469		T46	1
valid_sources[0x5a]	21080	1			T2	1		T4	432		T28	1
valid_sources[0x5b]	21353	1			T10	1		T4	429		T28	2
valid_sources[0x5c]	21224	1			T9	1		T4	463		T28	2
valid_sources[0x5d]	19299	1			T2	2		T4	460		T23	4
valid_sources[0x5e]	20924	1			T4	471		T28	3		T32	3
valid_sources[0x5f]	19967	1			T4	457		T23	2		T33	1
valid_sources[0x60]	20844	1			T4	460		T27	3		T28	2
valid_sources[0x61]	20406	1			T4	462		T28	1		T33	1
valid_sources[0x62]	23356	1			T9	1		T4	421		T46	1
valid_sources[0x63]	19754	1			T2	1		T4	496		T28	2
valid_sources[0x64]	20910	1			T4	463		T28	4		T85	3
valid_sources[0x65]	20806	1			T26	16		T4	428		T90	1
valid_sources[0x66]	19393	1			T4	452		T28	3		T23	2
valid_sources[0x67]	21080	1			T4	493		T28	1		T23	5
valid_sources[0x68]	20789	1			T4	444		T23	7		T33	1
valid_sources[0x69]	19422	1			T2	2		T9	1		T4	484
valid_sources[0x6a]	21111	1			T9	1		T4	431		T85	1
valid_sources[0x6b]	20736	1			T4	419		T85	4		T59	9
valid_sources[0x6c]	20580	1			T10	2		T4	481		T28	12
valid_sources[0x6d]	22438	1			T4	460		T28	1		T46	1
valid_sources[0x6e]	19465	1			T4	429		T48	1		T43	494
valid_sources[0x6f]	19572	1			T4	451		T28	5		T32	1
valid_sources[0x70]	20833	1			T2	1		T9	3		T4	478
valid_sources[0x71]	19370	1			T2	1		T4	443		T46	1
valid_sources[0x72]	21458	1			T25	7		T4	438		T32	2
valid_sources[0x73]	19893	1			T10	1		T4	469		T28	3
valid_sources[0x74]	19854	1			T2	1		T9	1		T4	454
valid_sources[0x75]	21732	1			T4	443		T48	1		T43	491
valid_sources[0x76]	19508	1			T2	1		T9	1		T4	460
valid_sources[0x77]	21648	1			T4	459		T48	1		T43	458
valid_sources[0x78]	19737	1			T3	1		T4	481		T85	3
valid_sources[0x79]	19961	1			T4	446		T33	1		T48	3
valid_sources[0x7a]	19376	1			T4	448		T23	9		T32	1
valid_sources[0x7b]	21485	1			T3	1		T4	509		T28	3
valid_sources[0x7c]	21045	1			T4	503		T46	1		T85	1
valid_sources[0x7d]	20327	1			T2	1		T4	471		T43	550
valid_sources[0x7e]	20762	1			T4	444		T23	3		T46	1
valid_sources[0x7f]	20674	1			T4	447		T59	2		T43	517
valid_sources[0x80]	20187	1			T3	1		T26	3		T4	457

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1192002

1

T2

2

T3

3

T25

7

values[0x0]

all_enables

biggest_size

1766283

1

T1

2

T2

29

T3

2

values[0x1]

all_enables

biggest_size

1763796

1

T1

1

T2

45

T3

3