Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
62.50	62.50	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	62.50	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	24	28	53.85

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	24	28	53.85	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2544	1			T2	3		T25	1		T9	6
non_zero_bins[1]	1789	1			T25	1		T9	3		T4	21
zero	8869	1			T1	4		T3	3		T25	5

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	514	1			T4	8		T28	1		T89	1
uni	3451	1			T3	1		T25	2		T26	2
gen	4210	1			T1	2		T3	1		T25	2
res	783	1			T2	2		T25	1		T9	5
ins	4244	1			T1	2		T2	1		T3	1

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

8656

1

T1

2

T2

1

T3

3

mubi_true

4546

1

T1

2

T2

2

T25

3

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

16

1

T101

1

T304

1

T305

1

pass

13186

1

T1

4

T2

3

T3

3

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	24	28	53.85	24
Automatically Generated Cross Bins	52	24	28	53.85	24
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	*	[fail]	*	--	--	6

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	117	1			T4	3		T43	1		T67	1
upd	non_zero_bins[0]	pass	mubi_true	126	1			T4	2		T28	1		T83	1
upd	non_zero_bins[1]	pass	mubi_false	77	1			T4	1		T44	1		T84	3
upd	non_zero_bins[1]	pass	mubi_true	98	1			T4	2		T89	1		T43	4
upd	zero	pass	mubi_false	48	1			T43	1		T83	1		T120	2
upd	zero	pass	mubi_true	48	1			T43	1		T44	1		T306	1
uni	zero	pass	mubi_false	2552	1			T3	1		T25	2		T26	2
uni	zero	pass	mubi_true	899	1			T4	17		T43	15		T44	6
gen	non_zero_bins[0]	pass	mubi_false	455	1			T4	6		T43	5		T44	2
gen	non_zero_bins[0]	pass	mubi_true	474	1			T26	1		T4	5		T89	1
gen	non_zero_bins[1]	pass	mubi_false	385	1			T4	1		T28	1		T43	6
gen	non_zero_bins[1]	pass	mubi_true	300	1			T9	3		T4	4		T45	1
gen	zero	fail	mubi_false	15	1			T101	1		T304	1		T305	1
gen	zero	pass	mubi_false	1836	1			T1	2		T3	1		T25	1
gen	zero	pass	mubi_true	745	1			T25	1		T10	2		T26	1
res	non_zero_bins[0]	pass	mubi_false	184	1			T25	1		T9	1		T4	1
res	non_zero_bins[0]	pass	mubi_true	190	1			T2	2		T9	4		T43	1
res	non_zero_bins[1]	pass	mubi_false	122	1			T45	1		T43	1		T84	1
res	non_zero_bins[1]	pass	mubi_true	125	1			T4	1		T85	1		T48	1
res	zero	fail	mubi_false	1	1			T162	1		-	-		-	-
res	zero	pass	mubi_false	78	1			T5	1		T91	1		T44	1
res	zero	pass	mubi_true	83	1			T26	1		T43	1		T84	1
ins	non_zero_bins[0]	pass	mubi_false	496	1			T2	1		T9	1		T4	8
ins	non_zero_bins[0]	pass	mubi_true	502	1			T26	1		T4	5		T45	1
ins	non_zero_bins[1]	pass	mubi_false	350	1			T4	5		T28	1		T23	1
ins	non_zero_bins[1]	pass	mubi_true	332	1			T25	1		T4	7		T23	1
ins	zero	pass	mubi_false	1940	1			T3	1		T10	1		T4	21
ins	zero	pass	mubi_true	624	1			T1	2		T25	1		T9	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded