Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.14	100.00	94.44		98.65	97.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	98.14	100.00	94.44		98.65	97.62	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.14	100.00	94.44		98.65	97.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.16	100.00	94.44		98.65	97.73	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		108	108	100.00
ALWAYS	42	3	3	100.00
CONT_ASSIGN	44	1	1	100.00
ALWAYS	47	104	104	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	3	3
44	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
78	1	1
79	1	1
80	1	1
83	1	1
84	1	1
85	1	1
			MISSING_ELSE
89	1	1
90	1	1
93	1	1
94	1	1
			MISSING_ELSE
98	1	1
101	1	1
102	1	1
			MISSING_ELSE
106	1	1
107	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
117	1	1
118	1	1
119	1	1
			MISSING_ELSE
123	1	1
124	1	1
125	1	1
			MISSING_ELSE
129	1	1
130	1	1
131	1	1
			MISSING_ELSE
135	1	1
136	1	1
137	1	1
138	1	1
140	1	1
141	1	1
143	1	1
148	1	1
149	1	1
150	1	1
153	1	1
154	1	1
155	1	1
156	1	1
			MISSING_ELSE
160	1	1
161	1	1
162	1	1
165	1	1
166	1	1
167	1	1
168	1	1
			MISSING_ELSE
172	1	1
175	1	1
178	1	1
186	1	1
188	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
211	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T25
1	0	Covered	T1,T51,T39
1	1	Covered	T1,T25,T26

 LINE       66
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T25,T10
1	0	Covered	T2,T9,T23
1	1	Covered	T2,T9,T10

 LINE       186
 EXPRESSION (local_escalate_i || csrng_ack_err_i)
             --------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T32,T33
1	0	Covered	T5,T6,T39

 LINE       188
 EXPRESSION (local_escalate_i ? Error : ((state_q == Error) ? Error : RejectCsrngEntropy))
             --------1-------

-1-	Status	Tests
0	Covered	T10,T32,T33
1	Covered	T5,T6,T39

 LINE       188
 SUB-EXPRESSION ((state_q == Error) ? Error : RejectCsrngEntropy)
                 ---------1--------

-1-	Status	Tests
0	Covered	T10,T32,T33
1	Not Covered

 LINE       188
 SUB-EXPRESSION (state_q == Error)
                ---------1--------

-1-	Status	Tests
0	Covered	T10,T32,T33
1	Covered	T5,T6,T39

 LINE       201
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T9

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	20	100.00	(Not included in score)
Transitions	74	73	98.65
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	156	Covered	T2,T9,T10
AutoCaptGenCnt	143	Covered	T2,T9,T10
AutoCaptReseedCnt	141	Covered	T2,T9,T23
AutoDispatch	125	Covered	T2,T9,T10
AutoFirstAckWait	119	Covered	T2,T9,T10
AutoLoadIns	69	Covered	T2,T9,T10
AutoSendGenCmd	150	Covered	T2,T9,T10
AutoSendReseedCmd	162	Covered	T2,T9,T23
BootDone	98	Covered	T1,T25,T26
BootGenAckWait	90	Covered	T1,T25,T26
BootInsAckWait	80	Covered	T1,T25,T26
BootLoadGen	85	Covered	T1,T25,T26
BootLoadIns	65	Covered	T1,T25,T26
BootLoadUni	102	Covered	T25,T26,T45
BootPulse	94	Covered	T1,T25,T26
BootUniAckWait	107	Covered	T25,T26,T45
Error	188	Covered	T5,T6,T39
Idle	112	Covered	T1,T2,T3
RejectCsrngEntropy	188	Covered	T10,T32,T33
SWPortMode	74	Covered	T3,T25,T10

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	131	Covered	T2,T9,T23
AutoAckWait->Error	188	Covered	T129,T130
AutoAckWait->Idle	211	Covered	T2,T9,T23
AutoAckWait->RejectCsrngEntropy	188	Covered	T10,T91,T20
AutoCaptGenCnt->AutoSendGenCmd	150	Covered	T2,T9,T10
AutoCaptGenCnt->Error	188	Covered	T15
AutoCaptGenCnt->Idle	211	Covered	T103,T77,T131
AutoCaptGenCnt->RejectCsrngEntropy	188	Covered	T33,T132,T133
AutoCaptReseedCnt->AutoSendReseedCmd	162	Covered	T2,T9,T23
AutoCaptReseedCnt->Error	188	Covered	T134
AutoCaptReseedCnt->Idle	211	Covered	T135,T136,T137
AutoCaptReseedCnt->RejectCsrngEntropy	188	Covered	T86,T138,T139
AutoDispatch->AutoCaptGenCnt	143	Covered	T2,T9,T10
AutoDispatch->AutoCaptReseedCnt	141	Covered	T2,T9,T23
AutoDispatch->Error	188	Covered	T140,T141
AutoDispatch->Idle	138	Covered	T11,T24,T21
AutoDispatch->RejectCsrngEntropy	188	Covered	T32,T142,T143
AutoFirstAckWait->AutoDispatch	125	Covered	T2,T9,T10
AutoFirstAckWait->Error	188	Covered	T144,T145,T146
AutoFirstAckWait->Idle	211	Covered	T2,T102,T147
AutoFirstAckWait->RejectCsrngEntropy	188	Covered	T59,T96,T110
AutoLoadIns->AutoFirstAckWait	119	Covered	T2,T9,T10
AutoLoadIns->Error	188	Covered	T64,T148,T149
AutoLoadIns->Idle	211	Covered	T10,T32,T5
AutoLoadIns->RejectCsrngEntropy	188	Covered	T122,T150,T151
AutoSendGenCmd->AutoAckWait	156	Covered	T2,T9,T10
AutoSendGenCmd->Error	188	Covered	T152
AutoSendGenCmd->Idle	211	Covered	T153,T154,T155
AutoSendGenCmd->RejectCsrngEntropy	188	Covered	T125,T156,T157
AutoSendReseedCmd->AutoAckWait	168	Covered	T2,T9,T23
AutoSendReseedCmd->Error	188	Covered	T5,T8,T158
AutoSendReseedCmd->Idle	211	Covered	T23,T159,T160
AutoSendReseedCmd->RejectCsrngEntropy	188	Covered	T75,T161,T162
BootDone->BootLoadUni	102	Covered	T25,T26,T45
BootDone->Error	188	Covered	T63,T65,T163
BootDone->Idle	211	Covered	T52,T88,T58
BootDone->RejectCsrngEntropy	188	Covered	T164,T165,T166
BootGenAckWait->BootPulse	94	Covered	T1,T25,T26
BootGenAckWait->Error	188	Covered	T167,T168,T169
BootGenAckWait->Idle	211	Covered	T170,T171,T169
BootGenAckWait->RejectCsrngEntropy	188	Covered	T172,T173,T174
BootInsAckWait->BootLoadGen	85	Covered	T1,T25,T26
BootInsAckWait->Error	188	Covered	T88,T61,T175
BootInsAckWait->Idle	211	Covered	T39,T87,T14
BootInsAckWait->RejectCsrngEntropy	188	Covered	T93,T94,T126
BootLoadGen->BootGenAckWait	90	Covered	T1,T25,T26
BootLoadGen->Error	188	Covered	T176,T177,T178
BootLoadGen->Idle	211	Covered	T51,T92,T111
BootLoadGen->RejectCsrngEntropy	188	Covered	T66,T179,T180
BootLoadIns->BootInsAckWait	80	Covered	T1,T25,T26
BootLoadIns->Error	188	Covered	T181,T182,T183
BootLoadIns->Idle	211	Covered	T95,T184
BootLoadIns->RejectCsrngEntropy	188	Covered	T185,T186,T187
BootLoadUni->BootUniAckWait	107	Covered	T25,T26,T45
BootLoadUni->Error	188	Covered	T14,T188,T189
BootLoadUni->Idle	211	Not Covered
BootLoadUni->RejectCsrngEntropy	188	Covered	T99,T190,T191
BootPulse->BootDone	98	Covered	T1,T25,T26
BootPulse->Error	188	Covered	T39,T16,T192
BootPulse->Idle	211	Covered	T1,T193,T194
BootPulse->RejectCsrngEntropy	188	Covered	T98,T195,T196
BootUniAckWait->Error	188	Covered	T197,T198,T199
BootUniAckWait->Idle	112	Covered	T25,T26,T45
BootUniAckWait->RejectCsrngEntropy	188	Covered	T200,T201,T202
Idle->AutoLoadIns	69	Covered	T2,T9,T10
Idle->BootLoadIns	65	Covered	T1,T25,T26
Idle->Error	188	Covered	T17,T18,T19
Idle->RejectCsrngEntropy	188	Covered	T32,T94,T71
Idle->SWPortMode	74	Covered	T3,T25,T10
RejectCsrngEntropy->Error	188	Covered	T6,T203,T204
RejectCsrngEntropy->Idle	211	Covered	T10,T32,T33
SWPortMode->Error	188	Covered	T60,T205,T17
SWPortMode->Idle	211	Covered	T4,T33,T43
SWPortMode->RejectCsrngEntropy	188	Covered	T10,T33,T59

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		42	41	97.62
IF	42	2	2	100.00
CASE	62	35	35	100.00
IF	186	5	4	80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	42	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	62	case (state_q)
-2-:	64	if ((boot_req_mode_i && edn_enable_i))
-3-:	66	if ((auto_req_mode_i && edn_enable_i))
-4-:	70	if (edn_enable_i)
-5-:	84	if (csrng_cmd_ack_i)
-6-:	93	if (csrng_cmd_ack_i)
-7-:	101	if ((!boot_req_mode_i))
-8-:	110	if (csrng_cmd_ack_i)
-9-:	118	if (sw_cmd_req_load_i)
-10-:	124	if (csrng_cmd_ack_i)
-11-:	130	if (csrng_cmd_ack_i)
-12-:	136	if ((!auto_req_mode_i))
-13-:	140	if (max_reqs_cnt_zero_i)
-14-:	155	if (cmd_sent_i)
-15-:	167	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T25,T26
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T9,T10
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T25,T10
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T25,T26
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T25,T26
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T25,T26
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T25,T26
BootGenAckWait	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T1,T25,T26
BootGenAckWait	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T1,T25,T26
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T25,T26
BootDone	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T25,T26,T45
BootDone	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T47,T51
BootLoadUni	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T25,T26,T45
BootUniAckWait	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T25,T26,T45
BootUniAckWait	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T25,T26,T45
AutoLoadIns	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T2,T9,T10
AutoLoadIns	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T2,T9,T10
AutoFirstAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T2,T9,T10
AutoFirstAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T9,T10
AutoAckWait	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T2,T9,T10
AutoAckWait	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T2,T9,T10
AutoDispatch	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T11,T24,T21
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T2,T9,T23
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T2,T9,T10
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T9,T10
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T2,T9,T10
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T2,T9,T10
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T9,T23
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T9,T23
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T9,T23
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T25,T10
RejectCsrngEntropy	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T32,T33
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T39
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T87,T7,T70

	LineNo.	Expression
-1-:	186	if ((local_escalate_i || csrng_ack_err_i))
-2-:	188	(local_escalate_i) ? 
-3-:	188	((state_q == Error)) ? 
-4-:	201	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy})))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T5,T6,T39
1	0	1	-	Not Covered
1	0	0	-	Covered	T10,T32,T33
0	-	-	1	Covered	T1,T2,T9
0	-	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	186287800	163216	0	0
FpvSecCmErrorStEscalate_A	186287800	164516	0	0
u_state_regs_A	186250972	186054742	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186287800	163216	0	0
T5	831	360	0	0
T6	1876	1070	0	0
T7	0	280	0	0
T8	0	1127	0	0
T14	0	203	0	0
T39	683	350	0	0
T43	375562	0	0	0
T52	1021	0	0	0
T70	0	200	0	0
T82	1838	0	0	0
T86	2939	0	0	0
T87	0	1060	0	0
T88	0	1144	0	0
T89	2620	0	0	0
T90	2385	0	0	0
T91	2475	0	0	0
T206	0	310	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186287800	164516	0	0
T5	831	361	0	0
T6	1876	1071	0	0
T7	0	281	0	0
T8	0	1128	0	0
T14	0	204	0	0
T39	683	351	0	0
T43	375562	0	0	0
T52	1021	0	0	0
T70	0	201	0	0
T82	1838	0	0	0
T86	2939	0	0	0
T87	0	1061	0	0
T88	0	1145	0	0
T89	2620	0	0	0
T90	2385	0	0	0
T91	2475	0	0	0
T206	0	311	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186250972	186054742	0	0
T1	1337	1254	0	0
T2	2958	2894	0	0
T3	1212	1155	0	0
T4	331516	331504	0	0
T9	3586	3505	0	0
T10	2750	2674	0	0
T25	1390	1291	0	0
T26	2994	2935	0	0
T27	3912	3814	0	0
T28	4075	4022	0	0