Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T9,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T9,T10

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T34,T40,T41
1	1	0	Not Covered
1	1	1	Covered	T2,T9,T10

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T35,T36,T42
1	0	1	Covered	T2,T9,T10
1	1	0	Not Covered
1	1	1	Covered	T2,T9,T10

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T9,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	371777384	599211	0	0
DepthKnown_A	372575600	372183140	0	0
RvalidKnown_A	372575600	372183140	0	0
WreadyKnown_A	372575600	372183140	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	372146646	681526	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371777384	599211	0	0
T2	5916	3830	0	0
T3	2424	0	0	0
T4	663032	0	0	0
T5	0	77	0	0
T9	7172	3673	0	0
T10	5500	939	0	0
T23	7488	5748	0	0
T25	2780	0	0	0
T26	5988	0	0	0
T27	7824	0	0	0
T28	8150	0	0	0
T32	0	769	0	0
T33	0	513	0	0
T59	0	366	0	0
T86	0	890	0	0
T91	0	551	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372575600	372183140	0	0
T1	2674	2508	0	0
T2	5916	5788	0	0
T3	2424	2310	0	0
T4	663032	663008	0	0
T9	7172	7010	0	0
T10	5500	5348	0	0
T25	2780	2582	0	0
T26	5988	5870	0	0
T27	7824	7628	0	0
T28	8150	8044	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372575600	372183140	0	0
T1	2674	2508	0	0
T2	5916	5788	0	0
T3	2424	2310	0	0
T4	663032	663008	0	0
T9	7172	7010	0	0
T10	5500	5348	0	0
T25	2780	2582	0	0
T26	5988	5870	0	0
T27	7824	7628	0	0
T28	8150	8044	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372575600	372183140	0	0
T1	2674	2508	0	0
T2	5916	5788	0	0
T3	2424	2310	0	0
T4	663032	663008	0	0
T9	7172	7010	0	0
T10	5500	5348	0	0
T25	2780	2582	0	0
T26	5988	5870	0	0
T27	7824	7628	0	0
T28	8150	8044	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	372146646	681526	0	0
T2	5916	3830	0	0
T3	2424	0	0	0
T4	663032	0	0	0
T5	0	742	0	0
T6	0	432	0	0
T9	7172	3673	0	0
T10	5500	939	0	0
T23	7488	5748	0	0
T25	2780	0	0	0
T26	5988	0	0	0
T27	7824	0	0	0
T28	8150	0	0	0
T32	0	769	0	0
T33	0	513	0	0
T39	0	310	0	0
T59	0	366	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T9,T10

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T34,T40,T41
1	1	0	Not Covered
1	1	1	Covered	T2,T9,T10

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T35,T36,T42
1	0	1	Covered	T2,T9,T10
1	1	0	Not Covered
1	1	1	Covered	T2,T9,T23

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T9,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	185888692	294637	0	0
DepthKnown_A	186287800	186091570	0	0
RvalidKnown_A	186287800	186091570	0	0
WreadyKnown_A	186287800	186091570	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	186073323	335773	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185888692	294637	0	0
T2	2958	1911	0	0
T3	1212	0	0	0
T4	331516	0	0	0
T5	0	31	0	0
T9	3586	1740	0	0
T10	2750	422	0	0
T23	3744	2852	0	0
T25	1390	0	0	0
T26	2994	0	0	0
T27	3912	0	0	0
T28	4075	0	0	0
T32	0	381	0	0
T33	0	249	0	0
T59	0	184	0	0
T86	0	411	0	0
T91	0	277	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186287800	186091570	0	0
T1	1337	1254	0	0
T2	2958	2894	0	0
T3	1212	1155	0	0
T4	331516	331504	0	0
T9	3586	3505	0	0
T10	2750	2674	0	0
T25	1390	1291	0	0
T26	2994	2935	0	0
T27	3912	3814	0	0
T28	4075	4022	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186287800	186091570	0	0
T1	1337	1254	0	0
T2	2958	2894	0	0
T3	1212	1155	0	0
T4	331516	331504	0	0
T9	3586	3505	0	0
T10	2750	2674	0	0
T25	1390	1291	0	0
T26	2994	2935	0	0
T27	3912	3814	0	0
T28	4075	4022	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186287800	186091570	0	0
T1	1337	1254	0	0
T2	2958	2894	0	0
T3	1212	1155	0	0
T4	331516	331504	0	0
T9	3586	3505	0	0
T10	2750	2674	0	0
T25	1390	1291	0	0
T26	2994	2935	0	0
T27	3912	3814	0	0
T28	4075	4022	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	186073323	335773	0	0
T2	2958	1911	0	0
T3	1212	0	0	0
T4	331516	0	0	0
T5	0	366	0	0
T6	0	217	0	0
T9	3586	1740	0	0
T10	2750	422	0	0
T23	3744	2852	0	0
T25	1390	0	0	0
T26	2994	0	0	0
T27	3912	0	0	0
T28	4075	0	0	0
T32	0	381	0	0
T33	0	249	0	0
T39	0	156	0	0
T59	0	184	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T9,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T9,T10

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T115
1	1	0	Not Covered
1	1	1	Covered	T2,T9,T10

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T38,T116,T117
1	0	1	Covered	T2,T9,T10
1	1	0	Not Covered
1	1	1	Covered	T2,T9,T10

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T9,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	185888692	304574	0	0
DepthKnown_A	186287800	186091570	0	0
RvalidKnown_A	186287800	186091570	0	0
WreadyKnown_A	186287800	186091570	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	186073323	345753	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185888692	304574	0	0
T2	2958	1919	0	0
T3	1212	0	0	0
T4	331516	0	0	0
T5	0	46	0	0
T9	3586	1933	0	0
T10	2750	517	0	0
T23	3744	2896	0	0
T25	1390	0	0	0
T26	2994	0	0	0
T27	3912	0	0	0
T28	4075	0	0	0
T32	0	388	0	0
T33	0	264	0	0
T59	0	182	0	0
T86	0	479	0	0
T91	0	274	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186287800	186091570	0	0
T1	1337	1254	0	0
T2	2958	2894	0	0
T3	1212	1155	0	0
T4	331516	331504	0	0
T9	3586	3505	0	0
T10	2750	2674	0	0
T25	1390	1291	0	0
T26	2994	2935	0	0
T27	3912	3814	0	0
T28	4075	4022	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186287800	186091570	0	0
T1	1337	1254	0	0
T2	2958	2894	0	0
T3	1212	1155	0	0
T4	331516	331504	0	0
T9	3586	3505	0	0
T10	2750	2674	0	0
T25	1390	1291	0	0
T26	2994	2935	0	0
T27	3912	3814	0	0
T28	4075	4022	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186287800	186091570	0	0
T1	1337	1254	0	0
T2	2958	2894	0	0
T3	1212	1155	0	0
T4	331516	331504	0	0
T9	3586	3505	0	0
T10	2750	2674	0	0
T25	1390	1291	0	0
T26	2994	2935	0	0
T27	3912	3814	0	0
T28	4075	4022	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	186073323	345753	0	0
T2	2958	1919	0	0
T3	1212	0	0	0
T4	331516	0	0	0
T5	0	376	0	0
T6	0	215	0	0
T9	3586	1933	0	0
T10	2750	517	0	0
T23	3744	2896	0	0
T25	1390	0	0	0
T26	2994	0	0	0
T27	3912	0	0	0
T28	4075	0	0	0
T32	0	388	0	0
T33	0	264	0	0
T39	0	154	0	0
T59	0	182	0	0