Module Definition
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Module : prim_arbiter_ppc
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.16 95.00 92.31 100.00 93.33

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_edn_core.u_prim_arbiter_ppc_packer_arb 95.16 95.00 92.31 100.00 93.33



Module Instance : tb.dut.u_edn_core.u_prim_arbiter_ppc_packer_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.16 95.00 92.31 100.00 93.33


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.16 95.00 92.31 100.00 93.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.31 100.00 91.03 98.23 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : prim_arbiter_ppc
Line No.TotalCoveredPercent
TOTAL201995.00
CONT_ASSIGN5500
CONT_ASSIGN7511100.00
CONT_ASSIGN7611100.00
ALWAYS8233100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9011100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9411100.00
ALWAYS9666100.00
CONT_ASSIGN120100.00
ALWAYS12444100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
55 unreachable
75 1 1
76 1 1
82 1 1
83 1 1
84 1 1
89 1 1
90 1 1
92 1 1
94 1 1
96 1 1
97 1 1
98 1 1
100 1 1
101 1 1
103 1 1
MISSING_ELSE
120 0 1
124 1 1
125 1 1
126 1 1
127 1 1
MISSING_ELSE


Cond Coverage for Module : prim_arbiter_ppc
TotalCoveredPercent
Conditions131292.31
Logical131292.31
Non-Logical00
Event00

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T9
10CoveredT1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---
-1--2-StatusTests
01CoveredT1,T2,T25
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

Branch Coverage for Module : prim_arbiter_ppc
Line No.TotalCoveredPercent
Branches 10 10 100.00
TERNARY 76 2 2 100.00
TERNARY 90 2 2 100.00
IF 96 4 4 100.00
IF 126 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 76 ((|gen_normal_case.masked_req)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 90 (ready_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 96 if ((!rst_ni)) -2-: 98 if ((valid_o && ready_i)) -3-: 101 if ((valid_o && (!ready_i)))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 126 if (gen_normal_case.winner[i])

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : prim_arbiter_ppc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 15 15 100.00 14 93.33
Cover properties 0 0 0
Cover sequences 0 0 0
Total 15 15 100.00 14 93.33




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckHotOne_A 186287800 186091570 0 0
CheckNGreaterZero_A 964 964 0 0
GntImpliesReady_A 186287800 12812 0 0
GntImpliesValid_A 186287800 12812 0 0
GrantKnown_A 186287800 186091570 0 0
IdxKnown_A 186287800 186091570 0 0
IndexIsCorrect_A 186287800 12812 0 0
LockArbDecision_A 186287800 607404 0 0
NoReadyValidNoGrant_A 186287800 185389583 0 0
ReadyAndValidImplyGrant_A 186287800 12812 0 0
ReqAndReadyImplyGrant_A 186287800 12812 0 0
ReqImpliesValid_A 186287800 621461 0 0
ReqStaysHighUntilGranted0_M 186287800 607404 0 0
RoundRobin_A 186287800 0 0 964
ValidKnown_A 186287800 186091570 0 0


CheckHotOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 186287800 186091570 0 0
T1 1337 1254 0 0
T2 2958 2894 0 0
T3 1212 1155 0 0
T4 331516 331504 0 0
T9 3586 3505 0 0
T10 2750 2674 0 0
T25 1390 1291 0 0
T26 2994 2935 0 0
T27 3912 3814 0 0
T28 4075 4022 0 0

CheckNGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 964 964 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T25 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0

GntImpliesReady_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 186287800 12812 0 0
T1 1337 1 0 0
T2 2958 1 0 0
T3 1212 1 0 0
T4 331516 17 0 0
T9 3586 1 0 0
T10 2750 2 0 0
T23 0 1 0 0
T25 1390 7 0 0
T26 2994 4 0 0
T27 3912 0 0 0
T28 4075 16 0 0

GntImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 186287800 12812 0 0
T1 1337 1 0 0
T2 2958 1 0 0
T3 1212 1 0 0
T4 331516 17 0 0
T9 3586 1 0 0
T10 2750 2 0 0
T23 0 1 0 0
T25 1390 7 0 0
T26 2994 4 0 0
T27 3912 0 0 0
T28 4075 16 0 0

GrantKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 186287800 186091570 0 0
T1 1337 1254 0 0
T2 2958 2894 0 0
T3 1212 1155 0 0
T4 331516 331504 0 0
T9 3586 3505 0 0
T10 2750 2674 0 0
T25 1390 1291 0 0
T26 2994 2935 0 0
T27 3912 3814 0 0
T28 4075 4022 0 0

IdxKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 186287800 186091570 0 0
T1 1337 1254 0 0
T2 2958 2894 0 0
T3 1212 1155 0 0
T4 331516 331504 0 0
T9 3586 3505 0 0
T10 2750 2674 0 0
T25 1390 1291 0 0
T26 2994 2935 0 0
T27 3912 3814 0 0
T28 4075 4022 0 0

IndexIsCorrect_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 186287800 12812 0 0
T1 1337 1 0 0
T2 2958 1 0 0
T3 1212 1 0 0
T4 331516 17 0 0
T9 3586 1 0 0
T10 2750 2 0 0
T23 0 1 0 0
T25 1390 7 0 0
T26 2994 4 0 0
T27 3912 0 0 0
T28 4075 16 0 0

LockArbDecision_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 186287800 607404 0 0
T1 1337 13 0 0
T2 2958 28 0 0
T3 1212 40 0 0
T4 331516 577 0 0
T9 3586 54 0 0
T10 2750 0 0 0
T23 0 38 0 0
T25 1390 449 0 0
T26 2994 1311 0 0
T27 3912 0 0 0
T28 4075 2422 0 0
T47 0 56 0 0

NoReadyValidNoGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 186287800 185389583 0 0
T1 1337 173 0 0
T2 2958 2048 0 0
T3 1212 1114 0 0
T4 331516 331445 0 0
T9 3586 2745 0 0
T10 2750 2605 0 0
T25 1390 830 0 0
T26 2994 1609 0 0
T27 3912 3814 0 0
T28 4075 1527 0 0

ReadyAndValidImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 186287800 12812 0 0
T1 1337 1 0 0
T2 2958 1 0 0
T3 1212 1 0 0
T4 331516 17 0 0
T9 3586 1 0 0
T10 2750 2 0 0
T23 0 1 0 0
T25 1390 7 0 0
T26 2994 4 0 0
T27 3912 0 0 0
T28 4075 16 0 0

ReqAndReadyImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 186287800 12812 0 0
T1 1337 1 0 0
T2 2958 1 0 0
T3 1212 1 0 0
T4 331516 17 0 0
T9 3586 1 0 0
T10 2750 2 0 0
T23 0 1 0 0
T25 1390 7 0 0
T26 2994 4 0 0
T27 3912 0 0 0
T28 4075 16 0 0

ReqImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 186287800 621461 0 0
T1 1337 14 0 0
T2 2958 29 0 0
T3 1212 41 0 0
T4 331516 594 0 0
T9 3586 55 0 0
T10 2750 2 0 0
T23 0 39 0 0
T25 1390 456 0 0
T26 2994 1315 0 0
T27 3912 0 0 0
T28 4075 2438 0 0

ReqStaysHighUntilGranted0_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 186287800 607404 0 0
T1 1337 13 0 0
T2 2958 28 0 0
T3 1212 40 0 0
T4 331516 577 0 0
T9 3586 54 0 0
T10 2750 0 0 0
T23 0 38 0 0
T25 1390 449 0 0
T26 2994 1311 0 0
T27 3912 0 0 0
T28 4075 2422 0 0
T47 0 56 0 0

RoundRobin_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 186287800 0 0 964

ValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 186287800 186091570 0 0
T1 1337 1254 0 0
T2 2958 2894 0 0
T3 1212 1155 0 0
T4 331516 331504 0 0
T9 3586 3505 0 0
T10 2750 2674 0 0
T25 1390 1291 0 0
T26 2994 2935 0 0
T27 3912 3814 0 0
T28 4075 4022 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%