Unified Coverage Report :: Group :: tb.dut.u_edn_cov_if::edn_cfg_cg

Group : tb.dut.u_edn_cov_if::edn_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
edn_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : edn_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance edn_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	21	0	21	100.00

Variables for Group Instance edn_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mode	3	0	3	100.00	100	1	1	0
cp_num_boot_reqs	2	0	2	100.00	100	1	1	0
cp_num_endpoints	7	0	7	100.00	100	1	1	8

Crosses for Group Instance edn_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_num_endpoints_mode	21	0	21	100.00	100	1	1	0

Summary for Variable cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_mode

Excluded/Illegal bins

NAME	COUNT	STATUS
both	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
boot_req_mode	141	1			T25	1		T27	1		T44	1
auto_req_mode	145	1			T14	1		T15	1		T22	1
sw_mode	2964	1			T1	11		T3	1		T26	1

---

Summary for Variable cp_num_boot_reqs

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_boot_reqs

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

multiple

314

1

T3

1

T25

1

T27

1

single

86

1

T26

1

T67

1

T22

1

---

Summary for Variable cp_num_endpoints

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_num_endpoints

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	1652	1			T1	11		T25	1		T26	1
auto[2]	204	1			T56	11		T276	5		T111	4
auto[3]	49	1			T89	1		T303	1		T304	1
auto[4]	29	1			T44	1		T305	1		T109	3
auto[5]	127	1			T202	7		T306	35		T307	1
auto[6]	16	1			T15	1		T308	1		T309	1
auto[7]	1173	1			T3	1		T40	57		T43	1

---

Summary for Cross cr_num_endpoints_mode

Samples crossed: cp_num_endpoints cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	21	0	21	100.00

Automatically Generated Cross Bins for cr_num_endpoints_mode

Excluded/Illegal bins

cp_num_endpoints	cp_mode	COUNT	STATUS
[auto[0]]	[boot_req_mode , auto_req_mode , sw_mode]	--	Excluded	(3 bins)

Covered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	boot_req_mode	87	1			T25	1		T27	1		T65	1
auto[1]	auto_req_mode	84	1			T14	1		T23	1		T24	1
auto[1]	sw_mode	1481	1			T1	11		T26	1		T57	6
auto[2]	boot_req_mode	8	1			T310	1		T311	1		T312	1
auto[2]	auto_req_mode	1	1			T313	1		-	-		-	-
auto[2]	sw_mode	195	1			T56	11		T276	5		T111	4
auto[3]	boot_req_mode	8	1			T314	1		T315	1		T316	1
auto[3]	auto_req_mode	5	1			T303	1		T304	1		T317	1
auto[3]	sw_mode	36	1			T89	1		T318	1		T319	29
auto[4]	boot_req_mode	5	1			T44	1		T305	1		T320	1
auto[4]	auto_req_mode	3	1			T101	1		T321	1		T322	1
auto[4]	sw_mode	21	1			T109	3		T323	1		T324	1
auto[5]	boot_req_mode	1	1			T325	1		-	-		-	-
auto[5]	auto_req_mode	6	1			T307	1		T326	1		T327	1
auto[5]	sw_mode	120	1			T202	7		T306	35		T328	1
auto[6]	boot_req_mode	1	1			T308	1		-	-		-	-
auto[6]	auto_req_mode	4	1			T15	1		T329	1		T330	1
auto[6]	sw_mode	11	1			T309	1		T331	1		T332	1
auto[7]	boot_req_mode	31	1			T43	1		T50	1		T53	1
auto[7]	auto_req_mode	42	1			T22	1		T52	1		T48	1
auto[7]	sw_mode	1100	1			T3	1		T40	57		T66	9