SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
push_pull_agent_pkg.uvm_test_top.env.m_endpoint_agent[0].cov::m_req_ack_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
push_pull_agent_pkg.uvm_test_top.env.m_endpoint_agent[1].cov::m_req_ack_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
push_pull_agent_pkg.uvm_test_top.env.m_endpoint_agent[2].cov::m_req_ack_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
push_pull_agent_pkg.uvm_test_top.env.m_endpoint_agent[3].cov::m_req_ack_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
push_pull_agent_pkg.uvm_test_top.env.m_endpoint_agent[4].cov::m_req_ack_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
push_pull_agent_pkg.uvm_test_top.env.m_endpoint_agent[5].cov::m_req_ack_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
push_pull_agent_pkg.uvm_test_top.env.m_endpoint_agent[6].cov::m_req_ack_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 3 | 0 | 3 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_ack | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 4 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 3 | 0 | 3 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_ack | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 4 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 3 | 0 | 3 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_ack | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 4 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 3 | 0 | 3 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_ack | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 4 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 3 | 0 | 3 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_ack | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 4 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 3 | 0 | 3 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_ack | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 4 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 3 | 0 | 3 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_ack | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 3 | 0 | 3 | 100.00 |
NAME | COUNT | STATUS |
ack_wo_req | 0 | Excluded |
[auto[1]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 1969 | 1 | T1 | 7 | T2 | 2 | T3 | 1 | ||||
auto[2] | 30972 | 1 | T1 | 28 | T2 | 5 | T3 | 4 | ||||
auto[3] | 30025 | 1 | T1 | 28 | T2 | 5 | T3 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 3 | 0 | 3 | 100.00 |
NAME | COUNT | STATUS |
ack_wo_req | 0 | Excluded |
[auto[1]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 192 | 1 | T43 | 1 | T15 | 1 | T22 | 1 | ||||
auto[2] | 4984 | 1 | T4 | 1 | T16 | 1 | T43 | 55 | ||||
auto[3] | 4974 | 1 | T43 | 55 | T15 | 4 | T22 | 536 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 3 | 0 | 3 | 100.00 |
NAME | COUNT | STATUS |
ack_wo_req | 0 | Excluded |
[auto[1]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 175 | 1 | T3 | 1 | T8 | 2 | T34 | 1 | ||||
auto[2] | 4301 | 1 | T3 | 5 | T8 | 5 | T34 | 1 | ||||
auto[3] | 4295 | 1 | T3 | 5 | T8 | 5 | T34 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 3 | 0 | 3 | 100.00 |
NAME | COUNT | STATUS |
ack_wo_req | 0 | Excluded |
[auto[1]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 135 | 1 | T44 | 1 | T45 | 2 | T14 | 1 | ||||
auto[2] | 6530 | 1 | T44 | 12 | T45 | 5 | T14 | 4 | ||||
auto[3] | 6520 | 1 | T44 | 12 | T45 | 5 | T14 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 3 | 0 | 3 | 100.00 |
NAME | COUNT | STATUS |
ack_wo_req | 0 | Excluded |
[auto[1]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 122 | 1 | T3 | 1 | T43 | 1 | T15 | 1 | ||||
auto[2] | 2734 | 1 | T3 | 56 | T5 | 1 | T43 | 4 | ||||
auto[3] | 2722 | 1 | T3 | 56 | T43 | 4 | T15 | 22 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 3 | 0 | 3 | 100.00 |
NAME | COUNT | STATUS |
ack_wo_req | 0 | Excluded |
[auto[1]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 95 | 1 | T37 | 1 | T43 | 1 | T15 | 1 | ||||
auto[2] | 3189 | 1 | T37 | 1 | T43 | 4 | T15 | 8 | ||||
auto[3] | 3181 | 1 | T37 | 1 | T43 | 4 | T15 | 8 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 3 | 0 | 3 | 100.00 |
NAME | COUNT | STATUS |
ack_wo_req | 0 | Excluded |
[auto[1]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 105 | 1 | T43 | 1 | T46 | 1 | T47 | 1 | ||||
auto[2] | 1354 | 1 | T43 | 9 | T46 | 4 | T47 | 4 | ||||
auto[3] | 1351 | 1 | T43 | 9 | T46 | 4 | T47 | 4 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |