Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	655281	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5275174

1

T1

268

T2

50

T3

25

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1567343	1			T1	460		T2	27		T3	63
values[0x0]	2019384	1			T1	145		T2	24		T3	17
values[0x1]	2343728	1			T1	135		T2	27		T3	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	326346	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5604109

1

T1

372

T2

58

T3

43

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	22654	1			T57	1		T40	214		T66	2
valid_sources[0x01]	23584	1			T57	1		T40	253		T37	2
valid_sources[0x02]	23992	1			T56	1		T57	1		T40	86
valid_sources[0x03]	22525	1			T25	1		T56	1		T57	2
valid_sources[0x04]	22479	1			T57	1		T40	639		T66	3
valid_sources[0x05]	23783	1			T25	2		T4	7		T56	1
valid_sources[0x06]	24271	1			T56	1		T57	3		T40	247
valid_sources[0x07]	24017	1			T8	1		T40	259		T66	2
valid_sources[0x08]	24873	1			T25	1		T57	1		T40	688
valid_sources[0x09]	22045	1			T40	552		T66	2		T68	2
valid_sources[0x0a]	24559	1			T25	1		T56	9		T57	4
valid_sources[0x0b]	21173	1			T56	3		T57	2		T40	575
valid_sources[0x0c]	23500	1			T25	1		T9	1		T56	3
valid_sources[0x0d]	22774	1			T25	2		T9	2		T56	6
valid_sources[0x0e]	23323	1			T25	2		T56	2		T40	1206
valid_sources[0x0f]	23998	1			T3	1		T9	1		T57	2
valid_sources[0x10]	23503	1			T56	1		T57	2		T40	544
valid_sources[0x11]	21672	1			T3	2		T25	2		T56	3
valid_sources[0x12]	23737	1			T56	2		T57	1		T40	52
valid_sources[0x13]	23564	1			T8	1		T56	5		T40	223
valid_sources[0x14]	22646	1			T25	1		T4	20		T56	5
valid_sources[0x15]	20961	1			T3	2		T56	2		T57	2
valid_sources[0x16]	22910	1			T25	1		T57	1		T40	372
valid_sources[0x17]	23074	1			T8	1		T56	4		T40	88
valid_sources[0x18]	23129	1			T3	1		T40	225		T14	1
valid_sources[0x19]	23624	1			T3	1		T56	7		T40	154
valid_sources[0x1a]	24024	1			T56	10		T40	394		T65	1
valid_sources[0x1b]	25019	1			T8	1		T25	1		T9	1
valid_sources[0x1c]	23766	1			T8	1		T56	6		T57	1
valid_sources[0x1d]	22859	1			T3	1		T25	1		T57	2
valid_sources[0x1e]	23840	1			T8	2		T25	1		T56	2
valid_sources[0x1f]	23855	1			T25	3		T57	3		T40	211
valid_sources[0x20]	26267	1			T25	1		T56	1		T57	1
valid_sources[0x21]	22864	1			T56	4		T57	3		T40	32
valid_sources[0x22]	22766	1			T25	3		T56	3		T57	3
valid_sources[0x23]	23071	1			T25	1		T56	1		T40	375
valid_sources[0x24]	20612	1			T25	1		T27	99		T56	10
valid_sources[0x25]	24335	1			T25	1		T40	542		T66	2
valid_sources[0x26]	23170	1			T25	1		T56	6		T57	3
valid_sources[0x27]	24135	1			T3	1		T25	1		T56	7
valid_sources[0x28]	22800	1			T2	4		T25	1		T56	5
valid_sources[0x29]	23117	1			T2	47		T25	1		T56	1
valid_sources[0x2a]	23414	1			T25	1		T56	2		T40	326
valid_sources[0x2b]	24452	1			T57	1		T40	74		T66	5
valid_sources[0x2c]	22636	1			T56	3		T40	837		T55	1
valid_sources[0x2d]	22535	1			T40	398		T66	2		T15	4
valid_sources[0x2e]	24969	1			T57	1		T40	589		T14	2
valid_sources[0x2f]	22640	1			T4	4		T56	16		T57	2
valid_sources[0x30]	22697	1			T40	564		T66	2		T24	1
valid_sources[0x31]	22797	1			T3	1		T40	135		T37	7
valid_sources[0x32]	22216	1			T3	1		T25	4		T56	5
valid_sources[0x33]	23137	1			T25	1		T9	2		T56	2
valid_sources[0x34]	22253	1			T56	5		T57	1		T40	311
valid_sources[0x35]	22173	1			T25	2		T56	2		T57	1
valid_sources[0x36]	22410	1			T57	3		T40	39		T55	1
valid_sources[0x37]	21196	1			T3	1		T26	130		T56	4
valid_sources[0x38]	22607	1			T25	3		T57	1		T40	317
valid_sources[0x39]	23278	1			T25	2		T40	201		T14	1
valid_sources[0x3a]	23223	1			T57	1		T40	99		T14	1
valid_sources[0x3b]	23468	1			T2	1		T3	2		T8	8
valid_sources[0x3c]	24018	1			T25	3		T57	1		T40	446
valid_sources[0x3d]	22738	1			T25	1		T57	1		T40	281
valid_sources[0x3e]	20218	1			T8	1		T25	1		T57	1
valid_sources[0x3f]	23708	1			T3	2		T25	2		T56	1
valid_sources[0x40]	23085	1			T3	3		T57	3		T40	562
valid_sources[0x41]	23949	1			T8	1		T56	1		T40	440
valid_sources[0x42]	24282	1			T25	1		T40	90		T13	52
valid_sources[0x43]	24297	1			T2	4		T8	1		T57	1
valid_sources[0x44]	22498	1			T25	2		T56	1		T57	3
valid_sources[0x45]	21606	1			T57	1		T40	108		T66	2
valid_sources[0x46]	22460	1			T9	5		T40	336		T37	3
valid_sources[0x47]	23550	1			T40	263		T14	2		T65	1
valid_sources[0x48]	23673	1			T3	1		T40	221		T66	1
valid_sources[0x49]	20849	1			T3	1		T25	1		T4	7
valid_sources[0x4a]	21938	1			T56	1		T40	57		T14	2
valid_sources[0x4b]	24403	1			T56	1		T57	1		T40	554
valid_sources[0x4c]	23961	1			T57	1		T40	646		T14	2
valid_sources[0x4d]	21612	1			T25	1		T56	1		T57	3
valid_sources[0x4e]	22466	1			T3	1		T8	1		T57	4
valid_sources[0x4f]	23420	1			T40	278		T14	1		T66	1
valid_sources[0x50]	22937	1			T40	432		T45	3		T14	2
valid_sources[0x51]	22845	1			T56	1		T40	55		T14	5
valid_sources[0x52]	23431	1			T25	1		T56	3		T40	396
valid_sources[0x53]	24000	1			T8	1		T4	1		T56	5
valid_sources[0x54]	25830	1			T25	1		T56	2		T57	1
valid_sources[0x55]	23679	1			T3	1		T25	1		T56	15
valid_sources[0x56]	22218	1			T40	124		T85	2		T66	5
valid_sources[0x57]	22465	1			T2	1		T25	1		T56	8
valid_sources[0x58]	24385	1			T8	1		T56	4		T57	3
valid_sources[0x59]	22985	1			T57	2		T40	124		T65	1
valid_sources[0x5a]	23338	1			T8	1		T25	2		T56	1
valid_sources[0x5b]	22620	1			T3	1		T25	1		T57	1
valid_sources[0x5c]	22886	1			T3	1		T57	2		T40	139
valid_sources[0x5d]	21866	1			T57	1		T40	240		T66	5
valid_sources[0x5e]	23363	1			T57	3		T40	274		T49	1
valid_sources[0x5f]	23368	1			T25	2		T56	5		T40	65
valid_sources[0x60]	21807	1			T25	1		T57	1		T40	229
valid_sources[0x61]	25901	1			T57	1		T40	454		T66	1
valid_sources[0x62]	23575	1			T56	1		T57	1		T40	223
valid_sources[0x63]	22537	1			T8	1		T25	3		T40	283
valid_sources[0x64]	23092	1			T3	1		T40	254		T85	1
valid_sources[0x65]	22670	1			T25	1		T40	645		T65	1
valid_sources[0x66]	23537	1			T3	2		T25	2		T57	1
valid_sources[0x67]	21411	1			T2	1		T3	1		T25	1
valid_sources[0x68]	22420	1			T57	2		T40	46		T84	2
valid_sources[0x69]	21617	1			T8	1		T25	1		T9	1
valid_sources[0x6a]	23853	1			T56	1		T40	174		T37	4
valid_sources[0x6b]	24385	1			T40	33		T66	3		T15	3
valid_sources[0x6c]	24781	1			T3	1		T57	3		T40	898
valid_sources[0x6d]	24656	1			T8	2		T25	2		T57	1
valid_sources[0x6e]	23311	1			T25	1		T40	48		T84	1
valid_sources[0x6f]	22024	1			T3	1		T8	1		T40	215
valid_sources[0x70]	22443	1			T25	1		T9	9		T56	5
valid_sources[0x71]	24071	1			T2	3		T3	1		T25	1
valid_sources[0x72]	23018	1			T3	2		T40	730		T66	3
valid_sources[0x73]	23317	1			T25	2		T57	2		T40	847
valid_sources[0x74]	24212	1			T3	2		T56	6		T57	1
valid_sources[0x75]	23341	1			T25	2		T57	2		T40	110
valid_sources[0x76]	22560	1			T56	6		T57	2		T40	319
valid_sources[0x77]	23171	1			T3	2		T56	2		T57	3
valid_sources[0x78]	24386	1			T3	1		T8	2		T57	1
valid_sources[0x79]	25371	1			T8	1		T56	11		T57	3
valid_sources[0x7a]	22091	1			T56	4		T57	1		T40	396
valid_sources[0x7b]	24689	1			T25	2		T9	10		T56	10
valid_sources[0x7c]	23507	1			T56	4		T57	3		T40	306
valid_sources[0x7d]	21586	1			T3	1		T25	3		T56	10
valid_sources[0x7e]	23233	1			T8	1		T25	1		T40	258
valid_sources[0x7f]	22251	1			T25	1		T57	3		T40	414
valid_sources[0x80]	22506	1			T25	2		T57	1		T40	76

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1329236

1

T1

87

T2

9

T3

5

values[0x0]

all_enables

biggest_size

1975929

1

T1

92

T2

21

T3

14

values[0x1]

all_enables

biggest_size

1970009

1

T1

89

T2

20

T3

6