Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
62.50	62.50	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	62.50	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	24	28	53.85

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	24	28	53.85	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2772	1			T1	2		T3	1		T25	1
non_zero_bins[1]	1983	1			T1	8		T3	1		T25	1
zero	9529	1			T1	27		T2	4		T3	2

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	513	1			T1	1		T3	1		T56	1
uni	3784	1			T1	11		T3	1		T25	3
gen	4529	1			T1	11		T2	2		T3	1
res	904	1			T1	3		T26	1		T27	1
ins	4554	1			T1	11		T2	2		T3	1

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

9359

1

T1

30

T2

1

T3

4

mubi_true

4925

1

T1

7

T2

3

T8

3

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

15

1

T45

1

T98

1

T275

1

pass

14269

1

T1

37

T2

4

T3

4

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	24	28	53.85	24
Automatically Generated Cross Bins	52	24	28	53.85	24
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	*	[fail]	*	--	--	6

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	101	1			T40	5		T68	1		T276	1
upd	non_zero_bins[0]	pass	mubi_true	134	1			T40	4		T41	2		T42	3
upd	non_zero_bins[1]	pass	mubi_false	81	1			T56	1		T276	1		T41	3
upd	non_zero_bins[1]	pass	mubi_true	87	1			T40	1		T66	1		T50	1
upd	zero	pass	mubi_false	47	1			T3	1		T40	1		T42	2
upd	zero	pass	mubi_true	63	1			T1	1		T40	2		T66	1
uni	zero	pass	mubi_false	2781	1			T1	8		T3	1		T25	2
uni	zero	pass	mubi_true	1003	1			T1	3		T25	1		T56	5
gen	non_zero_bins[0]	pass	mubi_false	489	1			T40	9		T44	1		T65	1
gen	non_zero_bins[0]	pass	mubi_true	578	1			T26	1		T56	1		T40	6
gen	non_zero_bins[1]	pass	mubi_false	400	1			T1	2		T3	1		T56	1
gen	non_zero_bins[1]	pass	mubi_true	357	1			T1	2		T27	1		T56	1
gen	zero	fail	mubi_false	13	1			T45	1		T98	1		T275	1
gen	zero	pass	mubi_false	1952	1			T1	7		T25	1		T27	1
gen	zero	pass	mubi_true	740	1			T2	2		T8	2		T25	1
res	non_zero_bins[0]	pass	mubi_false	238	1			T1	2		T26	1		T27	1
res	non_zero_bins[0]	pass	mubi_true	166	1			T40	2		T14	1		T15	2
res	non_zero_bins[1]	pass	mubi_false	126	1			T40	1		T22	2		T41	2
res	non_zero_bins[1]	pass	mubi_true	158	1			T1	1		T40	3		T23	3
res	zero	fail	mubi_false	2	1			T277	1		T278	1		-	-
res	zero	pass	mubi_false	124	1			T40	2		T13	1		T44	1
res	zero	pass	mubi_true	90	1			T57	1		T40	3		T41	1
ins	non_zero_bins[0]	pass	mubi_false	523	1			T3	1		T56	1		T57	1
ins	non_zero_bins[0]	pass	mubi_true	543	1			T25	1		T56	1		T40	5
ins	non_zero_bins[1]	pass	mubi_false	392	1			T1	3		T25	1		T56	1
ins	non_zero_bins[1]	pass	mubi_true	382	1			T26	1		T40	10		T14	1
ins	zero	pass	mubi_false	2090	1			T1	8		T2	1		T8	1
ins	zero	pass	mubi_true	624	1			T2	1		T8	1		T9	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded