Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.14	100.00	94.44		98.65	97.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	98.14	100.00	94.44		98.65	97.62	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.14	100.00	94.44		98.65	97.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.16	100.00	94.44		98.65	97.73	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		108	108	100.00
ALWAYS	42	3	3	100.00
CONT_ASSIGN	44	1	1	100.00
ALWAYS	47	104	104	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	3	3
44	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
78	1	1
79	1	1
80	1	1
83	1	1
84	1	1
85	1	1
			MISSING_ELSE
89	1	1
90	1	1
93	1	1
94	1	1
			MISSING_ELSE
98	1	1
101	1	1
102	1	1
			MISSING_ELSE
106	1	1
107	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
117	1	1
118	1	1
119	1	1
			MISSING_ELSE
123	1	1
124	1	1
125	1	1
			MISSING_ELSE
129	1	1
130	1	1
131	1	1
			MISSING_ELSE
135	1	1
136	1	1
137	1	1
138	1	1
140	1	1
141	1	1
143	1	1
148	1	1
149	1	1
150	1	1
153	1	1
154	1	1
155	1	1
156	1	1
			MISSING_ELSE
160	1	1
161	1	1
162	1	1
165	1	1
166	1	1
167	1	1
168	1	1
			MISSING_ELSE
172	1	1
175	1	1
178	1	1
186	1	1
188	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
211	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T85,T16,T47
1	1	Covered	T2,T25,T9

 LINE       66
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T14,T6
1	1	Covered	T2,T8,T9

 LINE       186
 EXPRESSION (local_escalate_i || csrng_ack_err_i)
             --------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T8,T9
1	0	Covered	T4,T5,T37

 LINE       188
 EXPRESSION (local_escalate_i ? Error : ((state_q == Error) ? Error : RejectCsrngEntropy))
             --------1-------

-1-	Status	Tests
0	Covered	T2,T8,T9
1	Covered	T4,T5,T37

 LINE       188
 SUB-EXPRESSION ((state_q == Error) ? Error : RejectCsrngEntropy)
                 ---------1--------

-1-	Status	Tests
0	Covered	T2,T8,T9
1	Not Covered

 LINE       188
 SUB-EXPRESSION (state_q == Error)
                ---------1--------

-1-	Status	Tests
0	Covered	T2,T8,T9
1	Covered	T4,T5,T37

 LINE       201
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T8,T9

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	20	100.00	(Not included in score)
Transitions	74	73	98.65
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	156	Covered	T13,T14,T15
AutoCaptGenCnt	143	Covered	T85,T13,T14
AutoCaptReseedCnt	141	Covered	T13,T14,T15
AutoDispatch	125	Covered	T9,T85,T13
AutoFirstAckWait	119	Covered	T8,T9,T85
AutoLoadIns	69	Covered	T2,T8,T9
AutoSendGenCmd	150	Covered	T13,T14,T15
AutoSendReseedCmd	162	Covered	T13,T14,T15
BootDone	98	Covered	T25,T9,T27
BootGenAckWait	90	Covered	T2,T25,T9
BootInsAckWait	80	Covered	T2,T25,T9
BootLoadGen	85	Covered	T2,T25,T9
BootLoadIns	65	Covered	T2,T25,T9
BootLoadUni	102	Covered	T25,T9,T27
BootPulse	94	Covered	T25,T9,T27
BootUniAckWait	107	Covered	T25,T9,T27
Error	188	Covered	T4,T5,T37
Idle	112	Covered	T1,T2,T3
RejectCsrngEntropy	188	Covered	T2,T8,T9
SWPortMode	74	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	131	Covered	T13,T14,T15
AutoAckWait->Error	188	Covered	T63
AutoAckWait->Idle	211	Covered	T14,T23,T83
AutoAckWait->RejectCsrngEntropy	188	Covered	T13,T54,T98
AutoCaptGenCnt->AutoSendGenCmd	150	Covered	T13,T14,T15
AutoCaptGenCnt->Error	188	Covered	T117,T118
AutoCaptGenCnt->Idle	211	Covered	T119,T120,T71
AutoCaptGenCnt->RejectCsrngEntropy	188	Covered	T85,T121,T122
AutoCaptReseedCnt->AutoSendReseedCmd	162	Covered	T13,T14,T15
AutoCaptReseedCnt->Error	188	Covered	T123
AutoCaptReseedCnt->Idle	211	Covered	T23,T124,T125
AutoCaptReseedCnt->RejectCsrngEntropy	188	Covered	T126,T127,T128
AutoDispatch->AutoCaptGenCnt	143	Covered	T85,T13,T14
AutoDispatch->AutoCaptReseedCnt	141	Covered	T13,T14,T15
AutoDispatch->Error	188	Covered	T129
AutoDispatch->Idle	138	Covered	T15,T22,T24
AutoDispatch->RejectCsrngEntropy	188	Covered	T9,T130,T131
AutoFirstAckWait->AutoDispatch	125	Covered	T9,T85,T13
AutoFirstAckWait->Error	188	Covered	T6,T132,T133
AutoFirstAckWait->Idle	211	Covered	T14,T134,T135
AutoFirstAckWait->RejectCsrngEntropy	188	Covered	T8,T112,T136
AutoLoadIns->AutoFirstAckWait	119	Covered	T8,T9,T85
AutoLoadIns->Error	188	Covered	T4,T137,T138
AutoLoadIns->Idle	211	Covered	T2,T4,T13
AutoLoadIns->RejectCsrngEntropy	188	Covered	T139,T140,T141
AutoSendGenCmd->AutoAckWait	156	Covered	T13,T14,T15
AutoSendGenCmd->Error	188	Covered	T59,T142
AutoSendGenCmd->Idle	211	Covered	T83,T143,T144
AutoSendGenCmd->RejectCsrngEntropy	188	Covered	T114,T145,T146
AutoSendReseedCmd->AutoAckWait	168	Covered	T13,T14,T15
AutoSendReseedCmd->Error	188	Covered	T147,T148
AutoSendReseedCmd->Idle	211	Covered	T149,T150,T151
AutoSendReseedCmd->RejectCsrngEntropy	188	Covered	T152,T115,T153
BootDone->BootLoadUni	102	Covered	T25,T9,T27
BootDone->Error	188	Covered	T154,T155,T156
BootDone->Idle	211	Covered	T60,T157,T158
BootDone->RejectCsrngEntropy	188	Covered	T49,T95,T159
BootGenAckWait->BootPulse	94	Covered	T25,T9,T27
BootGenAckWait->Error	188	Covered	T86,T160
BootGenAckWait->Idle	211	Covered	T97,T161,T162
BootGenAckWait->RejectCsrngEntropy	188	Covered	T2,T45,T163
BootInsAckWait->BootLoadGen	85	Covered	T2,T25,T9
BootInsAckWait->Error	188	Covered	T16,T60,T164
BootInsAckWait->Idle	211	Covered	T16,T47,T86
BootInsAckWait->RejectCsrngEntropy	188	Covered	T165,T116,T166
BootLoadGen->BootGenAckWait	90	Covered	T2,T25,T9
BootLoadGen->Error	188	Covered	T87,T167
BootLoadGen->Idle	211	Covered	T168,T169,T170
BootLoadGen->RejectCsrngEntropy	188	Covered	T171,T172,T173
BootLoadIns->BootInsAckWait	80	Covered	T2,T25,T9
BootLoadIns->Error	188	Covered	T174,T175,T176
BootLoadIns->Idle	211	Covered	T177
BootLoadIns->RejectCsrngEntropy	188	Covered	T178,T179,T180
BootLoadUni->BootUniAckWait	107	Covered	T25,T9,T27
BootLoadUni->Error	188	Covered	T181
BootLoadUni->Idle	211	Not Covered
BootLoadUni->RejectCsrngEntropy	188	Covered	T182,T183,T184
BootPulse->BootDone	98	Covered	T25,T9,T27
BootPulse->Error	188	Covered	T58,T64,T185
BootPulse->Idle	211	Covered	T186,T187,T188
BootPulse->RejectCsrngEntropy	188	Covered	T189,T190,T191
BootUniAckWait->Error	188	Covered	T192
BootUniAckWait->Idle	112	Covered	T25,T9,T27
BootUniAckWait->RejectCsrngEntropy	188	Covered	T46,T193,T194
Idle->AutoLoadIns	69	Covered	T2,T8,T9
Idle->BootLoadIns	65	Covered	T2,T25,T9
Idle->Error	188	Covered	T19,T20,T21
Idle->RejectCsrngEntropy	188	Covered	T8,T13,T54
Idle->SWPortMode	74	Covered	T1,T2,T3
RejectCsrngEntropy->Error	188	Covered	T195,T196,T197
RejectCsrngEntropy->Idle	211	Covered	T2,T8,T9
SWPortMode->Error	188	Covered	T37,T17,T88
SWPortMode->Idle	211	Covered	T1,T8,T56
SWPortMode->RejectCsrngEntropy	188	Covered	T2,T9,T85

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		42	41	97.62
IF	42	2	2	100.00
CASE	62	35	35	100.00
IF	186	5	4	80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	42	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	62	case (state_q)
-2-:	64	if ((boot_req_mode_i && edn_enable_i))
-3-:	66	if ((auto_req_mode_i && edn_enable_i))
-4-:	70	if (edn_enable_i)
-5-:	84	if (csrng_cmd_ack_i)
-6-:	93	if (csrng_cmd_ack_i)
-7-:	101	if ((!boot_req_mode_i))
-8-:	110	if (csrng_cmd_ack_i)
-9-:	118	if (sw_cmd_req_load_i)
-10-:	124	if (csrng_cmd_ack_i)
-11-:	130	if (csrng_cmd_ack_i)
-12-:	136	if ((!auto_req_mode_i))
-13-:	140	if (max_reqs_cnt_zero_i)
-14-:	155	if (cmd_sent_i)
-15-:	167	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T25,T9
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T8,T9
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T25,T9
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T2,T25,T9
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T2,T25,T9
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T25,T9
BootGenAckWait	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T2,T25,T9
BootGenAckWait	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T2,T25,T9
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T25,T9,T27
BootDone	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T25,T9,T27
BootDone	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T9,T45,T16
BootLoadUni	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T25,T9,T27
BootUniAckWait	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T25,T27,T44
BootUniAckWait	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T25,T9,T27
AutoLoadIns	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T8,T9,T85
AutoLoadIns	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T2,T8,T9
AutoFirstAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T8,T9,T85
AutoFirstAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T8,T9,T85
AutoAckWait	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T13,T14,T15
AutoAckWait	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T13,T14,T15
AutoDispatch	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T15,T22,T24
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T13,T14,T15
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T9,T85,T13
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T85,T13,T14
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T13,T14,T15
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T13,T14,T15
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T15
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T13,T14,T15
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T13,T14,T15
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
RejectCsrngEntropy	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T8,T9
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T37
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T7,T105

	LineNo.	Expression
-1-:	186	if ((local_escalate_i || csrng_ack_err_i))
-2-:	188	(local_escalate_i) ? 
-3-:	188	((state_q == Error)) ? 
-4-:	201	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy})))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T4,T5,T37
1	0	1	-	Not Covered
1	0	0	-	Covered	T2,T8,T9
0	-	-	1	Covered	T2,T8,T9
0	-	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	221344259	137711	0	0
FpvSecCmErrorStEscalate_A	221344259	138750	0	0
u_state_regs_A	221311686	221130475	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221344259	137711	0	0
T4	2376	1115	0	0
T5	1857	1094	0	0
T6	0	1174	0	0
T7	0	200	0	0
T16	0	413	0	0
T17	0	602	0	0
T34	731	0	0	0
T37	849	348	0	0
T40	387377	0	0	0
T55	1460	0	0	0
T56	25626	0	0	0
T57	13182	0	0	0
T84	1682	0	0	0
T85	2139	0	0	0
T86	0	610	0	0
T87	0	1098	0	0
T88	0	1148	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221344259	138750	0	0
T4	2376	1116	0	0
T5	1857	1095	0	0
T6	0	1175	0	0
T7	0	201	0	0
T16	0	414	0	0
T17	0	603	0	0
T34	731	0	0	0
T37	849	349	0	0
T40	387377	0	0	0
T55	1460	0	0	0
T56	25626	0	0	0
T57	13182	0	0	0
T84	1682	0	0	0
T85	2139	0	0	0
T86	0	611	0	0
T87	0	1099	0	0
T88	0	1149	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221311686	221130475	0	0
T1	22644	21893	0	0
T2	1827	1773	0	0
T3	1954	1896	0	0
T4	2209	2068	0	0
T5	1660	1542	0	0
T8	2901	2803	0	0
T9	2359	2269	0	0
T25	1673	1578	0	0
T26	1046	990	0	0
T27	3381	3304	0	0