Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T8,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T33,T38,T100
1	1	0	Not Covered
1	1	1	Covered	T2,T8,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T35,T39,T36
1	0	1	Covered	T2,T8,T9
1	1	0	Not Covered
1	1	1	Covered	T85,T13,T14

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	441954386	650072	0	0
DepthKnown_A	442688518	442326096	0	0
RvalidKnown_A	442688518	442326096	0	0
WreadyKnown_A	442688518	442326096	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	442305728	721326	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441954386	650072	0	0
T2	3654	299	0	0
T3	3908	0	0	0
T4	726	282	0	0
T5	178	0	0	0
T6	0	486	0	0
T8	5802	593	0	0
T9	4718	540	0	0
T13	0	1092	0	0
T14	0	3084	0	0
T15	0	1587	0	0
T22	0	4933	0	0
T25	3346	0	0	0
T26	2092	0	0	0
T27	6762	0	0	0
T56	51252	0	0	0
T85	0	474	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442688518	442326096	0	0
T1	45288	43786	0	0
T2	3654	3546	0	0
T3	3908	3792	0	0
T4	4752	4470	0	0
T5	3714	3478	0	0
T8	5802	5606	0	0
T9	4718	4538	0	0
T25	3346	3156	0	0
T26	2092	1980	0	0
T27	6762	6608	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442688518	442326096	0	0
T1	45288	43786	0	0
T2	3654	3546	0	0
T3	3908	3792	0	0
T4	4752	4470	0	0
T5	3714	3478	0	0
T8	5802	5606	0	0
T9	4718	4538	0	0
T25	3346	3156	0	0
T26	2092	1980	0	0
T27	6762	6608	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442688518	442326096	0	0
T1	45288	43786	0	0
T2	3654	3546	0	0
T3	3908	3792	0	0
T4	4752	4470	0	0
T5	3714	3478	0	0
T8	5802	5606	0	0
T9	4718	4538	0	0
T25	3346	3156	0	0
T26	2092	1980	0	0
T27	6762	6608	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	442305728	721326	0	0
T2	3654	299	0	0
T3	3908	0	0	0
T4	4752	1747	0	0
T5	3714	301	0	0
T8	5802	593	0	0
T9	4718	540	0	0
T13	0	1092	0	0
T14	0	3084	0	0
T16	0	2296	0	0
T17	0	220	0	0
T25	3346	0	0	0
T26	2092	0	0	0
T27	6762	0	0	0
T56	51252	0	0	0
T85	0	474	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T101,T33
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T8,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T33,T100
1	1	0	Not Covered
1	1	1	Covered	T2,T8,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T39,T102,T103
1	0	1	Covered	T2,T8,T9
1	1	0	Not Covered
1	1	1	Covered	T13,T14,T15

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	220977193	318739	0	0
DepthKnown_A	221344259	221163048	0	0
RvalidKnown_A	221344259	221163048	0	0
WreadyKnown_A	221344259	221163048	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	221152864	354385	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220977193	318739	0	0
T2	1827	137	0	0
T3	1954	0	0	0
T4	363	109	0	0
T5	89	0	0	0
T6	0	211	0	0
T8	2901	298	0	0
T9	2359	276	0	0
T13	0	515	0	0
T14	0	1532	0	0
T15	0	785	0	0
T22	0	2454	0	0
T25	1673	0	0	0
T26	1046	0	0	0
T27	3381	0	0	0
T56	25626	0	0	0
T85	0	240	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221344259	221163048	0	0
T1	22644	21893	0	0
T2	1827	1773	0	0
T3	1954	1896	0	0
T4	2376	2235	0	0
T5	1857	1739	0	0
T8	2901	2803	0	0
T9	2359	2269	0	0
T25	1673	1578	0	0
T26	1046	990	0	0
T27	3381	3304	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221344259	221163048	0	0
T1	22644	21893	0	0
T2	1827	1773	0	0
T3	1954	1896	0	0
T4	2376	2235	0	0
T5	1857	1739	0	0
T8	2901	2803	0	0
T9	2359	2269	0	0
T25	1673	1578	0	0
T26	1046	990	0	0
T27	3381	3304	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221344259	221163048	0	0
T1	22644	21893	0	0
T2	1827	1773	0	0
T3	1954	1896	0	0
T4	2376	2235	0	0
T5	1857	1739	0	0
T8	2901	2803	0	0
T9	2359	2269	0	0
T25	1673	1578	0	0
T26	1046	990	0	0
T27	3381	3304	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	221152864	354385	0	0
T2	1827	137	0	0
T3	1954	0	0	0
T4	2376	849	0	0
T5	1857	160	0	0
T8	2901	298	0	0
T9	2359	276	0	0
T13	0	515	0	0
T14	0	1532	0	0
T16	0	1156	0	0
T17	0	111	0	0
T25	1673	0	0	0
T26	1046	0	0	0
T27	3381	0	0	0
T56	25626	0	0	0
T85	0	240	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T8,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T38
1	1	0	Not Covered
1	1	1	Covered	T2,T8,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T35,T36,T104
1	0	1	Covered	T2,T8,T9
1	1	0	Not Covered
1	1	1	Covered	T85,T13,T14

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	220977193	331333	0	0
DepthKnown_A	221344259	221163048	0	0
RvalidKnown_A	221344259	221163048	0	0
WreadyKnown_A	221344259	221163048	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	221152864	366941	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220977193	331333	0	0
T2	1827	162	0	0
T3	1954	0	0	0
T4	363	173	0	0
T5	89	0	0	0
T6	0	275	0	0
T8	2901	295	0	0
T9	2359	264	0	0
T13	0	577	0	0
T14	0	1552	0	0
T15	0	802	0	0
T22	0	2479	0	0
T25	1673	0	0	0
T26	1046	0	0	0
T27	3381	0	0	0
T56	25626	0	0	0
T85	0	234	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221344259	221163048	0	0
T1	22644	21893	0	0
T2	1827	1773	0	0
T3	1954	1896	0	0
T4	2376	2235	0	0
T5	1857	1739	0	0
T8	2901	2803	0	0
T9	2359	2269	0	0
T25	1673	1578	0	0
T26	1046	990	0	0
T27	3381	3304	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221344259	221163048	0	0
T1	22644	21893	0	0
T2	1827	1773	0	0
T3	1954	1896	0	0
T4	2376	2235	0	0
T5	1857	1739	0	0
T8	2901	2803	0	0
T9	2359	2269	0	0
T25	1673	1578	0	0
T26	1046	990	0	0
T27	3381	3304	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221344259	221163048	0	0
T1	22644	21893	0	0
T2	1827	1773	0	0
T3	1954	1896	0	0
T4	2376	2235	0	0
T5	1857	1739	0	0
T8	2901	2803	0	0
T9	2359	2269	0	0
T25	1673	1578	0	0
T26	1046	990	0	0
T27	3381	3304	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	221152864	366941	0	0
T2	1827	162	0	0
T3	1954	0	0	0
T4	2376	898	0	0
T5	1857	141	0	0
T8	2901	295	0	0
T9	2359	264	0	0
T13	0	577	0	0
T14	0	1552	0	0
T16	0	1140	0	0
T17	0	109	0	0
T25	1673	0	0	0
T26	1046	0	0	0
T27	3381	0	0	0
T56	25626	0	0	0
T85	0	234	0	0