Unified Coverage Report :: Group :: tb.dut.u_edn_cov_if::edn_cfg_cg

Group : tb.dut.u_edn_cov_if::edn_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
edn_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : edn_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance edn_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	21	0	21	100.00

Variables for Group Instance edn_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mode	3	0	3	100.00	100	1	1	0
cp_num_boot_reqs	2	0	2	100.00	100	1	1	0
cp_num_endpoints	7	0	7	100.00	100	1	1	8

Crosses for Group Instance edn_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_num_endpoints_mode	21	0	21	100.00	100	1	1	0

Summary for Variable cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_mode

Excluded/Illegal bins

NAME	COUNT	STATUS
both	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
boot_req_mode	130	1			T24	1		T26	1		T50	1
auto_req_mode	134	1			T2	1		T11	1		T21	1
sw_mode	3048	1			T1	1		T23	1		T4	3

---

Summary for Variable cp_num_boot_reqs

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_boot_reqs

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

multiple

288

1

T2

1

T24

1

T26

1

single

112

1

T23

1

T27

1

T21

1

---

Summary for Variable cp_num_endpoints

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_num_endpoints

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	1359	1			T24	1		T4	3		T25	1
auto[2]	161	1			T23	1		T251	1		T52	1
auto[3]	225	1			T74	1		T79	25		T238	49
auto[4]	56	1			T50	1		T21	1		T83	20
auto[5]	190	1			T311	14		T312	1		T242	49
auto[6]	93	1			T95	1		T313	1		T314	1
auto[7]	1228	1			T1	1		T2	1		T27	1

---

Summary for Cross cr_num_endpoints_mode

Samples crossed: cp_num_endpoints cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	21	0	21	100.00

Automatically Generated Cross Bins for cr_num_endpoints_mode

Excluded/Illegal bins

cp_num_endpoints	cp_mode	COUNT	STATUS
[auto[0]]	[boot_req_mode , auto_req_mode , sw_mode]	--	Excluded	(3 bins)

Covered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	boot_req_mode	72	1			T24	1		T26	1		T64	1
auto[1]	auto_req_mode	80	1			T11	1		T22	1		T80	1
auto[1]	sw_mode	1207	1			T4	3		T25	1		T33	1
auto[2]	boot_req_mode	3	1			T251	1		T315	1		T316	1
auto[2]	auto_req_mode	5	1			T317	1		T318	1		T319	1
auto[2]	sw_mode	153	1			T23	1		T52	1		T241	40
auto[3]	boot_req_mode	4	1			T74	1		T320	1		T321	1
auto[3]	auto_req_mode	4	1			T322	1		T323	1		T324	1
auto[3]	sw_mode	217	1			T79	25		T238	49		T325	1
auto[4]	boot_req_mode	4	1			T50	1		T326	1		T327	1
auto[4]	auto_req_mode	6	1			T21	1		T328	1		T329	1
auto[4]	sw_mode	46	1			T83	20		T330	11		T331	10
auto[5]	boot_req_mode	2	1			T332	1		T333	1		-	-
auto[5]	auto_req_mode	2	1			T334	1		T335	1		-	-
auto[5]	sw_mode	186	1			T311	14		T312	1		T242	49
auto[6]	boot_req_mode	5	1			T313	1		T336	1		T337	1
auto[6]	auto_req_mode	1	1			T95	1		-	-		-	-
auto[6]	sw_mode	87	1			T314	1		T338	1		T339	1
auto[7]	boot_req_mode	40	1			T98	1		T340	1		T53	1
auto[7]	auto_req_mode	36	1			T2	1		T55	1		T341	1
auto[7]	sw_mode	1152	1			T1	1		T27	1		T58	1