Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	677362	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5383131

1

T1

12

T2

43

T3

45

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1612393	1			T1	25		T2	414		T3	27
values[0x0]	2056844	1			T1	4		T2	22		T3	24
values[0x1]	2391256	1			T1	5		T2	21		T3	27

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	338218	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5722275

1

T1

18

T2

192

T3

54

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	24126	1			T2	5		T27	1		T5	577
valid_sources[0x01]	22558	1			T1	1		T23	5		T27	1
valid_sources[0x02]	23376	1			T2	1		T27	1		T5	569
valid_sources[0x03]	22270	1			T27	1		T5	581		T58	2
valid_sources[0x04]	23032	1			T2	4		T23	8		T27	1
valid_sources[0x05]	24436	1			T1	1		T9	1		T27	1
valid_sources[0x06]	23997	1			T1	1		T2	2		T27	3
valid_sources[0x07]	24753	1			T3	2		T23	1		T9	1
valid_sources[0x08]	23068	1			T2	4		T5	576		T41	1
valid_sources[0x09]	23562	1			T2	2		T23	3		T5	604
valid_sources[0x0a]	23253	1			T2	1		T5	558		T97	2
valid_sources[0x0b]	22678	1			T2	5		T27	2		T5	603
valid_sources[0x0c]	23040	1			T5	581		T38	9		T51	4
valid_sources[0x0d]	22632	1			T2	5		T3	1		T5	611
valid_sources[0x0e]	24195	1			T1	2		T2	2		T3	5
valid_sources[0x0f]	23802	1			T5	609		T97	1		T38	2
valid_sources[0x10]	24161	1			T2	2		T4	20		T5	559
valid_sources[0x11]	23715	1			T1	1		T2	2		T5	614
valid_sources[0x12]	23837	1			T23	2		T5	546		T58	1
valid_sources[0x13]	25091	1			T2	2		T9	1		T5	598
valid_sources[0x14]	23580	1			T2	8		T5	617		T31	1
valid_sources[0x15]	23609	1			T24	5		T5	583		T18	1
valid_sources[0x16]	23365	1			T27	1		T5	632		T58	2
valid_sources[0x17]	24531	1			T2	4		T27	4		T5	604
valid_sources[0x18]	23312	1			T3	2		T23	3		T5	573
valid_sources[0x19]	24322	1			T27	2		T5	567		T10	2
valid_sources[0x1a]	23297	1			T9	1		T27	1		T5	580
valid_sources[0x1b]	27331	1			T2	1		T3	5		T4	19
valid_sources[0x1c]	23011	1			T1	1		T5	575		T18	3
valid_sources[0x1d]	23770	1			T2	4		T5	608		T11	1
valid_sources[0x1e]	22748	1			T4	8		T5	589		T86	1
valid_sources[0x1f]	24321	1			T1	1		T5	521		T31	3
valid_sources[0x20]	23162	1			T2	11		T27	1		T5	582
valid_sources[0x21]	23633	1			T2	4		T9	1		T27	1
valid_sources[0x22]	21728	1			T2	1		T27	1		T5	602
valid_sources[0x23]	24448	1			T2	2		T27	2		T5	567
valid_sources[0x24]	23795	1			T2	4		T27	2		T5	571
valid_sources[0x25]	23168	1			T5	581		T38	1		T11	5
valid_sources[0x26]	21609	1			T2	1		T23	2		T4	2
valid_sources[0x27]	23570	1			T27	1		T5	543		T97	1
valid_sources[0x28]	23733	1			T1	1		T3	3		T4	15
valid_sources[0x29]	24865	1			T2	3		T23	2		T5	635
valid_sources[0x2a]	24622	1			T5	530		T54	1		T55	30
valid_sources[0x2b]	23775	1			T2	3		T9	1		T27	2
valid_sources[0x2c]	23958	1			T5	641		T86	1		T38	2
valid_sources[0x2d]	23179	1			T1	1		T2	3		T5	614
valid_sources[0x2e]	23617	1			T2	2		T23	3		T27	1
valid_sources[0x2f]	22079	1			T27	1		T5	597		T10	1
valid_sources[0x30]	23809	1			T27	1		T5	587		T10	1
valid_sources[0x31]	23256	1			T2	3		T5	543		T38	1
valid_sources[0x32]	24714	1			T2	3		T5	612		T54	1
valid_sources[0x33]	23118	1			T1	1		T3	3		T5	635
valid_sources[0x34]	23064	1			T3	1		T5	567		T18	1
valid_sources[0x35]	21890	1			T2	1		T5	524		T97	1
valid_sources[0x36]	23420	1			T2	4		T26	1		T5	618
valid_sources[0x37]	23879	1			T4	4		T5	582		T97	1
valid_sources[0x38]	23980	1			T2	3		T26	1		T5	620
valid_sources[0x39]	24046	1			T1	1		T23	3		T9	2
valid_sources[0x3a]	24150	1			T2	4		T9	2		T27	1
valid_sources[0x3b]	22923	1			T2	3		T27	1		T5	521
valid_sources[0x3c]	23470	1			T1	1		T2	1		T5	596
valid_sources[0x3d]	23823	1			T3	1		T5	648		T22	1
valid_sources[0x3e]	23539	1			T2	5		T27	1		T5	579
valid_sources[0x3f]	24006	1			T1	1		T2	2		T5	595
valid_sources[0x40]	24192	1			T2	1		T5	542		T86	4
valid_sources[0x41]	24637	1			T2	13		T5	616		T38	1
valid_sources[0x42]	24099	1			T2	5		T4	9		T27	6
valid_sources[0x43]	24138	1			T2	2		T5	586		T86	7
valid_sources[0x44]	24315	1			T5	575		T18	11		T97	1
valid_sources[0x45]	23495	1			T5	584		T54	1		T32	2
valid_sources[0x46]	25310	1			T5	627		T86	1		T38	5
valid_sources[0x47]	22726	1			T27	1		T5	594		T18	1
valid_sources[0x48]	24246	1			T2	7		T5	571		T38	6
valid_sources[0x49]	23202	1			T5	612		T58	1		T38	3
valid_sources[0x4a]	22870	1			T1	1		T9	1		T27	2
valid_sources[0x4b]	24320	1			T27	1		T5	640		T58	1
valid_sources[0x4c]	24849	1			T2	4		T9	1		T25	66
valid_sources[0x4d]	23147	1			T2	1		T5	565		T18	1
valid_sources[0x4e]	23323	1			T23	1		T5	601		T38	2
valid_sources[0x4f]	22648	1			T27	3		T5	601		T38	3
valid_sources[0x50]	23604	1			T23	7		T27	1		T5	588
valid_sources[0x51]	24456	1			T2	1		T9	1		T5	622
valid_sources[0x52]	23888	1			T2	3		T27	1		T5	540
valid_sources[0x53]	23553	1			T27	1		T5	604		T38	3
valid_sources[0x54]	23277	1			T2	2		T27	1		T5	575
valid_sources[0x55]	23615	1			T9	1		T5	639		T38	3
valid_sources[0x56]	24364	1			T2	2		T5	588		T90	1
valid_sources[0x57]	22331	1			T2	5		T5	612		T38	6
valid_sources[0x58]	22830	1			T2	1		T27	1		T5	572
valid_sources[0x59]	23973	1			T1	1		T2	1		T9	2
valid_sources[0x5a]	24197	1			T2	4		T9	2		T27	1
valid_sources[0x5b]	22923	1			T27	1		T5	557		T97	1
valid_sources[0x5c]	22204	1			T2	2		T27	1		T5	594
valid_sources[0x5d]	26275	1			T2	1		T5	573		T97	1
valid_sources[0x5e]	23729	1			T2	8		T23	1		T5	621
valid_sources[0x5f]	23311	1			T2	3		T23	5		T27	1
valid_sources[0x60]	23516	1			T2	7		T5	603		T65	1
valid_sources[0x61]	23555	1			T23	1		T27	1		T5	621
valid_sources[0x62]	25115	1			T2	4		T4	2		T27	1
valid_sources[0x63]	24165	1			T5	629		T97	1		T28	2
valid_sources[0x64]	23003	1			T1	1		T2	2		T23	1
valid_sources[0x65]	23422	1			T2	2		T4	4		T5	518
valid_sources[0x66]	24122	1			T2	2		T3	2		T5	579
valid_sources[0x67]	23251	1			T2	3		T27	1		T5	565
valid_sources[0x68]	22830	1			T1	1		T2	2		T5	556
valid_sources[0x69]	23446	1			T2	7		T5	598		T38	2
valid_sources[0x6a]	21912	1			T2	1		T5	652		T38	3
valid_sources[0x6b]	24596	1			T2	1		T27	1		T5	615
valid_sources[0x6c]	24862	1			T1	2		T2	3		T5	601
valid_sources[0x6d]	23535	1			T1	1		T2	3		T5	594
valid_sources[0x6e]	22007	1			T2	2		T4	1		T27	1
valid_sources[0x6f]	23264	1			T5	590		T10	1		T38	1
valid_sources[0x70]	22607	1			T9	1		T5	620		T38	3
valid_sources[0x71]	24377	1			T27	2		T5	550		T97	1
valid_sources[0x72]	23802	1			T1	1		T2	3		T5	517
valid_sources[0x73]	24203	1			T5	538		T97	1		T38	2
valid_sources[0x74]	23464	1			T9	1		T5	536		T10	2
valid_sources[0x75]	23367	1			T1	1		T2	2		T3	1
valid_sources[0x76]	23056	1			T2	11		T5	556		T41	4
valid_sources[0x77]	24020	1			T2	1		T27	1		T5	649
valid_sources[0x78]	24580	1			T2	3		T27	1		T5	580
valid_sources[0x79]	23955	1			T2	1		T3	2		T9	1
valid_sources[0x7a]	25207	1			T3	36		T5	584		T58	1
valid_sources[0x7b]	23610	1			T27	1		T5	595		T90	1
valid_sources[0x7c]	23671	1			T5	492		T97	1		T31	1
valid_sources[0x7d]	25109	1			T2	2		T27	2		T5	594
valid_sources[0x7e]	22372	1			T2	5		T4	7		T5	589
valid_sources[0x7f]	21925	1			T23	5		T27	2		T5	631
valid_sources[0x80]	23312	1			T2	2		T9	1		T5	608

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1355682

1

T1

6

T2

4

T3

9

values[0x0]

all_enables

biggest_size

2013460

1

T1

3

T2

22

T3

17

values[0x1]

all_enables

biggest_size

2013989

1

T1

3

T2

17

T3

19