Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
60.94	60.94	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	60.94	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
60.94	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	25	27	51.92

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	25	27	51.92	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2796	1			T2	18		T27	1		T5	29
non_zero_bins[1]	1938	1			T23	3		T27	1		T5	30
zero	9782	1			T1	3		T2	4		T3	4

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	529	1			T23	1		T5	9		T97	1
uni	3907	1			T1	1		T2	1		T23	1
gen	4584	1			T1	1		T2	18		T3	2
res	842	1			T2	2		T5	8		T38	3
ins	4654	1			T1	1		T2	1		T3	2

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

9534

1

T1

3

T2

20

T3

1

mubi_true

4982

1

T2

2

T3

3

T24

1

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

18

1

T9

1

T111

1

T112

1

pass

14498

1

T1

3

T2

22

T3

4

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	25	27	51.92	25
Automatically Generated Cross Bins	52	25	27	51.92	25
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	4
[res , ins]	*	[fail]	*	--	--	12

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen]	[zero]	[fail]	[mubi_true]	0	1	1

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	124	1			T5	1		T38	1		T64	1
upd	non_zero_bins[0]	pass	mubi_true	128	1			T5	3		T97	1		T48	4
upd	non_zero_bins[1]	pass	mubi_false	95	1			T23	1		T5	1		T81	1
upd	non_zero_bins[1]	pass	mubi_true	80	1			T5	3		T66	1		T52	1
upd	zero	pass	mubi_false	42	1			T5	1		T38	1		T109	1
upd	zero	pass	mubi_true	60	1			T56	1		T51	1		T92	1
uni	zero	pass	mubi_false	2852	1			T1	1		T2	1		T23	1
uni	zero	pass	mubi_true	1055	1			T4	3		T27	1		T5	21
gen	non_zero_bins[0]	pass	mubi_false	494	1			T2	18		T5	7		T38	1
gen	non_zero_bins[0]	pass	mubi_true	546	1			T5	4		T58	1		T97	1
gen	non_zero_bins[1]	pass	mubi_false	389	1			T23	1		T5	5		T38	1
gen	non_zero_bins[1]	pass	mubi_true	340	1			T27	1		T5	3		T38	1
gen	zero	fail	mubi_false	18	1			T9	1		T111	1		T112	1
gen	zero	pass	mubi_false	2031	1			T1	1		T4	3		T25	1
gen	zero	pass	mubi_true	766	1			T3	2		T24	1		T9	2
res	non_zero_bins[0]	pass	mubi_false	187	1			T5	1		T21	2		T22	3
res	non_zero_bins[0]	pass	mubi_true	203	1			T5	2		T38	1		T66	1
res	non_zero_bins[1]	pass	mubi_false	124	1			T11	2		T22	1		T55	2
res	non_zero_bins[1]	pass	mubi_true	150	1			T5	3		T38	2		T109	1
res	zero	pass	mubi_false	89	1			T5	1		T48	1		T49	1
res	zero	pass	mubi_true	89	1			T2	2		T5	1		T108	1
ins	non_zero_bins[0]	pass	mubi_false	522	1			T27	1		T5	4		T38	3
ins	non_zero_bins[0]	pass	mubi_true	592	1			T5	7		T58	1		T90	1
ins	non_zero_bins[1]	pass	mubi_false	394	1			T23	1		T5	8		T50	1
ins	non_zero_bins[1]	pass	mubi_true	366	1			T5	7		T58	1		T97	1
ins	zero	pass	mubi_false	2173	1			T1	1		T2	1		T3	1
ins	zero	pass	mubi_true	607	1			T3	1		T9	1		T26	2

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded