Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.87	100.00	94.44		97.30	97.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	97.87	100.00	94.44		97.30	97.62	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.87	100.00	94.44		97.30	97.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.89	100.00	94.44		97.30	97.73	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		108	108	100.00
ALWAYS	42	3	3	100.00
CONT_ASSIGN	44	1	1	100.00
ALWAYS	47	104	104	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	3	3
44	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
78	1	1
79	1	1
80	1	1
83	1	1
84	1	1
85	1	1
			MISSING_ELSE
89	1	1
90	1	1
93	1	1
94	1	1
			MISSING_ELSE
98	1	1
101	1	1
102	1	1
			MISSING_ELSE
106	1	1
107	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
117	1	1
118	1	1
119	1	1
			MISSING_ELSE
123	1	1
124	1	1
125	1	1
			MISSING_ELSE
129	1	1
130	1	1
131	1	1
			MISSING_ELSE
135	1	1
136	1	1
137	1	1
138	1	1
140	1	1
141	1	1
143	1	1
148	1	1
149	1	1
150	1	1
153	1	1
154	1	1
155	1	1
156	1	1
			MISSING_ELSE
160	1	1
161	1	1
162	1	1
165	1	1
166	1	1
167	1	1
168	1	1
			MISSING_ELSE
172	1	1
175	1	1
178	1	1
186	1	1
188	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
211	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T24,T26,T15
1	1	Covered	T3,T24,T26

 LINE       66
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T31,T22
1	1	Covered	T2,T9,T18

 LINE       186
 EXPRESSION (local_escalate_i || csrng_ack_err_i)
             --------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T9,T41
1	0	Covered	T43,T15,T44

 LINE       188
 EXPRESSION (local_escalate_i ? Error : ((state_q == Error) ? Error : RejectCsrngEntropy))
             --------1-------

-1-	Status	Tests
0	Covered	T3,T9,T41
1	Covered	T43,T15,T44

 LINE       188
 SUB-EXPRESSION ((state_q == Error) ? Error : RejectCsrngEntropy)
                 ---------1--------

-1-	Status	Tests
0	Covered	T3,T9,T41
1	Not Covered

 LINE       188
 SUB-EXPRESSION (state_q == Error)
                ---------1--------

-1-	Status	Tests
0	Covered	T3,T9,T41
1	Covered	T43,T15,T44

 LINE       201
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T24,T9

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	20	100.00	(Not included in score)
Transitions	74	72	97.30
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	156	Covered	T2,T9,T11
AutoCaptGenCnt	143	Covered	T2,T9,T10
AutoCaptReseedCnt	141	Covered	T2,T11,T21
AutoDispatch	125	Covered	T2,T9,T10
AutoFirstAckWait	119	Covered	T2,T9,T10
AutoLoadIns	69	Covered	T2,T9,T18
AutoSendGenCmd	150	Covered	T2,T9,T11
AutoSendReseedCmd	162	Covered	T2,T11,T21
BootDone	98	Covered	T24,T26,T41
BootGenAckWait	90	Covered	T3,T24,T26
BootInsAckWait	80	Covered	T3,T24,T26
BootLoadGen	85	Covered	T3,T24,T26
BootLoadIns	65	Covered	T3,T24,T26
BootLoadUni	102	Covered	T41,T93,T94
BootPulse	94	Covered	T24,T26,T41
BootUniAckWait	107	Covered	T41,T93,T94
Error	188	Covered	T43,T15,T44
Idle	112	Covered	T1,T2,T3
RejectCsrngEntropy	188	Covered	T3,T9,T41
SWPortMode	74	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	131	Covered	T2,T11,T21
AutoAckWait->Error	188	Covered	T61,T125,T126
AutoAckWait->Idle	211	Covered	T22,T80,T85
AutoAckWait->RejectCsrngEntropy	188	Covered	T9,T111,T112
AutoCaptGenCnt->AutoSendGenCmd	150	Covered	T2,T9,T11
AutoCaptGenCnt->Error	188	Covered	T127,T128,T129
AutoCaptGenCnt->Idle	211	Covered	T130,T131,T132
AutoCaptGenCnt->RejectCsrngEntropy	188	Covered	T10,T133,T134
AutoCaptReseedCnt->AutoSendReseedCmd	162	Covered	T2,T11,T21
AutoCaptReseedCnt->Error	188	Covered	T135
AutoCaptReseedCnt->Idle	211	Covered	T136,T137,T138
AutoCaptReseedCnt->RejectCsrngEntropy	188	Covered	T139,T140,T141
AutoDispatch->AutoCaptGenCnt	143	Covered	T2,T9,T10
AutoDispatch->AutoCaptReseedCnt	141	Covered	T2,T11,T21
AutoDispatch->Error	188	Covered	T142,T143,T144
AutoDispatch->Idle	138	Covered	T2,T11,T21
AutoDispatch->RejectCsrngEntropy	188	Covered	T32,T145,T146
AutoFirstAckWait->AutoDispatch	125	Covered	T2,T9,T10
AutoFirstAckWait->Error	188	Covered	T8,T147
AutoFirstAckWait->Idle	211	Covered	T80,T148,T149
AutoFirstAckWait->RejectCsrngEntropy	188	Covered	T104,T150,T151
AutoLoadIns->AutoFirstAckWait	119	Covered	T2,T9,T10
AutoLoadIns->Error	188	Covered	T152,T153,T154
AutoLoadIns->Idle	211	Covered	T18,T10,T32
AutoLoadIns->RejectCsrngEntropy	188	Covered	T67,T155,T156
AutoSendGenCmd->AutoAckWait	156	Covered	T2,T9,T11
AutoSendGenCmd->Error	188	Covered	T157
AutoSendGenCmd->Idle	211	Covered	T22,T158,T159
AutoSendGenCmd->RejectCsrngEntropy	188	Covered	T160,T161,T162
AutoSendReseedCmd->AutoAckWait	168	Covered	T2,T11,T21
AutoSendReseedCmd->Error	188	Covered	T117,T163,T164
AutoSendReseedCmd->Idle	211	Covered	T85,T165,T166
AutoSendReseedCmd->RejectCsrngEntropy	188	Covered	T115,T167,T168
BootDone->BootLoadUni	102	Covered	T41,T93,T94
BootDone->Error	188	Covered	T59,T169,T170
BootDone->Idle	211	Covered	T171,T172,T173
BootDone->RejectCsrngEntropy	188	Covered	T41,T18,T91
BootGenAckWait->BootPulse	94	Covered	T24,T26,T41
BootGenAckWait->Error	188	Covered	T174,T175,T176
BootGenAckWait->Idle	211	Covered	T89,T177,T178
BootGenAckWait->RejectCsrngEntropy	188	Covered	T3,T179,T180
BootInsAckWait->BootLoadGen	85	Covered	T3,T24,T26
BootInsAckWait->Error	188	Covered	T87,T88,T63
BootInsAckWait->Idle	211	Covered	T24,T26,T15
BootInsAckWait->RejectCsrngEntropy	188	Covered	T31,T118,T119
BootLoadGen->BootGenAckWait	90	Covered	T3,T24,T26
BootLoadGen->Error	188	Covered	T17,T60,T181
BootLoadGen->Idle	211	Covered	T99,T182,T183
BootLoadGen->RejectCsrngEntropy	188	Covered	T93,T184,T185
BootLoadIns->BootInsAckWait	80	Covered	T3,T24,T26
BootLoadIns->Error	188	Covered	T15,T186,T62
BootLoadIns->Idle	211	Covered	T187,T188,T189
BootLoadIns->RejectCsrngEntropy	188	Covered	T190,T191,T101
BootLoadUni->BootUniAckWait	107	Covered	T41,T93,T94
BootLoadUni->Error	188	Not Covered
BootLoadUni->Idle	211	Not Covered
BootLoadUni->RejectCsrngEntropy	188	Covered	T192,T193,T194
BootPulse->BootDone	98	Covered	T24,T26,T41
BootPulse->Error	188	Covered	T195,T196
BootPulse->Idle	211	Covered	T197,T198,T199
BootPulse->RejectCsrngEntropy	188	Covered	T103,T200,T201
BootUniAckWait->Error	188	Covered	T202,T203,T204
BootUniAckWait->Idle	112	Covered	T41,T93,T50
BootUniAckWait->RejectCsrngEntropy	188	Covered	T94,T105,T205
Idle->AutoLoadIns	69	Covered	T2,T9,T18
Idle->BootLoadIns	65	Covered	T3,T24,T26
Idle->Error	188	Covered	T16,T19,T20
Idle->RejectCsrngEntropy	188	Covered	T18,T10,T93
Idle->SWPortMode	74	Covered	T1,T2,T3
RejectCsrngEntropy->Error	188	Covered	T75,T206,T207
RejectCsrngEntropy->Idle	211	Covered	T3,T9,T41
SWPortMode->Error	188	Covered	T68,T16,T73
SWPortMode->Idle	211	Covered	T1,T3,T9
SWPortMode->RejectCsrngEntropy	188	Covered	T3,T9,T41

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		42	41	97.62
IF	42	2	2	100.00
CASE	62	35	35	100.00
IF	186	5	4	80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	42	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	62	case (state_q)
-2-:	64	if ((boot_req_mode_i && edn_enable_i))
-3-:	66	if ((auto_req_mode_i && edn_enable_i))
-4-:	70	if (edn_enable_i)
-5-:	84	if (csrng_cmd_ack_i)
-6-:	93	if (csrng_cmd_ack_i)
-7-:	101	if ((!boot_req_mode_i))
-8-:	110	if (csrng_cmd_ack_i)
-9-:	118	if (sw_cmd_req_load_i)
-10-:	124	if (csrng_cmd_ack_i)
-11-:	130	if (csrng_cmd_ack_i)
-12-:	136	if ((!auto_req_mode_i))
-13-:	140	if (max_reqs_cnt_zero_i)
-14-:	155	if (cmd_sent_i)
-15-:	167	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T24,T26
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T9,T18
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T24,T26
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T24,T26
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T3,T24,T26
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T24,T26
BootGenAckWait	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T3,T24,T26
BootGenAckWait	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T3,T24,T26
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T24,T26,T41
BootDone	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T41,T93,T94
BootDone	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T24,T26,T41
BootLoadUni	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T41,T93,T94
BootUniAckWait	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T94,T50,T64
BootUniAckWait	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T41,T93,T94
AutoLoadIns	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T2,T9,T10
AutoLoadIns	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T2,T9,T18
AutoFirstAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T2,T9,T10
AutoFirstAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T9,T10
AutoAckWait	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T2,T9,T11
AutoAckWait	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T2,T9,T11
AutoDispatch	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T2,T11,T21
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T2,T11,T21
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T2,T9,T10
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T9,T10
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T2,T9,T11
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T2,T11,T21
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T11,T21
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T11,T21
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T11,T21
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
RejectCsrngEntropy	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T9,T41
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T43,T15,T44
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T43,T44,T6

	LineNo.	Expression
-1-:	186	if ((local_escalate_i || csrng_ack_err_i))
-2-:	188	(local_escalate_i) ? 
-3-:	188	((state_q == Error)) ? 
-4-:	201	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy})))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T43,T15,T44
1	0	1	-	Not Covered
1	0	0	-	Covered	T3,T9,T41
0	-	-	1	Covered	T3,T24,T9
0	-	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	209144438	142087	0	0
FpvSecCmErrorStEscalate_A	209144438	143258	0	0
u_state_regs_A	209111141	208922720	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	142087	0	0
T6	0	349	0	0
T15	0	641	0	0
T16	0	8703	0	0
T21	7929	0	0	0
T28	1255	0	0	0
T43	2281	1095	0	0
T44	0	1071	0	0
T50	2242	0	0	0
T51	1743	0	0	0
T54	2193	0	0	0
T56	2127	0	0	0
T68	0	358	0	0
T87	0	742	0	0
T88	0	256	0	0
T89	0	1088	0	0
T90	1895	0	0	0
T91	1626	0	0	0
T92	2511	0	0	0
T208	0	600	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	143258	0	0
T6	0	350	0	0
T15	0	642	0	0
T16	0	8833	0	0
T21	7929	0	0	0
T28	1255	0	0	0
T43	2281	1096	0	0
T44	0	1072	0	0
T50	2242	0	0	0
T51	1743	0	0	0
T54	2193	0	0	0
T56	2127	0	0	0
T68	0	359	0	0
T87	0	743	0	0
T88	0	257	0	0
T89	0	1089	0	0
T90	1895	0	0	0
T91	1626	0	0	0
T92	2511	0	0	0
T208	0	601	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209111141	208922720	0	0
T1	1897	1738	0	0
T2	2709	2658	0	0
T3	1995	1942	0	0
T4	6202	5972	0	0
T9	2442	2367	0	0
T23	4275	4177	0	0
T24	1389	1332	0	0
T25	1162	1070	0	0
T26	1093	1013	0	0
T27	2271	2198	0	0