Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T24,T9

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T2,T3
DataWait	75	Covered	T1,T2,T3
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T43,T15,T44
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T209,T210
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T2,T3
DataWait->AckPls	80	Covered	T1,T2,T3
DataWait->Disabled	107	Covered	T26,T22,T106
DataWait->Error	99	Covered	T44,T6,T75
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T19,T20
EndPointClear->Disabled	107	Covered	T1,T81,T211
EndPointClear->Error	99	Covered	T15,T89,T16
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T2,T3
Idle->Disabled	107	Covered	T3,T24,T9
Idle->Error	99	Covered	T43,T44,T68

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T2,T3
Idle	-	1	0	-	Covered	T1,T2,T3
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T2,T3
DataWait	-	-	-	0	Covered	T1,T2,T3
AckPls	-	-	-	-	Covered	T1,T2,T3
Error	-	-	-	-	Covered	T43,T15,T44
default	-	-	-	-	Covered	T68,T87,T88

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T43,T15,T44
0	1	Covered	T3,T24,T9
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	1464011066	1009259	0	0
FpvSecCmErrorStEscalate_A	1464011066	1017456	0	0
u_state_regs_A	1463977769	1462658822	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1464011066	1009259	0	0
T6	0	2793	0	0
T15	0	4487	0	0
T16	0	60921	0	0
T21	55503	0	0	0
T28	8785	0	0	0
T43	15967	8015	0	0
T44	0	7847	0	0
T50	15694	0	0	0
T51	12201	0	0	0
T54	15351	0	0	0
T56	14889	0	0	0
T68	0	2456	0	0
T87	0	5144	0	0
T88	0	1742	0	0
T89	0	7966	0	0
T90	13265	0	0	0
T91	11382	0	0	0
T92	17577	0	0	0
T208	0	4550	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1464011066	1017456	0	0
T6	0	2800	0	0
T15	0	4494	0	0
T16	0	61831	0	0
T21	55503	0	0	0
T28	8785	0	0	0
T43	15967	8022	0	0
T44	0	7854	0	0
T50	15694	0	0	0
T51	12201	0	0	0
T54	15351	0	0	0
T56	14889	0	0	0
T68	0	2463	0	0
T87	0	5151	0	0
T88	0	1749	0	0
T89	0	7973	0	0
T90	13265	0	0	0
T91	11382	0	0	0
T92	17577	0	0	0
T208	0	4557	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1463977769	1462658822	0	0
T1	13279	12166	0	0
T2	18963	18606	0	0
T3	13965	13594	0	0
T4	43414	41804	0	0
T9	17094	16569	0	0
T23	29925	29239	0	0
T24	9723	9324	0	0
T25	8134	7490	0	0
T26	7651	7091	0	0
T27	15897	15386	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T24,T9

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T27,T18,T31
DataWait	75	Covered	T27,T18,T31
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T43,T15,T44
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T27,T18,T31
DataWait->AckPls	80	Covered	T27,T18,T31
DataWait->Disabled	107	Covered	T212,T213
DataWait->Error	99	Covered	T206,T214,T207
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T19,T20
EndPointClear->Disabled	107	Covered	T1,T81,T211
EndPointClear->Error	99	Covered	T15,T89,T16
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T27,T18,T31
Idle->Disabled	107	Covered	T3,T24,T9
Idle->Error	99	Covered	T43,T44,T68

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T27,T18,T31
Idle	-	1	0	-	Covered	T27,T18,T31
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T27,T18,T31
DataWait	-	-	-	0	Covered	T27,T18,T31
AckPls	-	-	-	-	Covered	T27,T18,T31
Error	-	-	-	-	Covered	T43,T15,T44
default	-	-	-	-	Covered	T16,T19,T20

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T43,T15,T44
0	1	Covered	T3,T24,T9
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	209144438	144487	0	0
FpvSecCmErrorStEscalate_A	209144438	145658	0	0
u_state_regs_A	209144438	208956017	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	144487	0	0
T6	0	399	0	0
T15	0	641	0	0
T16	0	8703	0	0
T21	7929	0	0	0
T28	1255	0	0	0
T43	2281	1145	0	0
T44	0	1121	0	0
T50	2242	0	0	0
T51	1743	0	0	0
T54	2193	0	0	0
T56	2127	0	0	0
T68	0	358	0	0
T87	0	742	0	0
T88	0	256	0	0
T89	0	1138	0	0
T90	1895	0	0	0
T91	1626	0	0	0
T92	2511	0	0	0
T208	0	650	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	145658	0	0
T6	0	400	0	0
T15	0	642	0	0
T16	0	8833	0	0
T21	7929	0	0	0
T28	1255	0	0	0
T43	2281	1146	0	0
T44	0	1122	0	0
T50	2242	0	0	0
T51	1743	0	0	0
T54	2193	0	0	0
T56	2127	0	0	0
T68	0	359	0	0
T87	0	743	0	0
T88	0	257	0	0
T89	0	1139	0	0
T90	1895	0	0	0
T91	1626	0	0	0
T92	2511	0	0	0
T208	0	651	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	208956017	0	0
T1	1897	1738	0	0
T2	2709	2658	0	0
T3	1995	1942	0	0
T4	6202	5972	0	0
T9	2442	2367	0	0
T23	4275	4177	0	0
T24	1389	1332	0	0
T25	1162	1070	0	0
T26	1093	1013	0	0
T27	2271	2198	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T24,T9

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T18,T10,T50
DataWait	75	Covered	T18,T10,T50
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T43,T15,T44
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T18,T10,T50
DataWait->AckPls	80	Covered	T18,T10,T50
DataWait->Disabled	107	Covered	T99,T158,T215
DataWait->Error	99	Covered	T208,T60,T216
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T19,T20
EndPointClear->Disabled	107	Covered	T1,T81,T211
EndPointClear->Error	99	Covered	T15,T89,T16
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T18,T10,T50
Idle->Disabled	107	Covered	T3,T24,T9
Idle->Error	99	Covered	T43,T44,T68

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T18,T10,T50
Idle	-	1	0	-	Covered	T18,T10,T50
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T18,T10,T50
DataWait	-	-	-	0	Covered	T10,T50,T21
AckPls	-	-	-	-	Covered	T18,T10,T50
Error	-	-	-	-	Covered	T43,T15,T44
default	-	-	-	-	Covered	T16,T19,T20

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T43,T15,T44
0	1	Covered	T3,T24,T9
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	209144438	144487	0	0
FpvSecCmErrorStEscalate_A	209144438	145658	0	0
u_state_regs_A	209144438	208956017	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	144487	0	0
T6	0	399	0	0
T15	0	641	0	0
T16	0	8703	0	0
T21	7929	0	0	0
T28	1255	0	0	0
T43	2281	1145	0	0
T44	0	1121	0	0
T50	2242	0	0	0
T51	1743	0	0	0
T54	2193	0	0	0
T56	2127	0	0	0
T68	0	358	0	0
T87	0	742	0	0
T88	0	256	0	0
T89	0	1138	0	0
T90	1895	0	0	0
T91	1626	0	0	0
T92	2511	0	0	0
T208	0	650	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	145658	0	0
T6	0	400	0	0
T15	0	642	0	0
T16	0	8833	0	0
T21	7929	0	0	0
T28	1255	0	0	0
T43	2281	1146	0	0
T44	0	1122	0	0
T50	2242	0	0	0
T51	1743	0	0	0
T54	2193	0	0	0
T56	2127	0	0	0
T68	0	359	0	0
T87	0	743	0	0
T88	0	257	0	0
T89	0	1139	0	0
T90	1895	0	0	0
T91	1626	0	0	0
T92	2511	0	0	0
T208	0	651	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	208956017	0	0
T1	1897	1738	0	0
T2	2709	2658	0	0
T3	1995	1942	0	0
T4	6202	5972	0	0
T9	2442	2367	0	0
T23	4275	4177	0	0
T24	1389	1332	0	0
T25	1162	1070	0	0
T26	1093	1013	0	0
T27	2271	2198	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T24,T9

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T2,T27,T28
DataWait	75	Covered	T2,T27,T28
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T43,T15,T44
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T2,T27,T28
DataWait->AckPls	80	Covered	T2,T27,T28
DataWait->Disabled	107	Covered	T217,T218
DataWait->Error	99	Covered	T142,T219
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T19,T20
EndPointClear->Disabled	107	Covered	T1,T81,T211
EndPointClear->Error	99	Covered	T15,T89,T16
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T2,T27,T28
Idle->Disabled	107	Covered	T3,T24,T9
Idle->Error	99	Covered	T43,T44,T68

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T2,T27,T28
Idle	-	1	0	-	Covered	T2,T27,T28
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T2,T27,T28
DataWait	-	-	-	0	Covered	T2,T27,T56
AckPls	-	-	-	-	Covered	T2,T27,T28
Error	-	-	-	-	Covered	T43,T15,T44
default	-	-	-	-	Covered	T16,T19,T20

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T43,T15,T44
0	1	Covered	T3,T24,T9
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	209144438	144487	0	0
FpvSecCmErrorStEscalate_A	209144438	145658	0	0
u_state_regs_A	209144438	208956017	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	144487	0	0
T6	0	399	0	0
T15	0	641	0	0
T16	0	8703	0	0
T21	7929	0	0	0
T28	1255	0	0	0
T43	2281	1145	0	0
T44	0	1121	0	0
T50	2242	0	0	0
T51	1743	0	0	0
T54	2193	0	0	0
T56	2127	0	0	0
T68	0	358	0	0
T87	0	742	0	0
T88	0	256	0	0
T89	0	1138	0	0
T90	1895	0	0	0
T91	1626	0	0	0
T92	2511	0	0	0
T208	0	650	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	145658	0	0
T6	0	400	0	0
T15	0	642	0	0
T16	0	8833	0	0
T21	7929	0	0	0
T28	1255	0	0	0
T43	2281	1146	0	0
T44	0	1122	0	0
T50	2242	0	0	0
T51	1743	0	0	0
T54	2193	0	0	0
T56	2127	0	0	0
T68	0	359	0	0
T87	0	743	0	0
T88	0	257	0	0
T89	0	1139	0	0
T90	1895	0	0	0
T91	1626	0	0	0
T92	2511	0	0	0
T208	0	651	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	208956017	0	0
T1	1897	1738	0	0
T2	2709	2658	0	0
T3	1995	1942	0	0
T4	6202	5972	0	0
T9	2442	2367	0	0
T23	4275	4177	0	0
T24	1389	1332	0	0
T25	1162	1070	0	0
T26	1093	1013	0	0
T27	2271	2198	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T24,T9

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T2,T27,T51
DataWait	75	Covered	T2,T27,T51
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T43,T15,T44
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T2,T27,T51
DataWait->AckPls	80	Covered	T2,T27,T51
DataWait->Disabled	107	Covered	T22,T106,T130
DataWait->Error	99	Covered	T220,T129
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T19,T20
EndPointClear->Disabled	107	Covered	T1,T81,T211
EndPointClear->Error	99	Covered	T15,T89,T16
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T2,T27,T51
Idle->Disabled	107	Covered	T3,T24,T9
Idle->Error	99	Covered	T43,T44,T68

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T2,T27,T51
Idle	-	1	0	-	Covered	T2,T27,T51
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T2,T27,T51
DataWait	-	-	-	0	Covered	T2,T27,T51
AckPls	-	-	-	-	Covered	T2,T27,T51
Error	-	-	-	-	Covered	T43,T15,T44
default	-	-	-	-	Covered	T16,T19,T20

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T43,T15,T44
0	1	Covered	T3,T24,T9
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	209144438	144487	0	0
FpvSecCmErrorStEscalate_A	209144438	145658	0	0
u_state_regs_A	209144438	208956017	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	144487	0	0
T6	0	399	0	0
T15	0	641	0	0
T16	0	8703	0	0
T21	7929	0	0	0
T28	1255	0	0	0
T43	2281	1145	0	0
T44	0	1121	0	0
T50	2242	0	0	0
T51	1743	0	0	0
T54	2193	0	0	0
T56	2127	0	0	0
T68	0	358	0	0
T87	0	742	0	0
T88	0	256	0	0
T89	0	1138	0	0
T90	1895	0	0	0
T91	1626	0	0	0
T92	2511	0	0	0
T208	0	650	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	145658	0	0
T6	0	400	0	0
T15	0	642	0	0
T16	0	8833	0	0
T21	7929	0	0	0
T28	1255	0	0	0
T43	2281	1146	0	0
T44	0	1122	0	0
T50	2242	0	0	0
T51	1743	0	0	0
T54	2193	0	0	0
T56	2127	0	0	0
T68	0	359	0	0
T87	0	743	0	0
T88	0	257	0	0
T89	0	1139	0	0
T90	1895	0	0	0
T91	1626	0	0	0
T92	2511	0	0	0
T208	0	651	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	208956017	0	0
T1	1897	1738	0	0
T2	2709	2658	0	0
T3	1995	1942	0	0
T4	6202	5972	0	0
T9	2442	2367	0	0
T23	4275	4177	0	0
T24	1389	1332	0	0
T25	1162	1070	0	0
T26	1093	1013	0	0
T27	2271	2198	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T24,T9

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T2,T24,T27
DataWait	75	Covered	T2,T24,T27
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T43,T15,T44
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T2,T24,T27
DataWait->AckPls	80	Covered	T2,T24,T27
DataWait->Disabled	107	Covered	T24,T221,T222
DataWait->Error	99	Covered	T223,T224,T225
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T19,T20
EndPointClear->Disabled	107	Covered	T1,T81,T211
EndPointClear->Error	99	Covered	T15,T89,T16
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T2,T24,T27
Idle->Disabled	107	Covered	T3,T9,T4
Idle->Error	99	Covered	T43,T44,T68

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T2,T24,T27
Idle	-	1	0	-	Covered	T2,T24,T27
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T2,T24,T27
DataWait	-	-	-	0	Covered	T2,T24,T27
AckPls	-	-	-	-	Covered	T2,T24,T27
Error	-	-	-	-	Covered	T43,T15,T44
default	-	-	-	-	Covered	T16,T19,T20

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T43,T15,T44
0	1	Covered	T3,T24,T9
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	209144438	144487	0	0
FpvSecCmErrorStEscalate_A	209144438	145658	0	0
u_state_regs_A	209144438	208956017	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	144487	0	0
T6	0	399	0	0
T15	0	641	0	0
T16	0	8703	0	0
T21	7929	0	0	0
T28	1255	0	0	0
T43	2281	1145	0	0
T44	0	1121	0	0
T50	2242	0	0	0
T51	1743	0	0	0
T54	2193	0	0	0
T56	2127	0	0	0
T68	0	358	0	0
T87	0	742	0	0
T88	0	256	0	0
T89	0	1138	0	0
T90	1895	0	0	0
T91	1626	0	0	0
T92	2511	0	0	0
T208	0	650	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	145658	0	0
T6	0	400	0	0
T15	0	642	0	0
T16	0	8833	0	0
T21	7929	0	0	0
T28	1255	0	0	0
T43	2281	1146	0	0
T44	0	1122	0	0
T50	2242	0	0	0
T51	1743	0	0	0
T54	2193	0	0	0
T56	2127	0	0	0
T68	0	359	0	0
T87	0	743	0	0
T88	0	257	0	0
T89	0	1139	0	0
T90	1895	0	0	0
T91	1626	0	0	0
T92	2511	0	0	0
T208	0	651	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	208956017	0	0
T1	1897	1738	0	0
T2	2709	2658	0	0
T3	1995	1942	0	0
T4	6202	5972	0	0
T9	2442	2367	0	0
T23	4275	4177	0	0
T24	1389	1332	0	0
T25	1162	1070	0	0
T26	1093	1013	0	0
T27	2271	2198	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T24,T9

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T23,T9
DataWait	75	Covered	T1,T23,T9
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T43,T15,T44
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T209
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T23,T9
DataWait->AckPls	80	Covered	T1,T23,T9
DataWait->Disabled	107	Covered	T226,T227,T228
DataWait->Error	99	Covered	T17,T177,T7
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T19,T20
EndPointClear->Disabled	107	Covered	T1,T81,T211
EndPointClear->Error	99	Covered	T15,T89,T16
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T23,T9
Idle->Disabled	107	Covered	T3,T24,T9
Idle->Error	99	Covered	T43,T44,T6

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T23,T9
Idle	-	1	0	-	Covered	T1,T23,T9
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T23,T9
DataWait	-	-	-	0	Covered	T1,T23,T9
AckPls	-	-	-	-	Covered	T1,T23,T9
Error	-	-	-	-	Covered	T43,T15,T44
default	-	-	-	-	Covered	T68,T87,T88

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T43,T15,T44
0	1	Covered	T3,T24,T9
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	209144438	142337	0	0
FpvSecCmErrorStEscalate_A	209144438	143508	0	0
u_state_regs_A	209111141	208922720	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	142337	0	0
T6	0	399	0	0
T15	0	641	0	0
T16	0	8703	0	0
T21	7929	0	0	0
T28	1255	0	0	0
T43	2281	1145	0	0
T44	0	1121	0	0
T50	2242	0	0	0
T51	1743	0	0	0
T54	2193	0	0	0
T56	2127	0	0	0
T68	0	308	0	0
T87	0	692	0	0
T88	0	206	0	0
T89	0	1138	0	0
T90	1895	0	0	0
T91	1626	0	0	0
T92	2511	0	0	0
T208	0	650	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	143508	0	0
T6	0	400	0	0
T15	0	642	0	0
T16	0	8833	0	0
T21	7929	0	0	0
T28	1255	0	0	0
T43	2281	1146	0	0
T44	0	1122	0	0
T50	2242	0	0	0
T51	1743	0	0	0
T54	2193	0	0	0
T56	2127	0	0	0
T68	0	309	0	0
T87	0	693	0	0
T88	0	207	0	0
T89	0	1139	0	0
T90	1895	0	0	0
T91	1626	0	0	0
T92	2511	0	0	0
T208	0	651	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209111141	208922720	0	0
T1	1897	1738	0	0
T2	2709	2658	0	0
T3	1995	1942	0	0
T4	6202	5972	0	0
T9	2442	2367	0	0
T23	4275	4177	0	0
T24	1389	1332	0	0
T25	1162	1070	0	0
T26	1093	1013	0	0
T27	2271	2198	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T24,T9

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T2,T3,T23
DataWait	75	Covered	T2,T3,T23
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T43,T15,T44
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T210
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T2,T3,T23
DataWait->AckPls	80	Covered	T2,T3,T23
DataWait->Disabled	107	Covered	T26,T229,T178
DataWait->Error	99	Covered	T44,T6,T75
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T19,T20
EndPointClear->Disabled	107	Covered	T1,T81,T211
EndPointClear->Error	99	Covered	T15,T89,T16
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T2,T3,T23
Idle->Disabled	107	Covered	T3,T24,T9
Idle->Error	99	Covered	T43,T68,T87

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T2,T3,T23
Idle	-	1	0	-	Covered	T2,T3,T23
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T2,T3,T23
DataWait	-	-	-	0	Covered	T2,T3,T23
AckPls	-	-	-	-	Covered	T2,T3,T23
Error	-	-	-	-	Covered	T43,T15,T44
default	-	-	-	-	Covered	T16,T19,T20

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T43,T15,T44
0	1	Covered	T3,T24,T9
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	209144438	144487	0	0
FpvSecCmErrorStEscalate_A	209144438	145658	0	0
u_state_regs_A	209144438	208956017	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	144487	0	0
T6	0	399	0	0
T15	0	641	0	0
T16	0	8703	0	0
T21	7929	0	0	0
T28	1255	0	0	0
T43	2281	1145	0	0
T44	0	1121	0	0
T50	2242	0	0	0
T51	1743	0	0	0
T54	2193	0	0	0
T56	2127	0	0	0
T68	0	358	0	0
T87	0	742	0	0
T88	0	256	0	0
T89	0	1138	0	0
T90	1895	0	0	0
T91	1626	0	0	0
T92	2511	0	0	0
T208	0	650	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	145658	0	0
T6	0	400	0	0
T15	0	642	0	0
T16	0	8833	0	0
T21	7929	0	0	0
T28	1255	0	0	0
T43	2281	1146	0	0
T44	0	1122	0	0
T50	2242	0	0	0
T51	1743	0	0	0
T54	2193	0	0	0
T56	2127	0	0	0
T68	0	359	0	0
T87	0	743	0	0
T88	0	257	0	0
T89	0	1139	0	0
T90	1895	0	0	0
T91	1626	0	0	0
T92	2511	0	0	0
T208	0	651	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	208956017	0	0
T1	1897	1738	0	0
T2	2709	2658	0	0
T3	1995	1942	0	0
T4	6202	5972	0	0
T9	2442	2367	0	0
T23	4275	4177	0	0
T24	1389	1332	0	0
T25	1162	1070	0	0
T26	1093	1013	0	0
T27	2271	2198	0	0