Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.86	100.00	71.43			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	92.86	100.00	71.43			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	92.86	100.00	71.43			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.86	100.00	71.43			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.84	100.00	89.19	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.86	100.00	71.43			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.84	100.00	89.19	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	10	71.43
Logical	14	10	71.43
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T28,T29,T30
1	0	1	Covered	T2,T3,T9
1	1	0	Not Covered
1	1	1	Covered	T2,T9,T10

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	417581892	1023553	0	0
DepthKnown_A	418288876	417912034	0	0
RvalidKnown_A	418288876	417912034	0	0
WreadyKnown_A	418288876	417912034	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	417925544	1102845	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417581892	1023553	0	0
T2	5418	2047	0	0
T3	3990	69	0	0
T4	12404	0	0	0
T9	4884	481	0	0
T10	0	626	0	0
T11	0	3641	0	0
T18	0	129	0	0
T21	0	11313	0	0
T22	0	2564	0	0
T23	8550	0	0	0
T24	2778	0	0	0
T25	2324	0	0	0
T26	2186	0	0	0
T27	4542	0	0	0
T31	0	85	0	0
T32	0	810	0	0
T33	2508	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418288876	417912034	0	0
T1	3794	3476	0	0
T2	5418	5316	0	0
T3	3990	3884	0	0
T4	12404	11944	0	0
T9	4884	4734	0	0
T23	8550	8354	0	0
T24	2778	2664	0	0
T25	2324	2140	0	0
T26	2186	2026	0	0
T27	4542	4396	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418288876	417912034	0	0
T1	3794	3476	0	0
T2	5418	5316	0	0
T3	3990	3884	0	0
T4	12404	11944	0	0
T9	4884	4734	0	0
T23	8550	8354	0	0
T24	2778	2664	0	0
T25	2324	2140	0	0
T26	2186	2026	0	0
T27	4542	4396	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418288876	417912034	0	0
T1	3794	3476	0	0
T2	5418	5316	0	0
T3	3990	3884	0	0
T4	12404	11944	0	0
T9	4884	4734	0	0
T23	8550	8354	0	0
T24	2778	2664	0	0
T25	2324	2140	0	0
T26	2186	2026	0	0
T27	4542	4396	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	417925544	1102845	0	0
T2	5418	2047	0	0
T3	3990	69	0	0
T4	12404	0	0	0
T9	4884	481	0	0
T10	0	626	0	0
T11	0	3641	0	0
T15	0	262	0	0
T18	0	129	0	0
T21	0	11313	0	0
T22	0	2564	0	0
T23	8550	0	0	0
T24	2778	0	0	0
T25	2324	0	0	0
T26	2186	0	0	0
T27	4542	0	0	0
T31	0	85	0	0
T33	2508	0	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	10	71.43
Logical	14	10	71.43
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T22,T34,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T28,T29,T35
1	0	1	Covered	T2,T3,T9
1	1	0	Not Covered
1	1	1	Covered	T2,T11,T21

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	208790946	506228	0	0
DepthKnown_A	209144438	208956017	0	0
RvalidKnown_A	209144438	208956017	0	0
WreadyKnown_A	209144438	208956017	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	208962772	545473	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	208790946	506228	0	0
T2	2709	1010	0	0
T3	1995	31	0	0
T4	6202	0	0	0
T9	2442	242	0	0
T10	0	318	0	0
T11	0	1800	0	0
T18	0	31	0	0
T21	0	5641	0	0
T22	0	1271	0	0
T23	4275	0	0	0
T24	1389	0	0	0
T25	1162	0	0	0
T26	1093	0	0	0
T27	2271	0	0	0
T31	0	41	0	0
T32	0	361	0	0
T33	1254	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	208956017	0	0
T1	1897	1738	0	0
T2	2709	2658	0	0
T3	1995	1942	0	0
T4	6202	5972	0	0
T9	2442	2367	0	0
T23	4275	4177	0	0
T24	1389	1332	0	0
T25	1162	1070	0	0
T26	1093	1013	0	0
T27	2271	2198	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	208956017	0	0
T1	1897	1738	0	0
T2	2709	2658	0	0
T3	1995	1942	0	0
T4	6202	5972	0	0
T9	2442	2367	0	0
T23	4275	4177	0	0
T24	1389	1332	0	0
T25	1162	1070	0	0
T26	1093	1013	0	0
T27	2271	2198	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	208956017	0	0
T1	1897	1738	0	0
T2	2709	2658	0	0
T3	1995	1942	0	0
T4	6202	5972	0	0
T9	2442	2367	0	0
T23	4275	4177	0	0
T24	1389	1332	0	0
T25	1162	1070	0	0
T26	1093	1013	0	0
T27	2271	2198	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	208962772	545473	0	0
T2	2709	1010	0	0
T3	1995	31	0	0
T4	6202	0	0	0
T9	2442	242	0	0
T10	0	318	0	0
T11	0	1800	0	0
T15	0	132	0	0
T18	0	31	0	0
T21	0	5641	0	0
T22	0	1271	0	0
T23	4275	0	0	0
T24	1389	0	0	0
T25	1162	0	0	0
T26	1093	0	0	0
T27	2271	0	0	0
T31	0	41	0	0
T33	1254	0	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	10	71.43
Logical	14	10	71.43
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T30,T36,T37
1	0	1	Covered	T2,T3,T9
1	1	0	Not Covered
1	1	1	Covered	T2,T9,T10

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	208790946	517325	0	0
DepthKnown_A	209144438	208956017	0	0
RvalidKnown_A	209144438	208956017	0	0
WreadyKnown_A	209144438	208956017	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	208962772	557372	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	208790946	517325	0	0
T2	2709	1037	0	0
T3	1995	38	0	0
T4	6202	0	0	0
T9	2442	239	0	0
T10	0	308	0	0
T11	0	1841	0	0
T18	0	98	0	0
T21	0	5672	0	0
T22	0	1293	0	0
T23	4275	0	0	0
T24	1389	0	0	0
T25	1162	0	0	0
T26	1093	0	0	0
T27	2271	0	0	0
T31	0	44	0	0
T32	0	449	0	0
T33	1254	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	208956017	0	0
T1	1897	1738	0	0
T2	2709	2658	0	0
T3	1995	1942	0	0
T4	6202	5972	0	0
T9	2442	2367	0	0
T23	4275	4177	0	0
T24	1389	1332	0	0
T25	1162	1070	0	0
T26	1093	1013	0	0
T27	2271	2198	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	208956017	0	0
T1	1897	1738	0	0
T2	2709	2658	0	0
T3	1995	1942	0	0
T4	6202	5972	0	0
T9	2442	2367	0	0
T23	4275	4177	0	0
T24	1389	1332	0	0
T25	1162	1070	0	0
T26	1093	1013	0	0
T27	2271	2198	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209144438	208956017	0	0
T1	1897	1738	0	0
T2	2709	2658	0	0
T3	1995	1942	0	0
T4	6202	5972	0	0
T9	2442	2367	0	0
T23	4275	4177	0	0
T24	1389	1332	0	0
T25	1162	1070	0	0
T26	1093	1013	0	0
T27	2271	2198	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	208962772	557372	0	0
T2	2709	1037	0	0
T3	1995	38	0	0
T4	6202	0	0	0
T9	2442	239	0	0
T10	0	308	0	0
T11	0	1841	0	0
T15	0	130	0	0
T18	0	98	0	0
T21	0	5672	0	0
T22	0	1293	0	0
T23	4275	0	0	0
T24	1389	0	0	0
T25	1162	0	0	0
T26	1093	0	0	0
T27	2271	0	0	0
T31	0	44	0	0
T33	1254	0	0	0