Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	738726	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

6220490

1

T1

110267

T2

8

T3

25

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1817670	1			T1	30013		T2	23		T3	42
values[0x0]	2375904	1			T1	42280		T2	3		T3	14
values[0x1]	2765642	1			T1	49001		T2	4		T3	13

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	359376	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

6599840

1

T1

116558

T2

13

T3

40

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27834	1			T1	455		T11	4		T15	1
valid_sources[0x01]	25845	1			T1	389		T15	4		T40	2
valid_sources[0x02]	27379	1			T1	452		T15	4		T41	1
valid_sources[0x03]	25396	1			T1	492		T40	1		T50	1
valid_sources[0x04]	29779	1			T1	401		T15	1		T40	2
valid_sources[0x05]	27156	1			T1	444		T23	1		T15	2
valid_sources[0x06]	26526	1			T1	470		T40	1		T50	1
valid_sources[0x07]	28099	1			T1	501		T15	2		T12	1
valid_sources[0x08]	27419	1			T1	448		T15	3		T40	3
valid_sources[0x09]	29274	1			T1	495		T40	1		T41	1
valid_sources[0x0a]	27818	1			T1	439		T15	2		T49	1
valid_sources[0x0b]	25849	1			T1	524		T15	2		T41	1
valid_sources[0x0c]	26896	1			T1	458		T20	2		T40	1
valid_sources[0x0d]	25753	1			T1	414		T15	1		T40	6
valid_sources[0x0e]	26559	1			T1	407		T40	1		T41	1
valid_sources[0x0f]	27711	1			T1	433		T11	8		T12	1
valid_sources[0x10]	26434	1			T1	482		T10	1		T15	1
valid_sources[0x11]	26954	1			T1	531		T15	1		T12	2
valid_sources[0x12]	28249	1			T1	503		T22	12		T40	1
valid_sources[0x13]	28187	1			T1	486		T11	5		T15	2
valid_sources[0x14]	27367	1			T1	488		T10	1		T11	7
valid_sources[0x15]	26131	1			T1	442		T10	1		T15	3
valid_sources[0x16]	26861	1			T1	507		T4	1		T15	1
valid_sources[0x17]	26463	1			T1	465		T11	1		T15	1
valid_sources[0x18]	26776	1			T1	493		T20	1		T40	1
valid_sources[0x19]	26939	1			T1	452		T10	1		T15	3
valid_sources[0x1a]	26487	1			T1	514		T4	1		T15	2
valid_sources[0x1b]	26588	1			T1	508		T21	1		T10	3
valid_sources[0x1c]	26270	1			T1	416		T12	1		T40	5
valid_sources[0x1d]	27050	1			T1	493		T15	3		T12	1
valid_sources[0x1e]	28080	1			T1	471		T11	15		T15	1
valid_sources[0x1f]	25992	1			T1	435		T15	1		T93	1
valid_sources[0x20]	25943	1			T1	428		T12	1		T40	1
valid_sources[0x21]	27049	1			T1	473		T15	1		T5	1
valid_sources[0x22]	28718	1			T1	457		T10	1		T15	4
valid_sources[0x23]	26265	1			T1	497		T15	3		T40	4
valid_sources[0x24]	26046	1			T1	485		T65	1		T13	2
valid_sources[0x25]	25932	1			T1	491		T15	1		T40	1
valid_sources[0x26]	26607	1			T1	541		T40	2		T50	1
valid_sources[0x27]	27625	1			T1	510		T15	3		T49	1
valid_sources[0x28]	27208	1			T1	485		T10	1		T15	1
valid_sources[0x29]	27590	1			T1	417		T15	2		T65	1
valid_sources[0x2a]	29334	1			T1	521		T15	1		T40	2
valid_sources[0x2b]	28352	1			T1	464		T15	3		T20	2
valid_sources[0x2c]	26707	1			T1	464		T10	1		T15	2
valid_sources[0x2d]	28922	1			T1	462		T10	2		T11	2
valid_sources[0x2e]	26420	1			T1	458		T21	1		T10	1
valid_sources[0x2f]	26235	1			T1	450		T11	14		T15	1
valid_sources[0x30]	27063	1			T1	494		T15	1		T40	2
valid_sources[0x31]	26979	1			T1	465		T20	1		T12	2
valid_sources[0x32]	26732	1			T1	487		T15	1		T40	1
valid_sources[0x33]	28338	1			T1	424		T10	2		T63	1
valid_sources[0x34]	27456	1			T1	467		T40	1		T49	1
valid_sources[0x35]	26467	1			T1	504		T10	1		T15	1
valid_sources[0x36]	27602	1			T1	429		T15	1		T20	2
valid_sources[0x37]	28099	1			T1	432		T10	1		T49	1
valid_sources[0x38]	27980	1			T1	494		T4	1		T15	1
valid_sources[0x39]	28635	1			T1	500		T10	1		T15	3
valid_sources[0x3a]	26840	1			T1	454		T4	1		T40	2
valid_sources[0x3b]	27570	1			T1	428		T11	3		T20	1
valid_sources[0x3c]	26877	1			T1	450		T15	2		T12	1
valid_sources[0x3d]	27393	1			T1	481		T10	1		T15	1
valid_sources[0x3e]	27227	1			T1	471		T21	1		T40	1
valid_sources[0x3f]	25813	1			T1	406		T15	5		T40	1
valid_sources[0x40]	27140	1			T1	498		T15	4		T90	2
valid_sources[0x41]	26302	1			T1	500		T4	2		T15	1
valid_sources[0x42]	26146	1			T1	469		T10	1		T15	1
valid_sources[0x43]	28231	1			T1	494		T10	1		T11	4
valid_sources[0x44]	27518	1			T1	529		T10	1		T15	1
valid_sources[0x45]	26586	1			T1	522		T15	1		T5	1
valid_sources[0x46]	27459	1			T1	477		T15	1		T40	1
valid_sources[0x47]	27046	1			T1	463		T4	1		T15	5
valid_sources[0x48]	26451	1			T1	478		T20	1		T40	2
valid_sources[0x49]	27393	1			T1	444		T15	2		T40	1
valid_sources[0x4a]	26449	1			T1	494		T15	3		T40	2
valid_sources[0x4b]	26907	1			T1	454		T10	2		T15	3
valid_sources[0x4c]	28099	1			T1	422		T15	3		T12	1
valid_sources[0x4d]	27835	1			T1	541		T10	2		T11	4
valid_sources[0x4e]	26948	1			T1	471		T15	2		T40	1
valid_sources[0x4f]	27259	1			T1	475		T10	1		T15	2
valid_sources[0x50]	29710	1			T1	441		T15	1		T40	2
valid_sources[0x51]	27966	1			T1	459		T22	13		T10	1
valid_sources[0x52]	28486	1			T1	468		T15	1		T32	1
valid_sources[0x53]	27297	1			T1	460		T15	4		T40	3
valid_sources[0x54]	26958	1			T1	459		T10	1		T40	1
valid_sources[0x55]	26381	1			T1	473		T21	5		T15	1
valid_sources[0x56]	29794	1			T1	504		T15	1		T63	1
valid_sources[0x57]	27197	1			T1	461		T10	1		T23	1
valid_sources[0x58]	27493	1			T1	474		T15	4		T12	1
valid_sources[0x59]	27930	1			T1	440		T12	1		T41	1
valid_sources[0x5a]	26497	1			T1	482		T12	2		T41	2
valid_sources[0x5b]	26371	1			T1	532		T21	1		T10	2
valid_sources[0x5c]	27427	1			T1	474		T21	3		T15	1
valid_sources[0x5d]	25980	1			T1	491		T12	1		T40	3
valid_sources[0x5e]	26753	1			T1	495		T15	3		T40	2
valid_sources[0x5f]	26634	1			T1	508		T15	3		T12	3
valid_sources[0x60]	29207	1			T1	430		T40	1		T50	1
valid_sources[0x61]	27099	1			T1	520		T21	3		T10	1
valid_sources[0x62]	27385	1			T1	427		T63	1		T65	2
valid_sources[0x63]	25181	1			T1	526		T15	2		T65	1
valid_sources[0x64]	26861	1			T1	476		T15	3		T38	1
valid_sources[0x65]	27531	1			T1	488		T40	2		T49	1
valid_sources[0x66]	27984	1			T1	441		T15	4		T20	2
valid_sources[0x67]	25430	1			T1	490		T15	1		T20	1
valid_sources[0x68]	28410	1			T1	530		T10	1		T15	4
valid_sources[0x69]	25841	1			T1	467		T15	2		T12	1
valid_sources[0x6a]	27228	1			T1	521		T15	2		T12	1
valid_sources[0x6b]	26081	1			T1	452		T15	3		T40	4
valid_sources[0x6c]	26473	1			T1	458		T15	2		T90	4
valid_sources[0x6d]	27456	1			T1	424		T21	2		T15	1
valid_sources[0x6e]	26998	1			T1	549		T15	2		T40	2
valid_sources[0x6f]	28355	1			T1	474		T40	2		T50	1
valid_sources[0x70]	25933	1			T1	483		T15	2		T20	2
valid_sources[0x71]	27078	1			T1	448		T23	2		T15	1
valid_sources[0x72]	25939	1			T1	490		T10	1		T15	1
valid_sources[0x73]	28784	1			T1	485		T10	1		T15	1
valid_sources[0x74]	26689	1			T1	467		T15	2		T40	1
valid_sources[0x75]	25866	1			T1	484		T21	1		T40	2
valid_sources[0x76]	27184	1			T1	541		T40	3		T53	3
valid_sources[0x77]	28177	1			T1	450		T15	1		T40	3
valid_sources[0x78]	27879	1			T1	435		T10	1		T20	1
valid_sources[0x79]	26891	1			T1	421		T10	1		T15	1
valid_sources[0x7a]	26137	1			T1	482		T15	3		T20	2
valid_sources[0x7b]	25593	1			T1	535		T5	1		T40	3
valid_sources[0x7c]	26682	1			T1	496		T10	1		T15	2
valid_sources[0x7d]	29421	1			T1	447		T15	3		T12	1
valid_sources[0x7e]	27872	1			T1	482		T10	1		T15	2
valid_sources[0x7f]	27606	1			T1	412		T10	2		T15	3
valid_sources[0x80]	26744	1			T1	473		T15	4		T20	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1565015

1

T1

27678

T2

3

T3

2

values[0x0]

all_enables

biggest_size

2327686

1

T1

41528

T2

2

T3

13

values[0x1]

all_enables

biggest_size

2327789

1

T1

41061

T2

3

T3

10