Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
62.50	62.50	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	62.50	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	24	28	53.85

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	24	28	53.85	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2602	1			T1	11		T3	1		T9	4
non_zero_bins[1]	1941	1			T1	12		T3	1		T9	1
zero	9320	1			T1	45		T2	3		T3	6

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	506	1			T1	5		T24	1		T49	1
uni	3692	1			T1	22		T2	1		T3	3
gen	4375	1			T1	19		T2	1		T3	2
res	859	1			T9	2		T22	1		T11	2
ins	4431	1			T1	22		T2	1		T3	3

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

9101

1

T1

52

T2

3

T3

6

mubi_true

4762

1

T1

16

T3

2

T21

3

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

20

1

T41

1

T79

1

T238

1

pass

13843

1

T1

68

T2

3

T3

8

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	24	28	53.85	24
Automatically Generated Cross Bins	52	24	28	53.85	24
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	*	[fail]	*	--	--	6

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	116	1			T1	3		T35	4		T36	5
upd	non_zero_bins[0]	pass	mubi_true	127	1			T24	1		T56	1		T35	3
upd	non_zero_bins[1]	pass	mubi_false	77	1			T1	1		T35	1		T36	1
upd	non_zero_bins[1]	pass	mubi_true	91	1			T1	1		T49	1		T65	1
upd	zero	pass	mubi_false	39	1			T35	1		T76	1		T62	1
upd	zero	pass	mubi_true	56	1			T37	1		T42	1		T35	2
uni	zero	pass	mubi_false	2731	1			T1	16		T2	1		T3	3
uni	zero	pass	mubi_true	961	1			T1	6		T42	5		T35	22
gen	non_zero_bins[0]	pass	mubi_false	500	1			T1	1		T40	3		T35	8
gen	non_zero_bins[0]	pass	mubi_true	475	1			T1	4		T3	1		T9	3
gen	non_zero_bins[1]	pass	mubi_false	362	1			T1	2		T24	1		T15	9
gen	non_zero_bins[1]	pass	mubi_true	349	1			T1	1		T9	1		T12	1
gen	zero	fail	mubi_false	17	1			T41	1		T79	1		T238	1
gen	zero	pass	mubi_false	1924	1			T1	11		T2	1		T3	1
gen	zero	pass	mubi_true	748	1			T21	2		T22	2		T10	2
res	non_zero_bins[0]	pass	mubi_false	202	1			T50	6		T55	1		T13	2
res	non_zero_bins[0]	pass	mubi_true	196	1			T35	3		T36	1		T62	5
res	non_zero_bins[1]	pass	mubi_false	143	1			T22	1		T11	2		T15	2
res	non_zero_bins[1]	pass	mubi_true	147	1			T90	1		T42	1		T35	3
res	zero	fail	mubi_false	3	1			T140	1		T297	1		T298	1
res	zero	pass	mubi_false	93	1			T40	2		T66	1		T67	1
res	zero	pass	mubi_true	75	1			T9	2		T35	2		T62	2
ins	non_zero_bins[0]	pass	mubi_false	493	1			T1	3		T9	1		T22	1
ins	non_zero_bins[0]	pass	mubi_true	493	1			T49	1		T50	1		T65	1
ins	non_zero_bins[1]	pass	mubi_false	365	1			T1	4		T3	1		T24	1
ins	non_zero_bins[1]	pass	mubi_true	407	1			T1	3		T11	1		T56	1
ins	zero	pass	mubi_false	2036	1			T1	11		T2	1		T3	1
ins	zero	pass	mubi_true	637	1			T1	1		T3	1		T21	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded