SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.auto_req_mode | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.boot_req_mode | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.cmd_fifo_rst | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.edn_enable | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 31 | 1 | T186 | 2 | T312 | 2 | T292 | 2 | ||||
others[1] | 22 | 1 | T313 | 2 | T138 | 2 | T206 | 2 | ||||
others[2] | 30 | 1 | T75 | 2 | T91 | 2 | T95 | 2 | ||||
others[3] | 22 | 1 | T92 | 2 | T305 | 2 | T118 | 2 | ||||
false | 3531 | 1 | T2 | 1 | T3 | 2 | T21 | 11 | ||||
true | 754 | 1 | T9 | 1 | T10 | 1 | T11 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 10 | 1 | T159 | 2 | T314 | 2 | T177 | 2 | ||||
others[1] | 35 | 1 | T21 | 2 | T10 | 2 | T145 | 2 | ||||
others[2] | 22 | 1 | T53 | 2 | T188 | 2 | T227 | 2 | ||||
others[3] | 41 | 1 | T41 | 2 | T63 | 2 | T98 | 2 | ||||
false | 3674 | 1 | T2 | 1 | T3 | 1 | T21 | 8 | ||||
true | 608 | 1 | T3 | 1 | T21 | 1 | T22 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 12 | 1 | T97 | 1 | T105 | 1 | T230 | 1 | ||||
others[1] | 13 | 1 | T187 | 1 | T315 | 1 | T176 | 1 | ||||
others[2] | 16 | 1 | T93 | 1 | T69 | 1 | T123 | 1 | ||||
others[3] | 15 | 1 | T78 | 1 | T238 | 1 | T172 | 1 | ||||
false | 3503 | 1 | T2 | 1 | T3 | 2 | T21 | 9 | ||||
true | 831 | 1 | T21 | 2 | T9 | 1 | T10 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 21 | 1 | T146 | 2 | T130 | 2 | T316 | 2 | ||||
others[1] | 34 | 1 | T20 | 2 | T54 | 2 | T309 | 2 | ||||
others[2] | 16 | 1 | T308 | 2 | T317 | 2 | T307 | 2 | ||||
others[3] | 45 | 1 | T79 | 2 | T181 | 2 | T154 | 2 | ||||
false | 1927 | 1 | T21 | 5 | T9 | 2 | T10 | 5 | ||||
true | 2347 | 1 | T2 | 1 | T3 | 2 | T21 | 6 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |